Searched refs:Src1 (Results 1 - 25 of 52) sorted by relevance

123

/external/swiftshader/third_party/subzero/unittest/AssemblerX8664/
H A DControlFlow.cpp17 #define TestJ(C, Near, Dest, Src0, Value0, Src1, Value1) \
20 "(" #C ", " #Near ", " #Dest ", " #Src0 ", " #Value0 ", " #Src1 \
25 __ mov(IceType_i32, Encoded_GPR_##Src1(), Immediate(Value1)); \
27 __ cmp(IceType_i32, Encoded_GPR_##Src0(), Encoded_GPR_##Src1()); \
34 ASSERT_EQ(Value1, test.Src1()) << TestString; \
39 #define TestImpl(Dst, Src0, Src1) \
41 TestJ(o, Near, Dst, Src0, 0x80000000ul, Src1, 0x1ul); \
42 TestJ(o, Far, Dst, Src0, 0x80000000ul, Src1, 0x1ul); \
43 TestJ(no, Near, Dst, Src0, 0x1ul, Src1, 0x1ul); \
44 TestJ(no, Far, Dst, Src0, 0x1ul, Src1,
[all...]
H A DDataMov.cpp422 #define TestRegReg(C, Dest, IsTrue, Src0, Value0, Src1, Value1) \
425 "(" #C ", " #Dest ", " #IsTrue ", " #Src0 ", " #Value0 ", " #Src1 \
428 __ mov(IceType_i32, Encoded_GPR_##Src1(), Immediate(Value1)); \
430 __ cmp(IceType_i32, Encoded_GPR_##Src0(), Encoded_GPR_##Src1()); \
432 Encoded_GPR_##Src1()); \
462 #define TestValue(C, Dest, IsTrue, Src0, Value0, Src1, Value1) \
464 TestRegReg(C, Dest, IsTrue, Src0, Value0, Src1, Value1); \
468 #define TestImpl(Dest, Src0, Src1) \
470 TestValue(o, Dest, 1u, Src0, 0x80000000u, Src1, 0x1u); \
471 TestValue(o, Dest, 0u, Src0, 0x1u, Src1,
[all...]
H A DGPRArith.cpp33 #define TestSetCC(C, Dest, IsTrue, Src0, Value0, Src1, Value1) \
36 "(" #C ", " #Dest ", " #IsTrue ", " #Src0 ", " #Value0 ", " #Src1 \
41 __ mov(IceType_i32, Encoded_GPR_##Src1(), Immediate(Value1)); \
42 __ cmp(IceType_i32, Encoded_GPR_##Src0(), Encoded_GPR_##Src1()); \
57 #define TestImpl(Dest, Src0, Src1) \
59 TestSetCC(o, Dest, 1u, Src0, 0x80000000u, Src1, 0x1u); \
60 TestSetCC(o, Dest, 0u, Src0, 0x1u, Src1, 0x10000000u); \
61 TestSetCC(no, Dest, 1u, Src0, 0x1u, Src1, 0x10000000u); \
62 TestSetCC(no, Dest, 0u, Src0, 0x80000000u, Src1, 0x1u); \
63 TestSetCC(b, Dest, 1u, Src0, 0x1, Src1,
[all...]
/external/swiftshader/third_party/subzero/src/
H A DIceTargetLoweringMIPS32.h166 void _add(Variable *Dest, Variable *Src0, Variable *Src1) { argument
167 Context.insert<InstMIPS32Add>(Dest, Src0, Src1);
170 void _addu(Variable *Dest, Variable *Src0, Variable *Src1) { argument
171 Context.insert<InstMIPS32Addu>(Dest, Src0, Src1);
174 void _and(Variable *Dest, Variable *Src0, Variable *Src1) { argument
175 Context.insert<InstMIPS32And>(Dest, Src0, Src1);
189 Operand *Src1, CondMIPS32::Cond Condition) {
190 Context.insert<InstMIPS32Br>(TargetTrue, TargetFalse, Src0, Src1,
200 Operand *Src1, const InstMIPS32Label *Label,
202 Context.insert<InstMIPS32Br>(TargetTrue, TargetFalse, Src0, Src1, Labe
188 _br(CfgNode *TargetTrue, CfgNode *TargetFalse, Operand *Src0, Operand *Src1, CondMIPS32::Cond Condition) argument
199 _br(CfgNode *TargetTrue, CfgNode *TargetFalse, Operand *Src0, Operand *Src1, const InstMIPS32Label *Label, CondMIPS32::Cond Condition) argument
222 _add_d(Variable *Dest, Variable *Src0, Variable *Src1) argument
226 _add_s(Variable *Dest, Variable *Src0, Variable *Src1) argument
234 _addiu(Variable *Dest, Variable *Src0, Operand *Src1, RelocOp Reloc) argument
238 _c_eq_d(Variable *Src0, Variable *Src1) argument
242 _c_eq_s(Variable *Src0, Variable *Src1) argument
246 _c_ole_d(Variable *Src0, Variable *Src1) argument
250 _c_ole_s(Variable *Src0, Variable *Src1) argument
254 _c_olt_d(Variable *Src0, Variable *Src1) argument
258 _c_olt_s(Variable *Src0, Variable *Src1) argument
262 _c_ueq_d(Variable *Src0, Variable *Src1) argument
266 _c_ueq_s(Variable *Src0, Variable *Src1) argument
270 _c_ule_d(Variable *Src0, Variable *Src1) argument
274 _c_ule_s(Variable *Src0, Variable *Src1) argument
278 _c_ult_d(Variable *Src0, Variable *Src1) argument
282 _c_ult_s(Variable *Src0, Variable *Src1) argument
286 _c_un_d(Variable *Src0, Variable *Src1) argument
290 _c_un_s(Variable *Src0, Variable *Src1) argument
322 _div(Variable *Dest, Variable *Src0, Variable *Src1) argument
326 _div_d(Variable *Dest, Variable *Src0, Variable *Src1) argument
330 _div_s(Variable *Dest, Variable *Src0, Variable *Src1) argument
334 _divu(Variable *Dest, Variable *Src0, Variable *Src1) argument
418 _movn(Variable *Dest, Variable *Src0, Variable *Src1) argument
422 _movn_d(Variable *Dest, Variable *Src0, Variable *Src1) argument
426 _movn_s(Variable *Dest, Variable *Src0, Variable *Src1) argument
434 _movz(Variable *Dest, Variable *Src0, Variable *Src1) argument
438 _movz_d(Variable *Dest, Variable *Src0, Variable *Src1) argument
442 _movz_s(Variable *Dest, Variable *Src0, Variable *Src1) argument
458 _mul(Variable *Dest, Variable *Src0, Variable *Src1) argument
462 _mul_d(Variable *Dest, Variable *Src0, Variable *Src1) argument
466 _mul_s(Variable *Dest, Variable *Src0, Variable *Src1) argument
470 _mult(Variable *Dest, Variable *Src0, Variable *Src1) argument
474 _multu(Variable *Dest, Variable *Src0, Variable *Src1) argument
480 _nor(Variable *Dest, Variable *Src0, Variable *Src1) argument
488 _or(Variable *Dest, Variable *Src0, Variable *Src1) argument
508 _sllv(Variable *Dest, Variable *Src0, Variable *Src1) argument
512 _slt(Variable *Dest, Variable *Src0, Variable *Src1) argument
524 _sltu(Variable *Dest, Variable *Src0, Variable *Src1) argument
540 _srav(Variable *Dest, Variable *Src0, Variable *Src1) argument
548 _srlv(Variable *Dest, Variable *Src0, Variable *Src1) argument
552 _sub(Variable *Dest, Variable *Src0, Variable *Src1) argument
556 _sub_d(Variable *Dest, Variable *Src0, Variable *Src1) argument
560 _sub_s(Variable *Dest, Variable *Src0, Variable *Src1) argument
564 _subu(Variable *Dest, Variable *Src0, Variable *Src1) argument
578 _teq(Variable *Src0, Variable *Src1, uint32_t TrapCode) argument
598 _xor(Variable *Dest, Variable *Src0, Variable *Src1) argument
[all...]
H A DIceTargetLoweringARM32.h213 Operand *Src0, Operand *Src1);
253 Operand *Src0, Operand *Src1);
255 Operand *Src1);
257 Operand *Src1);
259 Operand *Src1);
326 void lowerIDivRem(Variable *Dest, Variable *T, Variable *Src0R, Operand *Src1,
334 void _add(Variable *Dest, Variable *Src0, Operand *Src1, argument
336 Context.insert<InstARM32Add>(Dest, Src0, Src1, Pred);
338 void _adds(Variable *Dest, Variable *Src0, Operand *Src1, argument
341 Context.insert<InstARM32Add>(Dest, Src0, Src1, Pre
346 _adc(Variable *Dest, Variable *Src0, Operand *Src1, CondARM32::Cond Pred = CondARM32::AL) argument
350 _and(Variable *Dest, Variable *Src0, Operand *Src1, CondARM32::Cond Pred = CondARM32::AL) argument
354 _asr(Variable *Dest, Variable *Src0, Operand *Src1, CondARM32::Cond Pred = CondARM32::AL) argument
358 _bic(Variable *Dest, Variable *Src0, Operand *Src1, CondARM32::Cond Pred = CondARM32::AL) argument
373 _cmn(Variable *Src0, Operand *Src1, CondARM32::Cond Pred = CondARM32::AL) argument
377 _cmp(Variable *Src0, Operand *Src1, CondARM32::Cond Pred = CondARM32::AL) argument
386 _eor(Variable *Dest, Variable *Src0, Operand *Src1, CondARM32::Cond Pred = CondARM32::AL) argument
407 _lsl(Variable *Dest, Variable *Src0, Operand *Src1, CondARM32::Cond Pred = CondARM32::AL) argument
411 _lsls(Variable *Dest, Variable *Src0, Operand *Src1, CondARM32::Cond Pred = CondARM32::AL) argument
419 _lsr(Variable *Dest, Variable *Src0, Operand *Src1, CondARM32::Cond Pred = CondARM32::AL) argument
423 _mla(Variable *Dest, Variable *Src0, Variable *Src1, Variable *Acc, CondARM32::Cond Pred = CondARM32::AL) argument
427 _mls(Variable *Dest, Variable *Src0, Variable *Src1, Variable *Acc, CondARM32::Cond Pred = CondARM32::AL) argument
718 _mul(Variable *Dest, Variable *Src0, Variable *Src1, CondARM32::Cond Pred = CondARM32::AL) argument
726 _orr(Variable *Dest, Variable *Src0, Operand *Src1, CondARM32::Cond Pred = CondARM32::AL) argument
730 _orrs(Variable *Dest, Variable *Src0, Operand *Src1, CondARM32::Cond Pred = CondARM32::AL) argument
756 _rscs(Variable *Dest, Variable *Src0, Operand *Src1, CondARM32::Cond Pred = CondARM32::AL) argument
764 _rsc(Variable *Dest, Variable *Src0, Operand *Src1, CondARM32::Cond Pred = CondARM32::AL) argument
768 _rsbs(Variable *Dest, Variable *Src0, Operand *Src1, CondARM32::Cond Pred = CondARM32::AL) argument
776 _rsb(Variable *Dest, Variable *Src0, Operand *Src1, CondARM32::Cond Pred = CondARM32::AL) argument
780 _sbc(Variable *Dest, Variable *Src0, Operand *Src1, CondARM32::Cond Pred = CondARM32::AL) argument
784 _sbcs(Variable *Dest, Variable *Src0, Operand *Src1, CondARM32::Cond Pred = CondARM32::AL) argument
792 _sdiv(Variable *Dest, Variable *Src0, Variable *Src1, CondARM32::Cond Pred = CondARM32::AL) argument
810 _sub(Variable *Dest, Variable *Src0, Operand *Src1, CondARM32::Cond Pred = CondARM32::AL) argument
814 _subs(Variable *Dest, Variable *Src0, Operand *Src1, CondARM32::Cond Pred = CondARM32::AL) argument
826 _tst(Variable *Src0, Operand *Src1, CondARM32::Cond Pred = CondARM32::AL) argument
831 _udiv(Variable *Dest, Variable *Src0, Variable *Src1, CondARM32::Cond Pred = CondARM32::AL) argument
835 _umull(Variable *DestLo, Variable *DestHi, Variable *Src0, Variable *Src1, CondARM32::Cond Pred = CondARM32::AL) argument
855 _vadd(Variable *Dest, Variable *Src0, Variable *Src1) argument
858 _vand(Variable *Dest, Variable *Src0, Variable *Src1) argument
861 _vbsl(Variable *Dest, Variable *Src0, Variable *Src1) argument
864 _vceq(Variable *Dest, Variable *Src0, Variable *Src1) argument
867 _vcge(Variable *Dest, Variable *Src0, Variable *Src1) argument
870 _vcgt(Variable *Dest, Variable *Src0, Variable *Src1) argument
877 _vdiv(Variable *Dest, Variable *Src0, Variable *Src1) argument
880 _vcmp(Variable *Src0, Variable *Src1, CondARM32::Cond Pred = CondARM32::AL) argument
888 _veor(Variable *Dest, Variable *Src0, Variable *Src1) argument
894 _vmla(Variable *Dest, Variable *Src0, Variable *Src1) argument
897 _vmls(Variable *Dest, Variable *Src0, Variable *Src1) argument
900 _vmul(Variable *Dest, Variable *Src0, Variable *Src1) argument
910 _vorr(Variable *Dest, Variable *Src0, Variable *Src1) argument
913 _vshl(Variable *Dest, Variable *Src0, Variable *Src1) argument
916 _vshl(Variable *Dest, Variable *Src0, ConstantInteger32 *Src1) argument
920 _vshr(Variable *Dest, Variable *Src0, ConstantInteger32 *Src1) argument
928 _vsub(Variable *Dest, Variable *Src0, Variable *Src1) argument
[all...]
H A DIceTargetLoweringX86Base.h419 Operand *legalizeSrc0ForCmp(Operand *Src0, Operand *Src1);
520 void _adc_rmw(X86OperandMem *DestSrc0, Operand *Src1) { argument
521 AutoMemorySandboxer<> _(this, &DestSrc0, &Src1);
522 Context.insert<typename Traits::Insts::AdcRMW>(DestSrc0, Src1);
528 void _add_rmw(X86OperandMem *DestSrc0, Operand *Src1) { argument
529 AutoMemorySandboxer<> _(this, &DestSrc0, &Src1);
530 Context.insert<typename Traits::Insts::AddRMW>(DestSrc0, Src1);
555 void _and_rmw(X86OperandMem *DestSrc0, Operand *Src1) { argument
556 AutoMemorySandboxer<> _(this, &DestSrc0, &Src1);
557 Context.insert<typename Traits::Insts::AndRMW>(DestSrc0, Src1);
559 _blendvps(Variable *Dest, Operand *Src0, Operand *Src1) argument
597 _cmp(Operand *Src0, Operand *Src1) argument
637 _div(Variable *Dest, Operand *Src0, Operand *Src1) argument
671 _idiv(Variable *Dest, Operand *Src0, Operand *Src1) argument
683 _insertps(Variable *Dest, Operand *Src0, Operand *Src1) argument
758 _mul(Variable *Dest, Variable *Src0, Operand *Src1) argument
785 _or_rmw(X86OperandMem *DestSrc0, Operand *Src1) argument
809 _pblendvb(Variable *Dest, Operand *Src0, Operand *Src1) argument
823 _pextr(Variable *Dest, Operand *Src0, Operand *Src1) argument
827 _pinsr(Variable *Dest, Operand *Src0, Operand *Src1) argument
878 _pshufd(Variable *Dest, Operand *Src0, Operand *Src1) argument
936 _sbb_rmw(X86OperandMem *DestSrc0, Operand *Src1) argument
947 _shld(Variable *Dest, Variable *Src0, Operand *Src1) argument
955 _shrd(Variable *Dest, Variable *Src0, Operand *Src1) argument
959 _shufps(Variable *Dest, Operand *Src0, Operand *Src1) argument
991 _sub_rmw(X86OperandMem *DestSrc0, Operand *Src1) argument
1006 _test(Operand *Src0, Operand *Src1) argument
1010 _ucomiss(Operand *Src0, Operand *Src1) argument
1042 _xor_rmw(X86OperandMem *DestSrc0, Operand *Src1) argument
[all...]
H A DIceTargetLoweringX86BaseImpl.h802 /// Replaces Src0 or Src1 with LoadSrc if the answer is true.
804 Operand *&Src0, Operand *&Src1) {
805 if (Src0 == LoadDest && Src1 != LoadDest) {
809 if (Src0 != LoadDest && Src1 == LoadDest) {
810 Src1 = LoadSrc;
856 Operand *Src1 = Arith->getSrc(1); local
857 if (canFoldLoadIntoBinaryInst(LoadSrc, LoadDest, Src0, Src1)) {
859 Arith->getDest(), Src0, Src1);
863 Operand *Src1 = Icmp->getSrc(1); local
864 if (canFoldLoadIntoBinaryInst(LoadSrc, LoadDest, Src0, Src1)) {
803 canFoldLoadIntoBinaryInst(Operand *LoadSrc, Variable *LoadDest, Operand *&Src0, Operand *&Src1) argument
870 Operand *Src1 = Fcmp->getSrc(1); local
877 Operand *Src1 = Select->getFalseOperand(); local
1615 optimizeScalarMul(Variable *Dest, Operand *Src0, int32_t Src1) argument
1932 Operand *Src1 = legalize(Instr->getSrc(1)); local
3337 Operand *Src1 = Fcmp->getSrc(1); local
3442 Operand *Src1 = Fcmp->getSrc(1); local
3515 Operand *Src1 = legalize(Icmp->getSrc(1)); local
3552 Operand *Src1 = legalize(Icmp->getSrc(1)); local
3672 Operand *Src1 = legalize(Icmp->getSrc(1)); local
[all...]
H A DIceInstMIPS32.h497 /// Create an ordinary binary-op instruction like add, and sub. Dest and Src1
500 Variable *Src0, Variable *Src1) {
502 InstMIPS32ThreeAddrFPR(Func, Dest, Src0, Src1);
528 Variable *Src1)
531 addSource(Src1);
546 /// Create an ordinary binary-op instruction like add, and sub. Dest and Src1
549 Variable *Src0, Variable *Src1) {
551 InstMIPS32ThreeAddrGPR(Func, Dest, Src0, Src1);
577 Variable *Src1)
580 addSource(Src1);
499 create(Cfg *Func, Variable *Dest, Variable *Src0, Variable *Src1) argument
527 InstMIPS32ThreeAddrFPR(Cfg *Func, Variable *Dest, Variable *Src0, Variable *Src1) argument
548 create(Cfg *Func, Variable *Dest, Variable *Src0, Variable *Src1) argument
576 InstMIPS32ThreeAddrGPR(Cfg *Func, Variable *Dest, Variable *Src0, Variable *Src1) argument
819 create(Cfg *Func, CfgNode *TargetTrue, CfgNode *TargetFalse, Operand *Src0, Operand *Src1, CondMIPS32::Cond Cond) argument
835 create(Cfg *Func, CfgNode *TargetTrue, CfgNode *TargetFalse, Operand *Src0, Operand *Src1, const InstMIPS32Label *Label, CondMIPS32::Cond Cond) argument
903 create(Cfg *Func, Variable *Src0, Variable *Src1) argument
937 InstMIPS32FPCmp(Cfg *Func, Variable *Src0, Variable *Src1) argument
988 create(Cfg *Func, Operand *Src0, Operand *Src1, uint32_t Tcode) argument
1025 InstMIPS32Trap(Cfg *Func, Operand *Src0, Operand *Src1, const uint32_t Tcode) argument
1054 create(Cfg *Func, Variable *Dest, Operand *Src0, Operand *Src1, RelocOp Reloc) argument
1129 InstMIPS32Imm16(Cfg *Func, Variable *Dest, Operand *Src0, Operand *Src1, RelocOp Reloc = RO_No) argument
[all...]
H A DIceTargetLoweringARM32.cpp542 Operand *Src1 = Instr->getSrc(1); local
544 // Src0 and Src1 have to be zero-, or signed-extended to i32. For Src0,
550 // For extending Src1, we will just insert an InstCast if Src1 is not a
554 if (auto *C = llvm::dyn_cast<ConstantInteger32>(Src1)) {
562 Src1 = Ctx->getConstantInt32(NewC);
565 Context.insert<InstCast>(CastKind, Src1_32, Src1);
566 Src1 = Src1_32;
576 assert(Src1->getType() == IceType_i32);
577 Call->addArg(Src1);
2322 lowerIDivRem(Variable *Dest, Variable *T, Variable *Src0R, Operand *Src1, ExtInstr ExtFunc, DivInstr DivFunc, bool IsRemainder) argument
2361 Operand *Src1 = Instr->getSrc(1); local
2447 Operand *const Src1; member in class:__anon20705::NumericOperandsBase
2555 Operand *Src1 = Instr->getArg(1); local
2585 lowerInt64Arithmetic(InstArithmetic::OpKind Op, Variable *Dest, Operand *Src0, Operand *Src1) argument
[all...]
H A DIceInstARM32.h729 /// Create an ordinary binary-op instruction like add, and sub. Dest and Src1
732 Variable *Src0, Operand *Src1,
736 InstARM32ThreeAddrGPR(Func, Dest, Src0, Src1, Predicate, SetFlags);
758 Operand *Src1, CondARM32::Cond Predicate, bool SetFlags)
762 addSource(Src1);
783 Variable *Src1) {
785 InstARM32ThreeAddrFP(Func, Dest, Src0, Src1);
808 InstARM32ThreeAddrFP(Cfg *Func, Variable *Dest, Variable *Src0, Operand *Src1) argument
811 addSource(Src1);
833 Variable *Src0, Variable *Src1) {
731 create(Cfg *Func, Variable *Dest, Variable *Src0, Operand *Src1, CondARM32::Cond Predicate, bool SetFlags = false) argument
757 InstARM32ThreeAddrGPR(Cfg *Func, Variable *Dest, Variable *Src0, Operand *Src1, CondARM32::Cond Predicate, bool SetFlags) argument
782 create(Cfg *Func, Variable *Dest, Variable *Src0, Variable *Src1) argument
832 create(Cfg *Func, Variable *Dest, Variable *Src0, Variable *Src1) argument
839 create(Cfg *Func, Variable *Dest, Variable *Src0, ConstantInteger32 *Src1) argument
848 InstARM32ThreeAddrSignAwareFP(Cfg *Func, Variable *Dest, Variable *Src0, Operand *Src1) argument
862 create(Cfg *Func, Variable *Dest, Variable *Src0, Variable *Src1, Variable *Src2, CondARM32::Cond Predicate) argument
887 InstARM32FourAddrGPR(Cfg *Func, Variable *Dest, Variable *Src0, Variable *Src1, Variable *Src2, CondARM32::Cond Predicate) argument
912 create(Cfg *Func, Variable *Dest, Variable *Src0, Variable *Src1) argument
937 InstARM32FourAddrFP(Cfg *Func, Variable *Dest, Variable *Src0, Variable *Src1) argument
956 create(Cfg *Func, Variable *Src0, Operand *Src1, CondARM32::Cond Predicate) argument
978 InstARM32CmpLike(Cfg *Func, Variable *Src0, Operand *Src1, CondARM32::Cond Predicate) argument
1361 create(Cfg *Func, Variable *DestLo, Variable *DestHi, Variable *Src0, Variable *Src1, CondARM32::Cond Predicate) argument
1525 create(Cfg *Func, Variable *Src0, Variable *Src1, CondARM32::Cond Predicate) argument
1530 create(Cfg *Func, Variable *Src0, OperandARM32FlexFpZero *Src1, CondARM32::Cond Predicate) argument
[all...]
H A DIceTargetLoweringMIPS32.cpp307 Operand *Src1 = Instr->getSrc(1); local
318 Context.insert<InstExtractElement>(Op1, Src1, Index);
334 Operand *Src1 = Instr->getSrc(1); local
346 Context.insert<InstExtractElement>(Op1, Src1, Index);
2178 Operand *Src1 = NumSrcs < 2 ? nullptr : CurInstr->getSrc(1); local
2181 auto *Src1M = llvm::dyn_cast_or_null<OperandMIPS32Mem>(Src1);
2467 Operand *Src1) {
2482 Src1LoR = legalizeToReg(loOperand(Src1));
2484 Src1HiR = legalizeToReg(hiOperand(Src1));
2497 Src1LoR = legalizeToReg(loOperand(Src1));
2465 lowerInt64Arithmetic(const InstArithmetic *Instr, Variable *Dest, Operand *Src0, Operand *Src1) argument
2763 Operand *Src1 = legalizeUndef(Instr->getSrc(1)); local
3121 Operand *Src1 = CompareInst->getSrc(1); local
3911 Operand *Src1 = Instr->getSrc(1); local
3980 auto *Src1 = Instr->getSrc(1); local
4169 Operand *Src1 = legalize(Instr->getSrc(1)); local
4315 auto *Src1 = Instr->getSrc(1); local
4538 createArithInst(Intrinsics::AtomicRMWOperation Operation, Variable *Dest, Variable *Src0, Variable *Src1) argument
5312 Operand *Src1 = ArithInst->getSrc(1); local
[all...]
H A DIceTargetLowering.h504 Operand *Src0, Operand *Src1);
509 /// (Variable *Dest, Variable *Src0, Variable *Src1) -> Instr *.
576 auto *Src1 = thunk1(); local
577 return insertScalarInstruction(Res, Src0, Src1);
586 auto *Src1 = thunk1(); local
588 return insertScalarInstruction(Res, Src0, Src1, Src2);
H A DIceCfg.cpp1337 Variable **Src1, CfgVector<const Inst *> *Extracts) {
1341 *Src1 = nullptr;
1378 } else if (*Src1 == nullptr) {
1379 // We already have a source, so we might save Src in Src1 -- but only if
1382 *Src1 = Src;
1384 } else if (Src != *Src0 && Src != *Src1) {
1399 // If a second source was not seen, then we just make Src1 = Src0 to simplify
1402 if (*Src1 == nullptr) {
1403 *Src1 = *Src0;
1465 Variable *Src1; local
1335 findAllExtracts(Cfg *Func, GlobalContext *Ctx, VariablesMetadata *VM, const CfgVector<const Inst *> &Insts, Variable **Src0, Variable **Src1, CfgVector<const Inst *> *Extracts) argument
[all...]
/external/swiftshader/third_party/LLVM/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp50 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
53 static void executeFAddInst(GenericValue &Dest, GenericValue Src1, argument
64 static void executeFSubInst(GenericValue &Dest, GenericValue Src1, argument
75 static void executeFMulInst(GenericValue &Dest, GenericValue Src1, argument
86 static void executeFDivInst(GenericValue &Dest, GenericValue Src1, argument
97 static void executeFRemInst(GenericValue &Dest, GenericValue Src1, argument
101 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal);
104 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal);
114 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
123 Dest.IntVal = APInt(1,(void*)(intptr_t)Src1
127 executeICMP_EQ(GenericValue Src1, GenericValue Src2, Type *Ty) argument
140 executeICMP_NE(GenericValue Src1, GenericValue Src2, Type *Ty) argument
153 executeICMP_ULT(GenericValue Src1, GenericValue Src2, Type *Ty) argument
[all...]
/external/llvm/lib/ExecutionEngine/Interpreter/
H A DExecution.cpp52 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
55 static void executeFAddInst(GenericValue &Dest, GenericValue Src1, argument
66 static void executeFSubInst(GenericValue &Dest, GenericValue Src1, argument
77 static void executeFMulInst(GenericValue &Dest, GenericValue Src1, argument
88 static void executeFDivInst(GenericValue &Dest, GenericValue Src1, argument
99 static void executeFRemInst(GenericValue &Dest, GenericValue Src1, argument
103 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal);
106 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal);
116 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
121 assert(Src1
138 executeICMP_EQ(GenericValue Src1, GenericValue Src2, Type *Ty) argument
152 executeICMP_NE(GenericValue Src1, GenericValue Src2, Type *Ty) argument
166 executeICMP_ULT(GenericValue Src1, GenericValue Src2, Type *Ty) argument
[all...]
/external/llvm/lib/Target/AMDGPU/
H A DR600ExpandSpecialInstrs.cpp225 unsigned Src1 = BMI->getOperand( local
229 (void) Src1;
231 (TRI.getEncodingValue(Src1) & 0xff) < 127)
232 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1));
276 unsigned Src1 = 0; local
282 Src1 = MI.getOperand(Src1Idx).getReg();
288 Src1 = TRI.getSubReg(Src1, SubRegIndex);
293 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
328 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1);
[all...]
H A DSIShrinkInstructions.cpp106 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); local
110 if (Src1 && (!isVGPR(Src1, TRI, MRI) || (Src1Mod && Src1Mod->getImm() != 0)))
277 const MachineOperand &Src1 = MI.getOperand(2); local
289 if (Src1.isImm() && isKImmOperand(TII, Src1)) {
381 const MachineOperand *Src1 = local
383 if (Src1)
384 Inst32.addOperand(*Src1);
H A DSIInstrInfo.cpp890 unsigned Src1 = MI.getOperand(2).getReg(); local
895 .addReg(RI.getSubReg(Src1, AMDGPU::sub0))
900 .addReg(RI.getSubReg(Src1, AMDGPU::sub1))
967 MachineOperand &Src1 = MI.getOperand(Src1Idx);
983 if (!Src1.isReg()) {
985 if (NewMI || !Src1.isImm() || (!isVOP2(MI) && !isVOP3(MI))) {
1009 if (Src1.isImm())
1010 Src0.ChangeToImmediate(Src1.getImm());
1014 Src1.ChangeToRegister(Reg, false);
1015 Src1
1240 MachineOperand *Src1 = getNamedOperand(UseMI, AMDGPU::OpName::src1); local
[all...]
/external/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp147 // Use CLC to compare [Src1, Src1 + Size) with [Src2, Src2 + Size),
150 SDValue Src1, SDValue Src2, uint64_t Size) {
152 EVT PtrVT = Src1.getValueType();
162 return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2,
165 return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2,
184 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1,
190 Chain = emitCLC(DAG, DL, Chain, Src1, Src2, Bytes);
235 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1,
238 SDVTList VTs = DAG.getVTList(Src1
149 emitCLC(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, SDValue Src2, uint64_t Size) argument
183 EmitTargetCodeForMemcmp( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, SDValue Src2, SDValue Size, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
234 EmitTargetCodeForStrcmp( SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, SDValue Src2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
[all...]
H A DSystemZSelectionDAGInfo.h41 SDValue Src1, SDValue Src2, SDValue Size,
57 SDValue Src1, SDValue Src2,
/external/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp307 unsigned Src1 = 0, SubReg1; local
336 Src1 = MOSrc1->getReg();
355 if (!Src1) {
357 Src1 = MRI->createVirtualRegister(&AArch64::FPR64RegClass);
358 insertCopy(TII, MI, Src1, OrigSrc1, KillSrc1);
372 .addReg(Src1, getKillRegState(KillSrc1), SubReg1);
/external/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp96 unsigned getMuxOpcode(const MachineOperand &Src1,
175 unsigned HexagonGenMux::getMuxOpcode(const MachineOperand &Src1, argument
177 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg();
266 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2); local
267 unsigned SR1 = Src1->isReg() ? Src1->getReg() : 0;
284 MachineOperand *SrcT = (MinX == CI.TrueX) ? Src1 : Src2;
285 MachineOperand *SrcF = (MinX == CI.FalseX) ? Src1 : Src2;
H A DHexagonPeephole.cpp159 MachineOperand &Src1 = MI.getOperand(1); local
161 if (Src1.getImm() != 0)
176 MachineOperand &Src1 = MI.getOperand(1); local
181 unsigned SrcReg = Src1.getReg();
/external/syslinux/gnu-efi/gnu-efi-3.0/lib/
H A Ddpath.c119 IN EFI_DEVICE_PATH *Src1,
122 // Src1 may have multiple "instances" and each instance is appended
123 // Src2 is appended to each instance is Src1. (E.g., it's possible
135 if (!Src1) {
141 ASSERT (!IsDevicePathUnpacked (Src1));
142 return DuplicateDevicePath (Src1);
149 // ASSERT (!IsDevicePathUnpacked (Src1));
153 // Append Src2 to every instance in Src1
156 Src1Size = DevicePathSize(Src1);
157 Src1Inst = DevicePathInstanceCount(Src1);
118 AppendDevicePath( IN EFI_DEVICE_PATH *Src1, IN EFI_DEVICE_PATH *Src2 ) argument
191 AppendDevicePathNode( IN EFI_DEVICE_PATH *Src1, IN EFI_DEVICE_PATH *Src2 ) argument
[all...]
/external/swiftshader/third_party/subzero/unittest/AssemblerX8632/
H A DControlFlow.cpp18 #define TestJ(C, Near, Src0, Value0, Src1, Value1, Dest) \
23 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##Src1, Immediate(Value1)); \
26 GPRRegister::Encoded_Reg_##Src1); \
33 EXPECT_EQ(Value1, test.Src1()) << "Br_" #C ", " #Near; \

Completed in 2733 milliseconds

123