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Searched refs:SubReg0 (Results 1 - 6 of 6) sorted by relevance

/external/llvm/lib/Target/AArch64/
H A D	AArch64AdvSIMDScalarPass.cpp	`214 unsigned SubReg0; local 220 MachineOperand MOSrc0 = getSrcFromCopy(&Def, MRI, SubReg0); 306 unsigned Src0 = 0, SubReg0; local 313 MachineOperand MOSrc0 = getSrcFromCopy(&Def, MRI, SubReg0); 350 SubReg0 = 0; 371 .addReg(Src0, getKillRegState(KillSrc0), SubReg0)`
/external/llvm/lib/CodeGen/
H A D	TargetInstrInfo.cpp	`146 unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0; local 161 SubReg0 = SubReg2; 166 SubReg0 = SubReg1; 180 CommutedMI->getOperand(0).setSubReg(SubReg0);`
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A D	ARMISelDAGToDAG.cpp	1456 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32); local 1458 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; 1467 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32); local 1469 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; 1478 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32); local 1480 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; 1491 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32); local 1495 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, 1506 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32); local 1510 const SDValue Ops[] = { RegClass, V0, SubReg0, V 1521 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32); local [all...]
/external/llvm/lib/Target/ARM/
H A D	ARMISelDAGToDAG.cpp	1600 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, dl, MVT::i32); local 1602 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; 1611 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32); local 1613 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; 1622 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32); local 1624 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; 1633 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32); local 1635 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; 1645 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, dl, MVT::i32); local 1649 const SDValue Ops[] = { RegClass, V0, SubReg0, V 1660 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, dl, MVT::i32); local 1675 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, dl, MVT::i32); local [all...]
H A D	ARMISelLowering.cpp	`7108 SDValue SubReg0 = DAG.getTargetConstant(ARM::gsub_0, dl, MVT::i32); local 7110 const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 };`
/external/llvm/lib/Target/AMDGPU/
H A D	AMDGPUISelDAGToDAG.cpp	`364 SDValue RC, SubReg0, SubReg1; local 371 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32); 375 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32); 380 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,`

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