| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 41 UXTH, enumerator in enum:llvm::AArch64_AM::ShiftExtendType
61 case AArch64_AM::UXTH: return "uxth";
128 case 1: return AArch64_AM::UXTH;
155 case AArch64_AM::UXTH: return 1; break;
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| /external/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 360 UXTH, enumerator in enum:llvm::AArch64SE::ShiftExtSpecifiers
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ExpandPseudoInsts.cpp | 913 AArch64_AM::getArithExtendImm(AArch64_AM::UXTH, 0),
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| H A D | AArch64ISelDAGToDAG.cpp | 391 return AArch64_AM::UXTH;
409 return !IsLoadStore ? AArch64_AM::UXTH : AArch64_AM::InvalidShiftExtend;
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| H A D | AArch64FastISel.cpp | 1098 ExtendType = IsZExt ? AArch64_AM::UXTH : AArch64_AM::SXTH;
|
| /external/llvm/test/MC/ARM/ |
| H A D | basic-thumb-instructions.s | 656 @ UXTB/UXTH
|
| H A D | v8_IT_manual.s | 532 @ UXTH, encoding T1
536 @ UXTH, encoding T2 (32-bit)
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| H A D | basic-thumb-instructions.s | 605 @ UXTB/UXTH
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| H A D | basic-arm-instructions.s | 2596 @ UXTH
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| H A D | basic-thumb2-instructions.s | 3176 @ UXTH
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| /external/pcre/dist2/src/sljit/ |
| H A D | sljitNativeARM_T2_32.c | 167 #define UXTH 0xb280 macro
707 return push_inst16(compiler, UXTH | RD3(dst) | RN3(arg2));
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| H A D | sljitNativeARM_32.c | 124 #define UXTH 0xe6ff0070 macro
1033 return push_inst(compiler, (op == SLJIT_MOV_U16 ? UXTH : SXTH) | RD(dst) | RM(src2));
|
| /external/v8/src/compiler/arm64/ |
| H A D | code-generator-arm64.cc | 117 return Operand(InputRegister32(index), UXTH);
147 return Operand(InputRegister64(index), UXTH);
|
| /external/v8/src/arm64/ |
| H A D | constants-arm64.h | 340 UXTH = 1, enumerator in enum:v8::internal::Extend
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| H A D | assembler-arm64.cc | 2501 case UXTH:
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| H A D | simulator-arm64.cc | 980 case UXTH:
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 2644 /* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } }
2884 { { ARM::UXTH, ARM::t2UXTH }, 0, 1, MVT::i16 },
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| H A D | ARMExpandPseudoInsts.cpp | 1641 ARM::UXTH, NextMBBI);
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 2029 Opc = isThumb ? ARM::t2UXTH : ARM::UXTH;
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| /external/vixl/src/aarch64/ |
| H A D | constants-aarch64.h | 286 UXTH = 1, enumerator in enum:vixl::aarch64::Extend
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| H A D | simulator-aarch64.cc | 391 case UXTH:
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| H A D | assembler-aarch64.cc | 4193 case UXTH:
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 989 ET == AArch64_AM::UXTH || ET == AArch64_AM::SXTH ||
2390 .Case("uxth", AArch64_AM::UXTH)
|
| /external/vixl/test/aarch64/ |
| H A D | test-assembler-aarch64.cc | 327 __ Mvn(w12, Operand(w2, UXTH, 2));
502 __ Mov(w25, Operand(w13, UXTH, 2));
556 __ Mov(w21, Operand(w11, UXTH, 1));
563 __ Mov(x27, Operand(x12, UXTH, 1));
636 __ Orr(x7, x0, Operand(x1, UXTH, 1));
730 __ Orn(x7, x0, Operand(x1, UXTH, 1));
797 __ And(x7, x0, Operand(x1, UXTH, 1));
935 __ Bic(x7, x0, Operand(x1, UXTH, 1));
1059 __ Eor(x7, x0, Operand(x1, UXTH, 1));
1126 __ Eon(x7, x0, Operand(x1, UXTH,
[all...] |
| H A D | test-disasm-aarch64.cc | 427 COMPARE(add(w6, w7, Operand(w8, UXTH, 2)), "add w6, w7, w8, uxth #2");
439 COMPARE(add(x2, sp, Operand(x3, UXTH, 1)), "add x2, sp, w3, uxth #1");
453 COMPARE(sub(w6, w7, Operand(w8, UXTH, 2)), "sub w6, w7, w8, uxth #2");
462 COMPARE(cmp(x2, Operand(x3, UXTH, 3)), "cmp x2, w3, uxth #3");
465 COMPARE(sub(x2, sp, Operand(x3, UXTH, 1)), "sub x2, sp, w3, uxth #1");
|