| /external/swiftshader/third_party/LLVM/bindings/ocaml/bitwriter/ |
| H A D | llvm_bitwriter.ml | 16 (* Writes the bitcode for module the given path. Returns true if successful. *)
|
| /external/llvm/utils/TableGen/ |
| H A D | CodeGenSchedule.cpp | 186 RecVec Seq = RWDef->getValueAsListOfDefs("Writes");
293 findRWs(WI->TheDef->getValueAsListOfDefs("Writes"), WI->Sequence,
383 IdxVec &Writes, IdxVec &Reads) const {
387 findRWs(WriteDefs, Writes, false);
509 IdxVec Writes, Reads;
511 findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);
516 unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, ProcIndices);
551 if (!SC.Writes.empty()) {
554 for (IdxIter WI = SC.Writes.begin(), WE = SC.Writes
[all...] |
| H A D | CodeGenSchedule.h | 109 /// Writes and ReadDefs are empty. ProcIndices contains 0 for any processor.
118 /// provided InstrRW records for this class. ItinClassDef or Writes/Reads may
126 /// that mapped the itinerary class to the variant Writes or Reads.
132 IdxVec Writes; member in struct:llvm::CodeGenSchedClass
148 return ItinClassDef == IC && makeArrayRef(Writes) == W &&
370 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
382 unsigned findSchedClassIdx(Record *ItinClassDef, ArrayRef<unsigned> Writes,
432 void collectRWResources(ArrayRef<unsigned> Writes, ArrayRef<unsigned> Reads,
|
| H A D | SubtargetEmitter.cpp | 852 IdxVec Writes = SC.Writes; local
866 Writes.clear();
869 Writes, Reads);
872 if (Writes.empty()) {
879 Writes, Reads);
883 if (Writes.empty()) {
893 for (unsigned W : Writes) {
|
| /external/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBundle.h | 157 /// Writes - One of the operands writes the virtual register.
158 bool Writes; member in struct:llvm::MachineOperandIteratorBase::VirtRegInfo
|
| /external/blktrace/doc/ |
| H A D | blktrace.tex | 163 Reads Queued: 0, 0KiB Writes Queued: 7, 128KiB
165 Reads Completed: 0, 0KiB Writes Completed: 11, 168KiB
170 Reads Queued: 0, 0KiB Writes Queued: 1, 28KiB
172 Reads Completed: 0, 0KiB Writes Completed: 0, 0KiB
177 Reads Queued: 0, 0KiB Writes Queued: 11, 168KiB
179 Reads Completed: 0, 0KiB Writes Completed: 11, 168KiB
299 Reads Queued: 0, 0KiB Writes Queued: 9, 5,520KiB
301 Reads Completed: 0, 0KiB Writes Completed: 0, 0KiB
305 Reads Queued: 2,411, 38,576KiB Writes Queued: 769, 425,408KiB
307 Reads Completed: 0, 0KiB Writes Complete
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| H A D | InlineSpiller.cpp | 866 bool Reads, Writes; local
868 tie(Reads, Writes) = MI->readsWritesVirtualRegister(VirtReg.reg, &Ops);
869 if (Writes) {
1126 bool Reads, Writes; local
1128 tie(Reads, Writes) = MI->readsWritesVirtualRegister(Reg, &Ops);
1146 if (Writes) {
1190 if (Writes) {
|
| H A D | RegisterCoalescer.cpp | 942 bool Reads, Writes; local
943 tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
975 else if (!Reads && Writes)
|
| /external/llvm/lib/CodeGen/ |
| H A D | MachineInstrBundle.cpp | 286 RI.Writes = true;
|
| H A D | MachinePipeliner.cpp | 3651 bool Reads, Writes; local
3652 std::tie(Reads, Writes) =
3661 } else if (MO.isUse() && Writes && stageScheduled(*I) == StageInst1) {
3669 } else if (MO.isUse() && Writes && stageScheduled(*I) > StageInst1) {
3676 } else if (MO.isUse() && Writes && stageScheduled(*I) < StageInst1) {
|
| H A D | InlineSpiller.cpp | 925 if (RI.Writes) {
967 if (RI.Writes)
|
| H A D | RegisterCoalescer.cpp | 1276 bool Reads, Writes; local
1277 std::tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
|