/external/llvm/include/llvm/MC/ |
H A D | MCInstBuilder.h | 33 Inst.addOperand(MCOperand::createReg(Reg)); 39 Inst.addOperand(MCOperand::createImm(Val)); 45 Inst.addOperand(MCOperand::createFPImm(Val)); 51 Inst.addOperand(MCOperand::createExpr(Val)); 57 Inst.addOperand(MCOperand::createInst(Val)); 62 MCInstBuilder &addOperand(const MCOperand &Op) { function in class:llvm::MCInstBuilder 63 Inst.addOperand(Op);
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/external/llvm/lib/Target/Mips/Disassembler/ |
H A D | MipsDisassembler.cpp | 577 MI.addOperand(MCOperand::createImm(tmp)); 583 MI.addOperand(MCOperand::createImm(0)); 617 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 620 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 622 MI.addOperand(MCOperand::createImm(Imm)); 637 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 639 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 643 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 645 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, 649 MI.addOperand(MCOperan [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
H A D | ARMAsmPrinter.cpp | 984 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr)); 985 BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 986 BrInst.addOperand(MCOperand::CreateReg(0)); 1031 Inst.addOperand(MCOperand::CreateReg(Dest)); 1032 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr)); 1034 Inst.addOperand(MCOperand::CreateImm(pred)); 1035 Inst.addOperand(MCOperand::CreateReg(ccreg)); 1245 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR)); 1246 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); 1248 TmpInst.addOperand(MCOperan [all...] |
/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 1742 Inst.addOperand(MCOperand::createImm(0)); 1744 Inst.addOperand(MCOperand::createImm(CE->getValue())); 1746 Inst.addOperand(MCOperand::createExpr(Expr)); 1761 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); 1763 Inst.addOperand(MCOperand::createReg(RegNum)); 1768 Inst.addOperand(MCOperand::createImm(getCoproc())); 1773 Inst.addOperand(MCOperand::createImm(getCoproc())); 1778 Inst.addOperand(MCOperand::createImm(CoprocOption.Val)); 1783 Inst.addOperand(MCOperand::createImm(ITMask.Mask)); 1788 Inst.addOperand(MCOperan [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
H A D | PTXMCInstLower.cpp | 29 OutMI.addOperand(AP.lowerOperand(MO));
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/external/llvm/lib/Target/PowerPC/AsmParser/ |
H A D | PPCAsmParser.cpp | 557 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); 562 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()])); 567 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); 572 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()])); 591 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); 596 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); 601 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); 606 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()])); 611 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()])); 616 Inst.addOperand(MCOperan [all...] |
/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCCompound.cpp | 222 CompoundInsn->addOperand(Rt); 223 CompoundInsn->addOperand(L.getOperand(1)); // Immediate 224 CompoundInsn->addOperand(R.getOperand(0)); // Jump target 234 CompoundInsn->addOperand(Rt); 235 CompoundInsn->addOperand(Rs); 236 CompoundInsn->addOperand(R.getOperand(0)); // Jump target. 248 CompoundInsn->addOperand(Rs); 249 CompoundInsn->addOperand(Rt); 250 CompoundInsn->addOperand(R.getOperand(1)); 261 CompoundInsn->addOperand(R [all...] |
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
H A D | MachineInstrBuilder.h | 61 MI->addOperand(MachineOperand::CreateReg(RegNo, 76 MI->addOperand(MachineOperand::CreateImm(Val)); 81 MI->addOperand(MachineOperand::CreateCImm(Val)); 86 MI->addOperand(MachineOperand::CreateFPImm(Val)); 92 MI->addOperand(MachineOperand::CreateMBB(MBB, TargetFlags)); 97 MI->addOperand(MachineOperand::CreateFI(Idx)); 104 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset, TargetFlags)); 110 MI->addOperand(MachineOperand::CreateJTI(Idx, TargetFlags)); 117 MI->addOperand(MachineOperand::CreateGA(GV, Offset, TargetFlags)); 123 MI->addOperand(MachineOperan 139 const MachineInstrBuilder &addOperand(const MachineOperand &MO) const { function in class:llvm::MachineInstrBuilder [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonAsmPrinter.cpp | 271 Inst.addOperand(Reg); 272 Inst.addOperand(MCOperand::createReg(Hexagon::R0)); 273 Inst.addOperand(S16); 290 TmpInst.addOperand(Reg); 291 TmpInst.addOperand(MCOperand::createExpr( 309 TmpInst.addOperand(Reg); 310 TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create( 322 MappedInst.addOperand(Ps); 385 TmpInst.addOperand(MappedInst.getOperand(0)); 386 TmpInst.addOperand(MappedIns [all...] |
H A D | HexagonOptAddrMode.cpp | 320 MIB.addOperand(OldMI->getOperand(0)); 321 MIB.addOperand(OldMI->getOperand(2)); 322 MIB.addOperand(OldMI->getOperand(3)); 323 MIB.addOperand(ImmOp); 330 .addOperand(OldMI->getOperand(0)); 346 MIB.addOperand(OldMI->getOperand(0)); 347 MIB.addOperand(OldMI->getOperand(1)); 348 MIB.addOperand(ImmOp); 357 MIB.addOperand(OldMI->getOperand(i)); 377 MIB.addOperand(OldM [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMInstrInfo.cpp | 39 NopInst.addOperand(MCOperand::createImm(0)); 40 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); 41 NopInst.addOperand(MCOperand::createReg(0)); 44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); 45 NopInst.addOperand(MCOperand::createReg(ARM::R0)); 46 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); 47 NopInst.addOperand(MCOperand::createReg(0)); 48 NopInst.addOperand(MCOperand::createReg(0));
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H A D | Thumb1InstrInfo.cpp | 30 NopInst.addOperand(MCOperand::createReg(ARM::R8)); 31 NopInst.addOperand(MCOperand::createReg(ARM::R8)); 32 NopInst.addOperand(MCOperand::createImm(ARMCC::AL)); 33 NopInst.addOperand(MCOperand::createReg(0));
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/external/llvm/lib/Target/Lanai/Disassembler/ |
H A D | LanaiDisassembler.cpp | 126 Instr.addOperand(MCOperand::createImm(AluOp)); 169 Inst.addOperand(MCOperand::createReg(Reg)); 178 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); 180 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset))); 190 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); 192 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); 202 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); 204 Inst.addOperand(MCOperand::createImm(SignExtend32<10>(Offset))); 222 MI.addOperand(MCOperand::createImm(Insn)); 229 Inst.addOperand(MCOperan [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/ |
H A D | MBlazeDisassembler.cpp | 538 instr.addOperand(MCOperand::CreateReg(RD)); 539 instr.addOperand(MCOperand::CreateReg(RB)); 540 instr.addOperand(MCOperand::CreateReg(RA)); 546 instr.addOperand(MCOperand::CreateReg(RD)); 547 instr.addOperand(MCOperand::CreateReg(RA)); 548 instr.addOperand(MCOperand::CreateReg(RB)); 558 instr.addOperand(MCOperand::CreateReg(RD)); 559 instr.addOperand(MCOperand::CreateImm(insn&0x3FFF)); 564 instr.addOperand(MCOperand::CreateImm(insn&0x3FFF)); 565 instr.addOperand(MCOperan [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | MachineInstrBuilder.h | 73 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo, 88 MI->addOperand(*MF, MachineOperand::CreateImm(Val)); 93 MI->addOperand(*MF, MachineOperand::CreateCImm(Val)); 98 MI->addOperand(*MF, MachineOperand::CreateFPImm(Val)); 104 MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags)); 109 MI->addOperand(*MF, MachineOperand::CreateFI(Idx)); 116 MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags)); 122 MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset, 129 MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags)); 136 MI->addOperand(*M 175 const MachineInstrBuilder &addOperand(const MachineOperand &MO) const { function in class:llvm::MachineInstrBuilder [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64AsmPrinter.cpp | 435 MOVI.addOperand(MCOperand::createReg(DestReg)); 436 MOVI.addOperand(MCOperand::createImm(0)); 444 FMov.addOperand(MCOperand::createReg(DestReg)); 445 FMov.addOperand(MCOperand::createReg(AArch64::WZR)); 449 FMov.addOperand(MCOperand::createReg(DestReg)); 450 FMov.addOperand(MCOperand::createReg(AArch64::XZR)); 494 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); 503 TmpInst.addOperand(Dest); 527 Adrp.addOperand(MCOperand::createReg(AArch64::X0)); 528 Adrp.addOperand(SymTLSDes [all...] |
/external/llvm/lib/Target/AMDGPU/ |
H A D | SILowerI1Copies.cpp | 119 .addOperand(Dst) 127 .addOperand(Dst) 130 .addOperand(Src); 135 .addOperand(Dst) 136 .addOperand(Src)
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/external/llvm/lib/Target/SystemZ/Disassembler/ |
H A D | SystemZDisassembler.cpp | 83 Inst.addOperand(MCOperand::createReg(RegNo)); 157 Inst.addOperand(MCOperand::createImm(Imm)); 165 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); 245 Inst.addOperand(MCOperand::createImm(Value)); 273 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); 274 Inst.addOperand(MCOperand::createImm(Disp)); 283 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); 284 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp))); 294 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); 295 Inst.addOperand(MCOperan [all...] |
/external/llvm/lib/Target/WebAssembly/Disassembler/ |
H A D | WebAssemblyDisassembler.cpp | 102 MI.addOperand(MCOperand::createImm(Imm)); 110 MI.addOperand(MCOperand::createReg(Reg)); 123 MI.addOperand(MCOperand::createFPImm(Imm)); 139 MI.addOperand(MCOperand::createImm(Imm)); 143 MI.addOperand(MCOperand::createReg(Reg));
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/external/llvm/lib/Target/Hexagon/Disassembler/ |
H A D | HexagonDisassembler.cpp | 170 MI.addOperand(MCOperand::createInst(Inst)); 309 MI.addOperand(OPLow); 310 MI.addOperand(OPHigh); 476 Inst.addOperand(MCOperand::createReg(Table[RegNo])); 578 Inst.addOperand(MCOperand::createReg(Register)); 602 Inst.addOperand(MCOperand::createReg(Register)); 620 Inst.addOperand(MCOperand::createReg(Register)); 878 MI.addOperand(MCOperand::createImm(Value)); 903 MI.addOperand(MCOperand::createImm(Value)); 928 MI.addOperand(MCOperan [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 525 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx))); 527 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx))); 529 MI.addOperand(MCOperand::CreateExpr(Expr)); 857 Inst.addOperand(MCOperand::CreateReg(Register)); 901 Inst.addOperand(MCOperand::CreateReg(Register)); 928 Inst.addOperand(MCOperand::CreateReg(Register)); 949 Inst.addOperand(MCOperand::CreateReg(Register)); 983 Inst.addOperand(MCOperand::CreateReg(Register)); 993 Inst.addOperand(MCOperand::CreateImm(Val)); 995 Inst.addOperand(MCOperan [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 919 Inst.addOperand(MCOperand::CreateImm(0)); 921 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 923 Inst.addOperand(MCOperand::CreateExpr(Expr)); 928 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 930 Inst.addOperand(MCOperand::CreateReg(RegNum)); 935 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 940 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 945 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val)); 950 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask)); 955 Inst.addOperand(MCOperan [all...] |
/external/llvm/lib/Target/X86/AsmParser/ |
H A D | X86Operand.h | 380 Inst.addOperand(MCOperand::createImm(CE->getValue())); 382 Inst.addOperand(MCOperand::createExpr(Expr)); 387 Inst.addOperand(MCOperand::createReg(getReg())); 418 Inst.addOperand(MCOperand::createReg(RegNo)); 431 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); 432 Inst.addOperand(MCOperand::createImm(getMemScale())); 433 Inst.addOperand(MCOperand::createReg(getMemIndexReg())); 435 Inst.addOperand(MCOperand::createReg(getMemSegReg())); 442 Inst.addOperand(MCOperand::createImm(CE->getValue())); 444 Inst.addOperand(MCOperan [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/ |
H A D | X86Disassembler.cpp | 161 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum)); 230 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4))); 233 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4))); 256 mcInst.addOperand(MCOperand::CreateImm(immediate)); 287 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break; 426 mcInst.addOperand(baseReg); 427 mcInst.addOperand(scaleAmount); 428 mcInst.addOperand(indexReg); 429 mcInst.addOperand(displacement); 430 mcInst.addOperand(segmentRe [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
H A D | X86MCInstLower.cpp | 225 OutMI.addOperand(OutMI.getOperand(0)); 226 OutMI.addOperand(OutMI.getOperand(0)); 247 Inst.addOperand(Saved); 298 Inst.addOperand(Saved); 340 OutMI.addOperand(MCOp); 401 OutMI.addOperand(Saved); 427 OutMI.addOperand(Saved); 551 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest 552 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base 553 LEA.addOperand(MCOperan [all...] |