| /external/clang/test/CodeGen/ |
| H A D | ms-declspecs.c | 34 void f20(void) { f20_t(); }
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| H A D | function-attributes.c | 101 // CHECK-LABEL: define void @f20()
107 void f20(void) { function
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| H A D | x86_64-arguments-nacl.c | 71 // CHECK-LABEL: define void @f20(%struct.s20* byval align 32 %x)
76 void f20(struct s20 x) {} function
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| H A D | arm-arguments.c | 113 // APCS-GNU-LABEL: define void @f20(
115 // AAPCS-LABEL: define arm_aapcscc i32 @f20()
117 struct s20 f20(void) {} function
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| /external/compiler-rt/lib/builtins/ppc/ |
| H A D | restFP.S | 29 lfd f20,-96(r1)
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| H A D | saveFP.S | 27 stfd f20,-96(r1)
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| /external/linux-kselftest/tools/testing/selftests/powerpc/include/ |
| H A D | fpu_asm.h | 26 stfd f20,(stack_size + STACK_FRAME_MIN_SIZE - 88)(%r1); \
46 lfd f20,(stack_size + STACK_FRAME_MIN_SIZE - 88)(%r1); \
65 lfd f20,48(r3) variable
|
| /external/compiler-rt/lib/tsan/rtl/ |
| H A D | tsan_ppc_regs.h | 53 #define f20 20 macro
|
| /external/llvm/test/MC/Mips/mips1/ |
| H A D | invalid-mips5-wrong-error.s | 14 c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
18 c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
35 movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| H A D | valid.s | 37 cvt.w.d $f20,$f14
38 cvt.w.s $f20,$f24
40 div.d $f29,$f20,$f27
66 mov.d $f20,$f14
74 mul.d $f20,$f20,$f16
|
| /external/llvm/test/MC/Mips/mips2/ |
| H A D | invalid-mips5-wrong-error.s | 14 c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
18 c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
35 movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| H A D | valid.s | 44 ceil.w.s $f6,$f20
51 cvt.w.d $f20,$f14
52 cvt.w.s $f20,$f24
54 div.d $f29,$f20,$f27
86 mov.d $f20,$f14
94 mul.d $f20,$f20,$f16
|
| /external/llvm/test/MC/Mips/mips3/ |
| H A D | invalid-mips5-wrong-error.s | 14 c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
18 c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
35 movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/llvm/test/MC/Mips/mips4/ |
| H A D | invalid-mips5-wrong-error.s | 14 c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
18 c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
35 movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| H A D | valid.s | 51 ceil.w.s $f6,$f20
62 cvt.w.d $f20,$f14
63 cvt.w.s $f20,$f24
77 div.d $f29,$f20,$f27
146 madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1]
152 mov.d $f20,$f14
176 mul.d $f20,$f20,$f16
186 nmadd.d $f18, $f8, $f14, $f20 # encoding: [0x4d,0x14,0x74,0xb1]
189 nmsub.s $f0, $f24, $f20,
[all...] |
| /external/llvm/test/MC/Mips/mips64r6/ |
| H A D | invalid-mips5-wrong-error.s | 17 c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
21 c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
37 movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/llvm/test/MC/ARM/ |
| H A D | symbol-variants.s | 70 .word f20(TLSLDO)
72 @CHECK: 50 R_ARM_TLS_LDO32 f20
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| H A D | invalid-mips32r2.s | 8 madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/clang/test/CodeGenCXX/ |
| H A D | aarch64-mangle-neon-vectors.cpp | 78 void f20(uint32x4_t) {} function
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| H A D | debug-info-line.cpp | 237 void f20(int a, int b, int c) { function
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| /external/llvm/test/MC/Mips/mips5/ |
| H A D | valid.s | 51 ceil.w.s $f6,$f20
62 cvt.w.d $f20,$f14
63 cvt.w.s $f20,$f24
77 div.d $f29,$f20,$f27
147 madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1]
153 mov.d $f20,$f14
177 mul.d $f20,$f20,$f16
187 nmadd.d $f18, $f8, $f14, $f20 # encoding: [0x4d,0x14,0x74,0xb1]
190 nmsub.s $f0, $f24, $f20,
[all...] |
| /external/valgrind/none/tests/mips32/ |
| H A D | MoveIns.c | 294 TESTINSNMOVE("mfc1 $a3, $f20", 12, f20, a3);
323 TESTINSNMOVEt("mtc1 $a3, $f20", 14, f20, a3);
343 TESTINSNMOVEd("mfhc1 $s1, $f20", 80, f20, s1);
361 TESTINSNMOVEtd("mthc1 $s2, $f20", 40, 80, f20, s2);
390 TESTINSNMOVE1s("mov.s $f19, $f20", 12, f19, f20);
[all...] |
| /external/clang/test/SemaObjCXX/Inputs/ |
| H A D | nullability-pragmas-1.h | 92 void f20(A *a); // expected-warning{{pointer is missing a nullability type specifier}}
|
| /external/libjpeg-turbo/simd/ |
| H A D | jsimd_mips_dspr2_asm.h | 79 #define f20 $f20 macro
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| /external/llvm/test/MC/Mips/mips32r2/ |
| H A D | valid.s | 49 ceil.w.s $f6,$f20
60 cvt.w.d $f20,$f14
61 cvt.w.s $f20,$f24
66 div.d $f29,$f20,$f27
103 madd.d $f18,$f19,$f26,$f20
113 mov.d $f20,$f14
140 mul.d $f20,$f20,$f16
|