Searched refs:f30 (Results 1 - 25 of 114) sorted by relevance

12345

/external/llvm/test/MC/Mips/
H A Dmips-reginfo-fp32.s33 # abs.d - Reads from $f30 and $f31 and writes to $f30 and $f31.
34 abs.d $f30,$f30
H A Dmips-reginfo-fp64.s55 # abs.d - Reads from $f30 and writes to $f30.
56 abs.d $f30,$f30
/external/llvm/test/MC/Mips/mips1/
H A Dinvalid-mips5-wrong-error.s11 alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
17 c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
19 c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
29 cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
42 pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
44 pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/external/llvm/test/MC/Mips/mips2/
H A Dinvalid-mips5-wrong-error.s11 alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
17 c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
19 c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
29 cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
42 pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
44 pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
H A Dinvalid-mips32r2.s43 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
44 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
57 nmsub.d $f30,$f8,$f16,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/llvm/test/MC/Mips/mips3/
H A Dinvalid-mips5-wrong-error.s11 alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
17 c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
19 c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
29 cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
42 pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
44 pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
H A Dinvalid-mips4.s24 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
25 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
H A Dinvalid-mips5.s25 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
26 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
/external/llvm/test/MC/Mips/mips4/
H A Dinvalid-mips5-wrong-error.s11 alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
17 c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
19 c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
29 cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
42 pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
44 pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
H A Dvalid.s46 c.sf.d $f30,$f0
60 cvt.s.l $f15,$f30
147 madd.s $f2, $f30, $f18, $f24 # encoding: [0x4f,0xd8,0x90,0xa0]
166 movt.s $f30,$f2,$fcc1
170 msub.d $f10, $f2, $f30, $f18 # encoding: [0x4c,0x52,0xf2,0xa9]
177 mul.s $f30,$f10,$f2
188 nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9]
269 trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encodin
[all...]
/external/compiler-rt/lib/builtins/ppc/
H A DrestFP.S39 lfd f30,-16(r1)
H A DsaveFP.S37 stfd f30,-16(r1)
/external/llvm/test/MC/Mips/mips32r6/
H A Dinvalid-mips32r2.s14 nmsub.d $f30,$f8,$f16,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/llvm/test/MC/Mips/mips64r6/
H A Dinvalid-mips5-wrong-error.s10 alnv.ps $f12,$f18,$f30,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
20 c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
22 c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
44 pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
46 pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/external/linux-kselftest/tools/testing/selftests/powerpc/include/
H A Dfpu_asm.h16 stfd f30,(stack_size + STACK_FRAME_MIN_SIZE - 8)(%r1); \
36 lfd f30,(stack_size + STACK_FRAME_MIN_SIZE - 8)(%r1); \
75 lfd f30,128(r3) variable
/external/compiler-rt/lib/tsan/rtl/
H A Dtsan_ppc_regs.h63 #define f30 30 macro
/external/llvm/test/MC/Mips/mips5/
H A Dvalid.s46 c.sf.d $f30,$f0
60 cvt.s.l $f15,$f30
148 madd.s $f2, $f30, $f18, $f24 # encoding: [0x4f,0xd8,0x90,0xa0]
167 movt.s $f30,$f2,$fcc1
171 msub.d $f10, $f2, $f30, $f18 # encoding: [0x4c,0x52,0xf2,0xa9]
178 mul.s $f30,$f10,$f2
189 nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9]
271 trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encodin
[all...]
/external/clang/test/CodeGen/
H A Darm-arguments.c153 // APCS-GNU: define void @f30({{.*}} noalias sret
154 // AAPCS: define arm_aapcscc void @f30({{.*}} noalias sret
156 struct s30 f30() {} function
/external/clang/test/SemaObjCXX/Inputs/
H A Dnullability-pragmas-1.h73 static inline void f30(void) { function
/external/llvm/test/MC/Mips/mips32/
H A Dinvalid-mips32r2.s25 nmsub.d $f30,$f8,$f16,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/libjpeg-turbo/simd/
H A Djsimd_mips_dspr2_asm.h89 #define f30 $f30 macro
/external/llvm/test/MC/Mips/mips64/
H A Dvalid.s46 c.sf.d $f30,$f0
62 cvt.s.l $f15,$f30
159 madd.s $f2, $f30, $f18, $f24 # encoding: [0x4f,0xd8,0x90,0xa0]
179 movt.s $f30,$f2,$fcc1
185 msub.d $f10, $f2, $f30, $f18 # encoding: [0x4c,0x52,0xf2,0xa9]
194 mul.s $f30,$f10,$f2
205 nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9]
290 trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encodin
[all...]
/external/llvm/test/MC/Mips/mips32r2/
H A Dvalid.s46 c.sf.d $f30,$f0
125 movt.s $f30,$f2,$fcc1
141 mul.s $f30,$f10,$f2
152 nmsub.d $f30,$f8,$f16,$f30
241 trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
/external/llvm/test/MC/Mips/mips32r3/
H A Dvalid.s46 c.sf.d $f30,$f0
125 movt.s $f30,$f2,$fcc1
141 mul.s $f30,$f10,$f2
152 nmsub.d $f30,$f8,$f16,$f30
241 trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
/external/llvm/test/MC/Mips/mips32r5/
H A Dvalid.s46 c.sf.d $f30,$f0
126 movt.s $f30,$f2,$fcc1
142 mul.s $f30,$f10,$f2
153 nmsub.d $f30,$f8,$f16,$f30
242 trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]

Completed in 422 milliseconds

12345