Searched refs:r6 (Results 1 - 25 of 451) sorted by relevance

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/external/libmpeg2/common/arm/
H A Dimpeg2_format_conv.s139 mov r6, r5
145 sub r6, r6, #16
146 cmp r6, #15
149 cmp r6, #0
155 rsb r6, r6, #16
156 sub r0, r0, r6
157 sub r3, r3, r6
189 mov r6, r
[all...]
/external/vixl/test/aarch32/
H A Dtest-assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block.cc101 {{eq, r0, r6, r0}, true, eq, "eq r0 r6 r0", "eq_r0_r6_r0"},
109 {{eq, r1, r6, r1}, true, eq, "eq r1 r6 r1", "eq_r1_r6_r1"},
117 {{eq, r2, r6, r2}, true, eq, "eq r2 r6 r2", "eq_r2_r6_r2"},
125 {{eq, r3, r6, r3}, true, eq, "eq r3 r6 r3", "eq_r3_r6_r3"},
133 {{eq, r4, r6, r4}, true, eq, "eq r4 r6 r
[all...]
H A Dtest-assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block.cc99 {{ls, r4, r3, r6}, true, ls, "ls r4 r3 r6", "ls_r4_r3_r6"},
106 {{gt, r6, r4, r3}, true, gt, "gt r6 r4 r3", "gt_r6_r4_r3"},
108 {{eq, r4, r6, r0}, true, eq, "eq r4 r6 r0", "eq_r4_r6_r0"},
109 {{mi, r2, r6, r1}, true, mi, "mi r2 r6 r1", "mi_r2_r6_r1"},
111 {{hi, r6, r0, r2}, true, hi, "hi r6 r
[all...]
H A Dtest-assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block.cc106 {{ge, r6, r6, r1}, true, ge, "ge r6 r6 r1", "ge_r6_r6_r1"},
112 {{hi, r6, r6, r3}, true, hi, "hi r6 r6 r3", "hi_r6_r6_r3"},
113 {{ge, r7, r7, r6}, true, ge, "ge r7 r7 r6", "ge_r7_r7_r
[all...]
H A Dtest-assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block.cc96 {{{ge, r1, r1, LSL, r6}, true, ge, "ge r1 r1 LSL r6", "ge_r1_r1_LSL_r6"},
103 {{le, r6, r6, ASR, r6}, true, le, "le r6 r6 ASR r6", "le_r6_r6_ASR_r6"},
104 {{hi, r6, r6, RO
[all...]
H A Dtest-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3.cc145 {{al, r0, r6, 0}, false, al, "al r0 r6 0", "al_r0_r6_0"},
146 {{al, r0, r6, 1}, false, al, "al r0 r6 1", "al_r0_r6_1"},
147 {{al, r0, r6, 2}, false, al, "al r0 r6 2", "al_r0_r6_2"},
148 {{al, r0, r6, 3}, false, al, "al r0 r6 3", "al_r0_r6_3"},
149 {{al, r0, r6, 4}, false, al, "al r0 r6
[all...]
H A Dtest-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8.cc1633 {{al, r6, r6, 0}, false, al, "al r6 r6 0", "al_r6_r6_0"},
1634 {{al, r6, r6, 1}, false, al, "al r6 r6 1", "al_r6_r6_1"},
1635 {{al, r6, r6,
[all...]
H A Dtest-assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block.cc102 {{al, r0, r0, LSL, r6}, false, al, "al r0 r0 LSL r6", "al_r0_r0_LSL_r6"},
110 {{al, r0, r0, LSR, r6}, false, al, "al r0 r0 LSR r6", "al_r0_r0_LSR_r6"},
118 {{al, r0, r0, ASR, r6}, false, al, "al r0 r0 ASR r6", "al_r0_r0_ASR_r6"},
126 {{al, r0, r0, ROR, r6}, false, al, "al r0 r0 ROR r6", "al_r0_r0_ROR_r6"},
134 {{al, r1, r1, LSL, r6}, false, al, "al r1 r1 LSL r6", "al_r1_r1_LSL_r
[all...]
H A Dtest-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block.cc99 {{ls, r1, r6, 0}, true, ls, "ls r1 r6 0", "ls_r1_r6_0"},
102 {{vs, r5, r6, 7}, true, vs, "vs r5 r6 7", "vs_r5_r6_7"},
106 {{lt, r6, r7, 1}, true, lt, "lt r6 r7 1", "lt_r6_r7_1"},
116 {{ls, r6, r6, 4}, true, ls, "ls r6 r6
[all...]
H A Dtest-assembler-cond-rd-operand-rn-t32-low-registers-in-it-block.cc101 {{eq, r0, r6}, true, eq, "eq r0 r6", "eq_r0_r6"},
109 {{eq, r1, r6}, true, eq, "eq r1 r6", "eq_r1_r6"},
117 {{eq, r2, r6}, true, eq, "eq r2 r6", "eq_r2_r6"},
125 {{eq, r3, r6}, true, eq, "eq r3 r6", "eq_r3_r6"},
133 {{eq, r4, r6}, true, eq, "eq r4 r6", "eq_r4_r
[all...]
H A Dtest-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-in-it-block.cc101 {{eq, r0, r6, 0}, true, eq, "eq r0 r6 0", "eq_r0_r6_0"},
109 {{eq, r1, r6, 0}, true, eq, "eq r1 r6 0", "eq_r1_r6_0"},
117 {{eq, r2, r6, 0}, true, eq, "eq r2 r6 0", "eq_r2_r6_0"},
125 {{eq, r3, r6, 0}, true, eq, "eq r3 r6 0", "eq_r3_r6_0"},
133 {{eq, r4, r6, 0}, true, eq, "eq r4 r6
[all...]
H A Dtest-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block.cc98 {{vc, r6, r6, 138}, true, vc, "vc r6 r6 138", "vc_r6_r6_138"},
100 {{ge, r6, r6, 181}, true, ge, "ge r6 r6 181", "ge_r6_r6_181"},
108 {{le, r6, r6, 3
[all...]
H A Dtest-assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block.cc96 {{{ge, r7, r6, LSR, 20}, true, ge, "ge r7 r6 LSR 20", "ge_r7_r6_LSR_20"},
97 {{gt, r4, r6, LSR, 32}, true, gt, "gt r4 r6 LSR 32", "gt_r4_r6_LSR_32"},
98 {{hi, r6, r7, LSR, 29}, true, hi, "hi r6 r7 LSR 29", "hi_r6_r7_LSR_29"},
100 {{ls, r7, r6, LSR, 14}, true, ls, "ls r7 r6 LSR 14", "ls_r7_r6_LSR_14"},
106 {{gt, r6, r4, LSR, 13}, true, gt, "gt r6 r
[all...]
H A Dtest-assembler-rd-rn-rm-a32.cc109 {{r13, r6, r8}, false, al, "r13 r6 r8", "r13_r6_r8"},
113 {{r6, r0, r7}, false, al, "r6 r0 r7", "r6_r0_r7"},
121 {{r12, r2, r6}, false, al, "r12 r2 r6", "r12_r2_r6"},
124 {{r6, r3, r11}, false, al, "r6 r3 r11", "r6_r3_r11"},
130 {{r6, r5, r7}, false, al, "r6 r
[all...]
/external/libhevc/decoder/arm/
H A Dihevcd_fmt_conv_420sp_to_420p.s97 @ LDR r6,[sp,#56] @//Load u2_strideuv
113 MOV r6,r8 @// Copying width
117 SUB r6,r6,#16
120 CMP r6,#16
122 CMP r6,#0
128 RSB r6,r6,#16
129 SUB r0,r0,r6
130 SUB r2,r2,r6
[all...]
H A Dihevcd_fmt_conv_420sp_to_420sp.s105 MOV r6,r8 @// Copying width
109 SUB r6,r6,#32
118 CMP r6,#32
120 CMP r6,#0
126 RSB r6,r6,#32
127 SUB r0,r0,r6
128 SUB R2,R2,r6
161 MOV r6,r
[all...]
/external/libavc/encoder/arm/
H A Dih264e_fmt_conv.s85 mov r6, r5
91 sub r6, r6, #16
92 cmp r6, #15
95 cmp r6, #0
101 rsb r6, r6, #16
102 sub r0, r0, r6
103 sub r3, r3, r6
136 mov r6, r
[all...]
/external/libhevc/common/arm/
H A Dihevc_intra_pred_luma_mode_18_34.s130 moveq r6,#1
131 movne r6,#-1
136 vld1.8 {d0},[r8],r6
138 vld1.8 {d1},[r8],r6
140 vld1.8 {d2},[r8],r6
141 vld1.8 {d3},[r8],r6
143 vld1.8 {d4},[r8],r6
144 vld1.8 {d5},[r8],r6
145 vld1.8 {d6},[r8],r6
147 vld1.8 {d7},[r8],r6
[all...]
/external/mesa3d/src/gallium/drivers/nouveau/nvc0/mme/
H A Dcom9097.mme67 mov $r6 (extrinsrt 0x0 $r1 0x0 0x4 0x2)
69 maddr $r6 (add $r6 0x1701)
96 mov $r6 0x60
100 mov $r6 0x200
106 mov $r6 0x0
109 send $r6
135 mov $r6 0x60
139 mov $r6 0x200
145 mov $r6
[all...]
/external/libvpx/libvpx/vpx_dsp/arm/
H A Dvpx_convolve_avg_neon_asm.asm19 push {r4-r6, lr}
21 mov r6, r2
39 vld1.8 {q8-q9}, [r6@128]!
40 vld1.8 {q10-q11}, [r6@128], r4
49 pop {r4-r6, pc}
54 vld1.8 {q8-q9}, [r6@128], r3
55 vld1.8 {q10-q11}, [r6@128], r3
60 pld [r6]
62 pld [r6, r3]
68 pop {r4-r6, p
[all...]
/external/valgrind/none/tests/x86/
H A Dincdec_alt.c7 int r1,r2,r3,r4,r5,r6,r7,r8,a1,a2; variable
40 "\tpopl " VG_SYM(r6) "\n"
58 r1=r2=r3=r4=r5=r6=r7=r8=0;
65 printf("0x%08x\n",r6);
/external/compiler-rt/lib/tsan/rtl/
H A Dtsan_rtl_ppc64.S54 ld r6,-28696(r13)
56 xor r5,r6,r5
60 xor r0,r6,r0
104 addi r6,r5,16
107 stvx v21,0,r6
108 addi r6,r6,32
111 stvx v23,0,r6
112 addi r6,r6,3
[all...]
/external/webrtc/webrtc/common_audio/signal_processing/
H A Dfilter_ar_fast_q12_armv7.S30 @ r6: Calculated value for output data_out[]; interation counter for inner loop
58 subs r6, r3, #3 @ Iteration counter for inner loop.
64 subs r6, #2
85 smulbb r6, r10, r9 @ output1 = coefficients[0] * data_in[i];
86 sub r6, r7 @ output1 -= sum1;
88 sbfx r11, r6, #12, #16
89 ssat r7, #16, r6, asr #12
91 addeq r6, r6, #2048
92 ssat r6, #1
[all...]
/external/tremolo/Tremolo/
H A DmdctLARM.s61 LDMDB r2!,{r5,r6,r7,r12}
64 MOV r6, r6, ASR #9 @ r6 = (*--r)>>9
78 MOV r14,r6, ASR #15
80 EORNE r6, r4, r14,ASR #31
81 STRH r6, [r0], r3
123 LDR r6, [r2],#8
128 RSB r6, r6, #
[all...]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
H A Dbasic-arm-instructions.s48 adc r4, r5, r6
50 adc r4, r5, r6, lsl #1
51 adc r4, r5, r6, lsl #31
52 adc r4, r5, r6, lsr #1
53 adc r4, r5, r6, lsr #31
54 adc r4, r5, r6, lsr #32
55 adc r4, r5, r6, asr #1
56 adc r4, r5, r6, asr #31
57 adc r4, r5, r6, asr #32
58 adc r4, r5, r6, ro
[all...]

Completed in 1325 milliseconds

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