Searched refs:r7 (Results 1 - 25 of 425) sorted by relevance

1234567891011>>

/external/llvm/test/MC/MachO/ARM/
H A Dllvm-objdump-macho.s5 push {r7, lr}
6 pop {r7, pc}
9 push {r7, lr}
10 pop {r7, pc}
13 # CHECK: 0: 80 b5 push {r7, lr}
14 # CHECK: 2: 80 bd pop {r7, pc}
16 # CHECK: 4: 80 b5 push {r7, lr}
17 # CHECK: 6: 80 bd pop {r7, pc}
H A Dcompact-unwind-armv7k.s14 push {r4, r5, r6, r7, lr}
15 add r7, sp, #12
17 .cfi_def_cfa r7, 8
19 .cfi_offset r7, -8
31 push {r4, r5, r7, lr}
32 add r7, sp, #8
33 .cfi_def_cfa r7, 8
35 .cfi_offset r7, -8
49 push {r7, lr}
50 mov r7, s
[all...]
H A Dlong-call-branch-island-relocation.s14 push {r7, lr}
15 mov r7, sp
17 pop {r7, pc}
34 push {r7, lr}
35 mov r7, sp
36 pop {r7, pc}
/external/compiler-rt/lib/builtins/arm/
H A Dsync_synchronize.S26 stmfd sp!, {r7, lr}
27 add r7, sp, #0
29 ldmfd sp!, {r7, pc}
/external/llvm/test/MC/ARM/
H A Ddirective-fpu-instrs.s5 vldr d21, [r7, #296]
11 str r6, [r7, #264]
13 vldr d21, [r7, #296]
14 add r9, r7, #216
H A Delf-thumbfunc-reloc2.s17 push {r7, lr}
19 pop {r7, pc}
H A Dbasic-arm-instructions.s21 adc r7, r8, #(0xff << 16)
22 adc r7, r8, #-2147483638
23 adc r7, r8, #42, #2
24 adc r7, r8, #40, #2
25 adc r7, r8, $40, $2
26 adc r7, r8, 40, 2
27 adc r7, r8, (2 * 20), (1 << 1)
37 adcs r7, r8, #40, #2
44 @ CHECK: adc r7, r8, #16711680 @ encoding: [0xff,0x78,0xa8,0xe2]
45 @ CHECK: adc r7, r
[all...]
/external/mesa3d/src/gallium/drivers/nouveau/nvc0/mme/
H A Dcom9097.mme68 mov $r7 (extrinsrt 0x0 $r1 0x0 0x4 0x1)
72 maddr $r7 (add $r7 0x17c0)
93 mov $r7 (or $r1 $r2)
97 mov $r7 (and $r7 $r2)
98 braz $r7 #locn_0a_pmf
102 mov $r7 (or $r3 $r4)
103 mov $r7 (and $r7
[all...]
/external/vixl/test/aarch32/
H A Dtest-assembler-cond-rdlow-rnlow-rmlow-t32-in-it-block.cc102 {{eq, r0, r7, r0}, true, eq, "eq r0 r7 r0", "eq_r0_r7_r0"},
110 {{eq, r1, r7, r1}, true, eq, "eq r1 r7 r1", "eq_r1_r7_r1"},
118 {{eq, r2, r7, r2}, true, eq, "eq r2 r7 r2", "eq_r2_r7_r2"},
126 {{eq, r3, r7, r3}, true, eq, "eq r3 r7 r3", "eq_r3_r7_r3"},
134 {{eq, r4, r7, r4}, true, eq, "eq r4 r7 r
[all...]
H A Dtest-assembler-cond-rd-rn-operand-rm-t32-all-low-rd-is-rn-in-it-block.cc107 {{gt, r7, r7, r1}, true, gt, "gt r7 r7 r1", "gt_r7_r7_r1"},
113 {{ge, r7, r7, r6}, true, ge, "ge r7 r7 r6", "ge_r7_r7_r6"},
123 {{hi, r7, r7, r
[all...]
H A Dtest-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3.cc153 {{al, r0, r7, 0}, false, al, "al r0 r7 0", "al_r0_r7_0"},
154 {{al, r0, r7, 1}, false, al, "al r0 r7 1", "al_r0_r7_1"},
155 {{al, r0, r7, 2}, false, al, "al r0 r7 2", "al_r0_r7_2"},
156 {{al, r0, r7, 3}, false, al, "al r0 r7 3", "al_r0_r7_3"},
157 {{al, r0, r7, 4}, false, al, "al r0 r7
[all...]
H A Dtest-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8.cc1889 {{al, r7, r7, 0}, false, al, "al r7 r7 0", "al_r7_r7_0"},
1890 {{al, r7, r7, 1}, false, al, "al r7 r7 1", "al_r7_r7_1"},
1891 {{al, r7, r7,
[all...]
H A Dtest-assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block.cc103 {{al, r0, r0, LSL, r7}, false, al, "al r0 r0 LSL r7", "al_r0_r0_LSL_r7"},
111 {{al, r0, r0, LSR, r7}, false, al, "al r0 r0 LSR r7", "al_r0_r0_LSR_r7"},
119 {{al, r0, r0, ASR, r7}, false, al, "al r0 r0 ASR r7", "al_r0_r0_ASR_r7"},
127 {{al, r0, r0, ROR, r7}, false, al, "al r0 r0 ROR r7", "al_r0_r0_ROR_r7"},
135 {{al, r1, r1, LSL, r7}, false, al, "al r1 r1 LSL r7", "al_r1_r1_LSL_r
[all...]
H A Dtest-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm3-in-it-block.cc106 {{lt, r6, r7, 1}, true, lt, "lt r6 r7 1", "lt_r6_r7_1"},
112 {{ge, r7, r5, 7}, true, ge, "ge r7 r5 7", "ge_r7_r5_7"},
118 {{ge, r7, r1, 0}, true, ge, "ge r7 r1 0", "ge_r7_r1_0"},
120 {{ge, r1, r7, 0}, true, ge, "ge r1 r7 0", "ge_r1_r7_0"},
123 {{ne, r5, r7, 4}, true, ne, "ne r5 r7
[all...]
H A Dtest-assembler-cond-rd-rn-operand-rm-t32-all-low-in-it-block.cc97 {{{cs, r7, r1, r5}, true, cs, "cs r7 r1 r5", "cs_r7_r1_r5"},
104 {{ne, r1, r7, r0}, true, ne, "ne r1 r7 r0", "ne_r1_r7_r0"},
110 {{cs, r1, r4, r7}, true, cs, "cs r1 r4 r7", "cs_r1_r4_r7"},
112 {{ne, r1, r7, r1}, true, ne, "ne r1 r7 r1", "ne_r1_r7_r1"},
116 {{cc, r0, r4, r7}, true, cc, "cc r0 r4 r7", "cc_r0_r4_r
[all...]
H A Dtest-assembler-cond-rd-operand-rn-t32-low-registers-in-it-block.cc102 {{eq, r0, r7}, true, eq, "eq r0 r7", "eq_r0_r7"},
110 {{eq, r1, r7}, true, eq, "eq r1 r7", "eq_r1_r7"},
118 {{eq, r2, r7}, true, eq, "eq r2 r7", "eq_r2_r7"},
126 {{eq, r3, r7}, true, eq, "eq r3 r7", "eq_r3_r7"},
134 {{eq, r4, r7}, true, eq, "eq r4 r7", "eq_r4_r
[all...]
H A Dtest-assembler-cond-rdlow-rnlow-operand-immediate-t32-zero-in-it-block.cc102 {{eq, r0, r7, 0}, true, eq, "eq r0 r7 0", "eq_r0_r7_0"},
110 {{eq, r1, r7, 0}, true, eq, "eq r1 r7 0", "eq_r1_r7_0"},
118 {{eq, r2, r7, 0}, true, eq, "eq r2 r7 0", "eq_r2_r7_0"},
126 {{eq, r3, r7, 0}, true, eq, "eq r3 r7 0", "eq_r3_r7_0"},
134 {{eq, r4, r7, 0}, true, eq, "eq r4 r7
[all...]
H A Dtest-assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block.cc97 {{cs, r7, r7, LSL, r2}, true, cs, "cs r7 r7 LSL r2", "cs_r7_r7_LSL_r2"},
106 {{le, r7, r7, LSL, r0}, true, le, "le r7 r7 LSL r0", "le_r7_r7_LSL_r0"},
114 {{pl, r2, r2, ASR, r7}, true, pl, "pl r2 r2 ASR r7", "pl_r2_r2_ASR_r
[all...]
H A Dtest-assembler-cond-rdlow-rnlow-operand-immediate-t32-imm8-in-it-block.cc117 {{hi, r7, r7, 142}, true, hi, "hi r7 r7 142", "hi_r7_r7_142"},
130 {{lt, r7, r7, 224}, true, lt, "lt r7 r7 224", "lt_r7_r7_224"},
136 {{vs, r7, r7, 22
[all...]
H A Dtest-assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block.cc96 {{{ge, r7, r6, LSR, 20}, true, ge, "ge r7 r6 LSR 20", "ge_r7_r6_LSR_20"},
98 {{hi, r6, r7, LSR, 29}, true, hi, "hi r6 r7 LSR 29", "hi_r6_r7_LSR_29"},
99 {{mi, r7, r1, LSR, 10}, true, mi, "mi r7 r1 LSR 10", "mi_r7_r1_LSR_10"},
100 {{ls, r7, r6, LSR, 14}, true, ls, "ls r7 r6 LSR 14", "ls_r7_r6_LSR_14"},
101 {{eq, r7, r2, ASR, 14}, true, eq, "eq r7 r
[all...]
H A Dtest-assembler-cond-rdlow-rnlow-rmlow-t32.cc102 {{al, r0, r7, r0}, false, al, "al r0 r7 r0", "al_r0_r7_r0"},
110 {{al, r1, r7, r1}, false, al, "al r1 r7 r1", "al_r1_r7_r1"},
118 {{al, r2, r7, r2}, false, al, "al r2 r7 r2", "al_r2_r7_r2"},
126 {{al, r3, r7, r3}, false, al, "al r3 r7 r3", "al_r3_r7_r3"},
134 {{al, r4, r7, r4}, false, al, "al r4 r7 r
[all...]
/external/valgrind/none/tests/x86/
H A Dincdec_alt.c7 int r1,r2,r3,r4,r5,r6,r7,r8,a1,a2; variable
47 "\tmovl %eax," VG_SYM(r7) "\n"
58 r1=r2=r3=r4=r5=r6=r7=r8=0;
66 printf("0x%08x\n",r7);
/external/python/cpython2/Modules/_ctypes/libffi/src/moxie/
H A Deabi.S46 push $sp, $r7
60 mov $r7, $r5 /* Save the target fn */
76 jsr $r7
78 ldi.l $r7, 0xffffffff
79 cmp $r8, $r7
82 ldi.l $r7, 4
83 cmp $r8, $r7
97 ldo.l $r7, -8($fp)
/external/valgrind/coregrind/m_syswrap/
H A Dsyscall-arm-linux.S81 push {r0, r1, r3, r4, r5, r7, fp, lr}
85 mov r7, #__NR_rt_sigprocmask
95 ldr r7, [sp, #0] /* syscall# */
109 mov r7, #__NR_rt_sigprocmask
122 pop {r1, r3, r4, r5, r7, fp, pc}
126 pop {r1, r3, r4, r5, r7, fp, pc}
/external/boringssl/ios-arm/crypto/fipsmodule/
H A Dsha1-armv4-large.S32 stmdb sp!,{r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
34 ldmia r0,{r3,r4,r5,r6,r7}
41 mov r7,r7,ror#30 @ [6]
47 add r7,r8,r7,ror#2 @ E+=K_00_19
52 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
56 add r7,r8,r7,ro
[all...]

Completed in 1425 milliseconds

1234567891011>>