/external/mesa3d/src/gallium/drivers/nouveau/nv50/ |
H A D | nv50_transfer.h | 18 uint16_t tile_mode; member in struct:nv50_m2mf_rect
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H A D | nv50_miptree.c | 35 uint32_t tile_mode = 0x000; local 37 if (ny > 64) tile_mode = 0x040; /* height 128 tiles */ 39 if (ny > 32) tile_mode = 0x030; /* height 64 tiles */ 41 if (ny > 16) tile_mode = 0x020; /* height 32 tiles */ 43 if (ny > 8) tile_mode = 0x010; /* height 16 tiles */ 46 return tile_mode; 48 if (tile_mode > 0x020) 49 tile_mode = 0x020; 51 if (nz > 16 && tile_mode < 0x020) 52 return tile_mode | [all...] |
H A D | nv50_resource.h | 43 uint32_t tile_mode; member in struct:nv50_miptree_level
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H A D | nv50_transfer.c | 41 rect->tile_mode = mt->level[l].tile_mode; 79 PUSH_DATA (push, src->tile_mode); 96 PUSH_DATA (push, dst->tile_mode);
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H A D | nv50_tex.c | 157 ((mt->level[0].tile_mode & 0x0f0) << (22 - 4)) | 158 ((mt->level[0].tile_mode & 0xf00) << (25 - 8));
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/external/mesa3d/src/gallium/drivers/nouveau/nvc0/ |
H A D | nvc0_miptree.c | 177 mt->level[0].tile_mode = 0x10; 214 lvl->tile_mode = nvc0_tex_choose_tile_dims(nbx, nby, d, mt->layout_3d); 216 tsx = NVC0_TILE_SIZE_X(lvl->tile_mode); /* x is tile row pitch in bytes */ 217 tsy = NVC0_TILE_SIZE_Y(lvl->tile_mode); 218 tsz = NVC0_TILE_SIZE_Z(lvl->tile_mode); 231 NVC0_TILE_SIZE(mt->level[0].tile_mode)); 300 bo_config.nvc0.tile_mode = mt->level[0].tile_mode; 333 unsigned tds = NVC0_TILE_SHIFT_Z(mt->level[l].tile_mode); 334 unsigned ths = NVC0_TILE_SHIFT_Y(mt->level[l].tile_mode); [all...] |
H A D | nvc0_video_bsp.c | 71 cfg.nvc0.tile_mode = 0x10; 107 cfg.nvc0.tile_mode = 0x10;
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H A D | nvc0_tex.c | 161 ((mt->level[0].tile_mode & 0x0f0) >> 4 << 3) | 162 ((mt->level[0].tile_mode & 0xf00) >> 8 << 6); 368 ((mt->level[0].tile_mode & 0x0f0) << (22 - 4)) | 369 ((mt->level[0].tile_mode & 0xf00) << (25 - 8)); 932 info[4] |= (lvl->tile_mode & 0x0f0) << 25; 933 info[4] |= NVC0_TILE_SHIFT_Y(lvl->tile_mode) << 22; 936 info[6] |= (lvl->tile_mode & 0xf00) << 21; 937 info[6] |= NVC0_TILE_SHIFT_Z(lvl->tile_mode) << 22; 1053 PUSH_DATA (push, lvl->tile_mode & 0xff); /* mask out z-tiling */
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H A D | nvc0_transfer.c | 39 PUSH_DATA (push, src->tile_mode); 55 PUSH_DATA (push, dst->tile_mode); 143 PUSH_DATA (push, 0x1000 | dst->tile_mode); 151 PUSH_DATA (push, 0x1000 | src->tile_mode);
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H A D | nvc0_video.c | 99 cfg.nvc0.tile_mode = 0x10;
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/external/libdrm/nouveau/ |
H A D | abi16.c | 298 bo->config.nvc0.tile_mode = info->tile_mode; 303 bo->config.nv50.tile_mode = info->tile_mode << 4; 306 bo->config.nv04.surf_pitch = info->tile_mode; 343 info->tile_mode = config->nvc0.tile_mode; 348 info->tile_mode = config->nv50.tile_mode >> 4; 351 info->tile_mode [all...] |
H A D | nouveau.h | 103 uint32_t tile_mode; member in struct:nouveau_bo_config::__anon10557 107 uint32_t tile_mode; member in struct:nouveau_bo_config::__anon10558
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/external/libdrm/radeon/ |
H A D | radeon_surface.c | 1291 unsigned mode, unsigned *tile_mode, unsigned *stencil_tile_mode) 1356 *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D; 1359 *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D_2AA; 1362 *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D_4AA; 1365 *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_2D_8AA; 1373 *tile_mode = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP; 1376 *tile_mode = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP; 1384 *tile_mode = SI_TILE_MODE_COLOR_2D_8BPP; 1387 *tile_mode = SI_TILE_MODE_COLOR_2D_16BPP; 1390 *tile_mode 1289 si_surface_sanity(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, unsigned mode, unsigned *tile_mode, unsigned *stencil_tile_mode) argument 1520 si_surface_init_linear_aligned(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, unsigned tile_mode, uint64_t offset, unsigned start_level) argument 1553 si_surface_init_1d(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, struct radeon_surface_level *level, unsigned bpe, unsigned tile_mode, uint64_t offset, unsigned start_level) argument 1602 si_surface_init_1d_miptrees(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, unsigned tile_mode, unsigned stencil_tile_mode) argument 1620 si_surface_init_2d(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, struct radeon_surface_level *level, unsigned bpe, unsigned tile_mode, unsigned num_pipes, unsigned num_banks, unsigned tile_split, uint64_t offset, unsigned start_level) argument 1704 si_surface_init_2d_miptrees(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, unsigned tile_mode, unsigned stencil_tile_mode) argument 1731 unsigned mode, tile_mode, stencil_tile_mode; local 1791 unsigned mode, tile_mode, stencil_tile_mode; local 1860 cik_get_2d_params(struct radeon_surface_manager *surf_man, unsigned bpe, unsigned nsamples, bool is_color, unsigned tile_mode, uint32_t *num_pipes, uint32_t *tile_split_ptr, uint32_t *num_banks, uint32_t *macro_tile_aspect, uint32_t *bank_w, uint32_t *bank_h) argument 2119 cik_surface_sanity(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, unsigned mode, unsigned *tile_mode, unsigned *stencil_tile_mode) argument 2217 cik_surface_init_2d(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, struct radeon_surface_level *level, unsigned bpe, unsigned tile_mode, unsigned tile_split, unsigned num_pipes, unsigned num_banks, uint64_t offset, unsigned start_level) argument 2306 cik_surface_init_2d_miptrees(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, unsigned tile_mode, unsigned stencil_tile_mode) argument 2335 unsigned mode, tile_mode, stencil_tile_mode; local 2395 unsigned mode, tile_mode, stencil_tile_mode; local [all...] |
/external/mesa3d/src/gallium/drivers/radeonsi/ |
H A D | si_dma.c | 146 unsigned tile_mode = info->si_tile_mode_array[index]; local 169 array_mode = G_009910_ARRAY_MODE(tile_mode); 182 bank_h = G_009910_BANK_HEIGHT(tile_mode); 183 bank_w = G_009910_BANK_WIDTH(tile_mode); 184 mt_aspect = G_009910_MACRO_TILE_ASPECT(tile_mode); 187 nbanks = G_009910_NUM_BANKS(tile_mode); 191 pipe_config = G_009910_PIPE_CONFIG(tile_mode); 192 mt = G_009910_MICRO_TILE_MODE(tile_mode);
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H A D | cik_sdma.c | 125 unsigned tile_mode = info->si_tile_mode_array[tile_index]; local 129 (G_009910_ARRAY_MODE(tile_mode) << 3) | 130 (G_009910_MICRO_TILE_MODE_NEW(tile_mode) << 8) | 137 (G_009910_PIPE_CONFIG(tile_mode) << 26);
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/external/mesa3d/src/gallium/winsys/radeon/drm/ |
H A D | radeon_drm_surface.c | 54 uint32_t tile_mode; local 61 tile_mode = info->si_tile_mode_array[surf->tiling_index[0]]; 64 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode); 66 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
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/external/libdrm/include/drm/ |
H A D | nouveau_drm.h | 121 uint32_t tile_mode; member in struct:drm_nouveau_gem_info 127 uint32_t tile_mode; member in struct:drm_nouveau_gem_set_tiling 254 uint32_t tile_mode; member in struct:drm_nouveau_gem_map
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/external/kernel-headers/original/uapi/drm/ |
H A D | nouveau_drm.h | 55 __u32 tile_mode; member in struct:drm_nouveau_gem_info
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/external/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
H A D | radv_amdgpu_surface.c | 269 uint32_t tile_mode = info->si_tile_mode_array[surf->tiling_index[0]]; local 272 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode); 274 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
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/external/libdrm/libkms/ |
H A D | nouveau.c | 113 arg.info.tile_mode = 0;
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/external/mesa3d/src/gallium/drivers/freedreno/a5xx/ |
H A D | fd5_gmem.c | 49 enum a5xx_tile_mode tile_mode; local 53 tile_mode = TILE5_2; 55 tile_mode = TILE5_LINEAR; 97 A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
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/external/mesa3d/src/gallium/winsys/amdgpu/drm/ |
H A D | amdgpu_surface.c | 278 uint32_t tile_mode = info->si_tile_mode_array[surf->tiling_index[0]]; local 281 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode); 283 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
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/external/mesa3d/src/gallium/drivers/freedreno/a4xx/ |
H A D | fd4_gmem.c | 52 enum a4xx_tile_mode tile_mode; local 56 tile_mode = 2; 58 tile_mode = TILE4_LINEAR; 116 A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
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/external/mesa3d/src/gallium/drivers/freedreno/a3xx/ |
H A D | fd3_gmem.c | 51 enum a3xx_tile_mode tile_mode; local 55 tile_mode = TILE_32X32; 57 tile_mode = LINEAR; 113 A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
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/external/mesa3d/src/amd/vulkan/ |
H A D | radv_device.c | 1782 unsigned tile_mode = info->si_tile_mode_array[tiling_index]; local 1787 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) | 1788 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) | 1793 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
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