/external/llvm/test/MC/AArch64/ |
H A D | arm64-basic-a64-instructions.s | 3 crc32b w5, w7, w20 6 crc32x w7, w9, x20 11 // CHECK: crc32b w5, w7, w20 // encoding: [0xe5,0x40,0xd4,0x1a] 14 // CHECK: crc32x w7, w9, x20 // encoding: [0x27,0x4d,0xd4,0x9a]
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H A D | arm64-diagno-predicate.s | 20 crc32b w5, w7, w20 22 // CHECK-ERROR-NEXT: crc32b w5, w7, w20
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H A D | cyclone-crc.s | 17 crc32ch w3, w5, w7 23 CHECK: crc32ch w3, w5, w7
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H A D | alias-addsubimm.s | 87 // CHECK: {{adds wzr,|cmn}} w7, #5 88 // CHECK: {{adds wzr,|cmn}} w7, #5 89 cmn w7, #5 90 cmp w7, #-5
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H A D | arm64-tls-relocs.s | 56 movz w7, #:tprel_g1:var 61 // CHECK: movz w7, #:tprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12] 180 movz w7, #:dtprel_g1:var 185 // CHECK: movz w7, #:dtprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12]
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H A D | tls-relocs.s | 30 movz w7, #:dtprel_g1:var 37 // CHECK: movz w7, #:dtprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12] 232 movz w7, #:tprel_g1:var 239 // CHECK: movz w7, #:tprel_g1:var // encoding: [0bAAA00111,A,0b101AAAAA,0x12]
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/external/llvm/test/MC/Mips/msa/ |
H A D | test_vec.s | 4 # CHECK: bmnz.v $w17, $w6, $w7 # encoding: [0x78,0x87,0x34,0x5e] 7 # CHECK: nor.v $w7, $w31, $w0 # encoding: [0x78,0x40,0xf9,0xde] 9 # CHECK: xor.v $w7, $w27, $w15 # encoding: [0x78,0x6f,0xd9,0xde] 12 bmnz.v $w17, $w6, $w7 15 nor.v $w7, $w31, $w0 17 xor.v $w7, $w27, $w15
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H A D | test_3r.s | 76 # CHECK: cle_u.h $w7, $w0, $w29 # encoding: [0x7a,0xbd,0x01,0xcf] 82 # CHECK: clt_s.d $w7, $w30, $w12 # encoding: [0x79,0x6c,0xf1,0xcf] 86 # CHECK: clt_u.d $w7, $w0, $w1 # encoding: [0x79,0xe1,0x01,0xcf] 108 # CHECK: dpsub_s.w $w4, $w7, $w6 # encoding: [0x7a,0x46,0x39,0x13] 112 # CHECK: dpsub_u.d $w7, $w10, $w26 # encoding: [0x7a,0xfa,0x51,0xd3] 122 # CHECK: hsub_u.h $w7, $w12, $w14 # encoding: [0x7b,0xae,0x61,0xd5] 142 # CHECK: maddv.h $w7, $w24, $w9 # encoding: [0x78,0xa9,0xc1,0xd2] 147 # CHECK: max_a.w $w7, $w18, $w30 # encoding: [0x7b,0x5e,0x91,0xce] 154 # CHECK: max_u.h $w5, $w6, $w7 # encoding: [0x79,0xa7,0x31,0x4e] 155 # CHECK: max_u.w $w16, $w4, $w7 # encodin [all...] |
H A D | test_2rf.s | 11 # CHECK: ffint_u.w $w7, $w27 # encoding: [0x7b,0x3e,0xd9,0xde] 19 # CHECK: frint.w $w7, $w15 # encoding: [0x7b,0x2c,0x79,0xde] 44 ffint_u.w $w7, $w27 52 frint.w $w7, $w15
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H A D | test_i5.s | 16 # CHECK: clei_u.h $w29, $w7, 17 # encoding: [0x7a,0xb1,0x3f,0x47] 40 # CHECK: mini_u.h $w7, $w26, 18 # encoding: [0x7a,0xb2,0xd1,0xc6] 61 clei_u.h $w29, $w7, 17 85 mini_u.h $w7, $w26, 18
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H A D | test_mi10.s | 11 ld.h $w7, 1022($8) # CHECK: ld.h $w7, 1022($8) # encoding: [0x79,0xff,0x41,0xe1]
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H A D | test_bit.s | 22 # CHECK: bseti.d $w7, $w15, 1 # encoding: [0x7a,0x01,0x79,0xc9] 37 # CHECK: srai.w $w7, $w26, 1 # encoding: [0x78,0xc1,0xd1,0xc9] 40 # CHECK: srari.h $w7, $w6, 4 # encoding: [0x79,0x64,0x31,0xca] 71 bseti.d $w7, $w15, 1 86 srai.w $w7, $w26, 1 89 srari.h $w7, $w6, 4
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/external/libhevc/common/arm64/ |
H A D | ihevc_intra_pred_chroma_planar.s | 129 ldr w7, [x6] 130 sxtw x7,w7 131 dup v0.4h,w7 //src[nt-1] 138 ldr w7, [x6] 139 sxtw x7,w7 140 dup v1.4h,w7 //src[3nt+1] 185 ldr w7, [x6], #-2 //src[2nt-1-row] (dec to take into account row) 186 sxtw x7,w7 191 dup v4.4h,w7 //src[2nt-1-row] 199 ldr w7, [x [all...] |
/external/openssh/ |
H A D | blocks.c | 59 M(w6 ,w4 ,w15,w7 ) \ 60 M(w7 ,w5 ,w0 ,w8 ) \ 62 M(w9 ,w7 ,w2 ,w10) \ 67 M(w14,w12,w7 ,w15) \ 113 uint64 w7 = load_bigendian(in + 56); local 130 F(w7 ,0xab1c5ed5da6d8118ULL) 149 F(w7 ,0x76f988da831153b5ULL) 168 F(w7 ,0x92722c851482353bULL) 187 F(w7 ,0x682e6ff3d6b2b8a3ULL) 206 F(w7 , [all...] |
/external/boringssl/ios-aarch64/crypto/fipsmodule/ |
H A D | sha1-armv8.S | 94 add w20,w20,w7 // future e+=X[i] 248 eor w5,w5,w7 274 eor w7,w7,w9 278 eor w7,w7,w15 282 eor w7,w7,w4 286 ror w7,w7,#3 [all...] |
H A D | sha256-armv8.S | 117 eor w7,w23,w23,ror#14 123 eor w16,w16,w7,ror#11 // Sigma1(e) 124 ror w7,w27,#2 131 eor w17,w7,w17,ror#13 // Sigma0(a) 162 ldp w7,w8,[x1],#2*4 185 rev w7,w7 // 4 193 add w23,w23,w7 // h+=X[i] 385 str w7,[sp,#0] 388 eor w7,w2 [all...] |
/external/boringssl/linux-aarch64/crypto/fipsmodule/ |
H A D | sha1-armv8.S | 95 add w20,w20,w7 // future e+=X[i] 249 eor w5,w5,w7 275 eor w7,w7,w9 279 eor w7,w7,w15 283 eor w7,w7,w4 287 ror w7,w7,#3 [all...] |
H A D | sha256-armv8.S | 118 eor w7,w23,w23,ror#14 124 eor w16,w16,w7,ror#11 // Sigma1(e) 125 ror w7,w27,#2 132 eor w17,w7,w17,ror#13 // Sigma0(a) 163 ldp w7,w8,[x1],#2*4 186 rev w7,w7 // 4 194 add w23,w23,w7 // h+=X[i] 386 str w7,[sp,#0] 389 eor w7,w2 [all...] |
/external/libavc/common/armv8/ |
H A D | ih264_weighted_pred_av8.s | 106 // w7 => ht 150 subs w7, w7, #4 //decrement ht by 4 201 subs w7, w7, #4 //decrement ht by 4 257 subs w7, w7, #4 //decrement ht by 4 336 // w7 => ht 377 subs w7, w7, # [all...] |
/external/valgrind/none/tests/arm64/ |
H A D | integer.stdout.exp | 507 add w7,w8,w9,lsl #0 :: rd 000000007e23f68a rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 00000000 508 add w7,w8,w9,lsl #1 :: rd 000000005e37e3dc rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv 00000000 509 add w7,w8,w9,lsl #30 :: rd 0000000029b876ab rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv 00000000 510 add w7,w8,w9,lsl #31 :: rd 0000000015990527 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 00000000 511 adds w7,w8,w9,lsl #0 :: rd 000000007e23f68a rm 2b7c5939d7c0f528, rn b73870a5a6630162, cin 0, nzcv 30000000 CV 512 adds w7,w8,w9,lsl #1 :: rd 000000005e37e3dc rm fc9a9d8be2434f5e, rn 6a13f7db3dfa4a3f, cin 0, nzcv 20000000 C 513 adds w7,w8,w9,lsl #30 :: rd 0000000029b876ab rm d98d2022a9b876ab, rn a7e754e8ff3a554e, cin 0, nzcv 30000000 CV 514 adds w7,w8,w9,lsl #31 :: rd 0000000015990527 rm 33566e6515990527, rn 3d7e7390195d82e2, cin 0, nzcv 00000000 515 adds w7,w8,w9,lsl #0 :: rd 0000000000000000 rm 5555555555555556, rn aaaaaaaaaaaaaaaa, cin 0, nzcv 60000000 ZC 516 add w7,w [all...] |
/external/boringssl/ios-aarch64/crypto/chacha/ |
H A D | chacha-armv8.S | 67 mov w7,w23 88 add w7,w7,w11 92 eor w20,w20,w7 112 add w7,w7,w11 116 eor w20,w20,w7 136 add w7,w7,w12 140 eor w19,w19,w7 [all...] |
/external/boringssl/linux-aarch64/crypto/chacha/ |
H A D | chacha-armv8.S | 68 mov w7,w23 89 add w7,w7,w11 93 eor w20,w20,w7 113 add w7,w7,w11 117 eor w20,w20,w7 137 add w7,w7,w12 141 eor w19,w19,w7 [all...] |
/external/libmpeg2/common/armv8/ |
H A D | impeg2_format_conv.s | 183 ldr w7, [sp, #88] //// Load u2_strideu from stack 184 sxtw x7, w7 356 ldr w7, [sp, #80] //// Load u2_strideu from stack 357 sxtw x7, w7
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/external/libhevc/decoder/arm64/ |
H A D | ihevcd_fmt_conv_420sp_to_420p.s | 145 LDR w7, [sp,#80] ////Load u2_strideuv 146 sxtw x7,w7
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/external/llvm/test/MC/Mips/mips32r2/ |
H A D | invalid-msa.s | 11 bsel.v $w28,$w7,$w0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 44 ftrunc_s.w $w24,$w7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 46 ftrunc_u.w $w7,$w26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 49 nloc.d $w16,$w7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 52 nlzc.b $w12,$w7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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