Searched refs:Vd (Results 1 - 13 of 13) sorted by relevance

/external/v8/src/arm/
H A Dsimulator-arm.cc4009 void AddSaturate(Simulator* simulator, int Vd, int Vm, int Vn) { argument
4017 simulator->set_q_register(Vd, src1);
4021 void SubSaturate(Simulator* simulator, int Vd, int Vm, int Vn) { argument
4029 simulator->set_q_register(Vd, src1);
4035 int Vd, Vm, Vn; local
4037 Vd = instr->VFPDRegValue(kDoublePrecision);
4041 Vd = instr->VFPDRegValue(kSimd128Precision);
4052 AddSaturate<int8_t>(this, Vd, Vm, Vn);
4055 AddSaturate<int16_t>(this, Vd, Vm, Vn);
4058 AddSaturate<int32_t>(this, Vd, V
4429 int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1); local
4447 int Vd = instr->VFPDRegValue(kSimd128Precision); local
4466 int Vd = instr->VFPDRegValue(kSimd128Precision); local
4505 int Vd = instr->VFPDRegValue(kSimd128Precision); local
4545 int Vd, Vm, Vn; local
4862 int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1); local
4881 int Vd = instr->VFPDRegValue(kSimd128Precision); local
4975 int Vd = instr->VFPDRegValue(kSimd128Precision); local
5026 int Vd = instr->VFPDRegValue(kSimd128Precision); local
5110 int Vd = instr->VFPDRegValue(kSimd128Precision); local
5207 int Vd = instr->VFPDRegValue(kSimd128Precision); local
5236 int Vd = instr->VFPDRegValue(kSimd128Precision); local
5278 int Vd = (instr->Bit(22) << 4) | instr->VdValue(); local
5319 int Vd = (instr->Bit(22) << 4) | instr->VdValue(); local
[all...]
H A Ddisasm-arm.cc90 void FormatNeonList(int Vd, int type);
369 // vmov.32 has Vd in a different place.
401 void Decoder::FormatNeonList(int Vd, int type) { argument
404 "{d%d}", Vd);
407 "{d%d, d%d}", Vd, Vd + 1);
410 "{d%d, d%d, d%d}", Vd, Vd + 1, Vd + 2);
413 "{d%d, d%d, d%d, d%d}", Vd, V
1570 int Vd = instr->VFPNRegValue(kSimd128Precision); local
1860 int Vd, Vm, Vn; local
2008 int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1); local
2016 int Vd = instr->VFPDRegValue(kSimd128Precision); local
2026 int Vd = instr->VFPDRegValue(kSimd128Precision); local
2035 int Vd = instr->VFPDRegValue(kSimd128Precision); local
2045 int Vd, Vm, Vn; local
2163 int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1); local
2172 int Vd = instr->VFPDRegValue(kDoublePrecision); local
2177 int Vd = instr->VFPDRegValue(kSimd128Precision); local
2183 int Vd = instr->VFPDRegValue(kSimd128Precision); local
2189 int Vd = instr->VFPDRegValue(kSimd128Precision); local
2195 int Vd = instr->VFPDRegValue(kSimd128Precision); local
2216 int Vd = instr->VFPDRegValue(kDoublePrecision); local
2228 int Vd = instr->VFPDRegValue(kSimd128Precision); local
2235 int Vd = instr->VFPDRegValue(kSimd128Precision); local
2244 int Vd = instr->VFPDRegValue(kSimd128Precision); local
2263 int Vd = instr->VFPDRegValue(kSimd128Precision); local
2275 int Vd = instr->VFPDRegValue(kSimd128Precision); local
2287 int Vd = (instr->Bit(22) << 4) | instr->VdValue(); local
2300 int Vd = (instr->Bit(22) << 4) | instr->VdValue(); local
[all...]
H A Dassembler-arm.cc2406 // Vd(15-12) | 1011(11-8) | offset
2505 // Vd(15-12) | 1011(11-8) | (offset/4)
2732 // Vd(15-12) | 101(11-9) | sz=0(8) | imm4L(3-0)
2762 // Vd(15-12) | 101(11-9) | sz=1(8) | imm4L(3-0)
2845 // cond(31-28) | 11101(27-23) | D(22) | 11(21-20) | 0000(19-16) | Vd(15-12) |
2864 // Vd(19-16) | Rt(15-12) | 1011(11-8) | D(7) | opc2=00(6-5) | 1(4) | 0000(3-0)
3027 int D, Vd, M, Vm; local
3029 SplitRegCode(dst_type, dst_code, &Vd, &D);
3035 // Vd(15-12) | 101(11-9) | sz(8) | op(7) | 1(6) | M(5) | 0(4) | Vm(3-0)
3052 Vd*B1
[all...]
/external/clang/include/clang/Analysis/Analyses/
H A DThreadSafetyTIL.h364 Variable(const Variable &Vd, SExpr *D) // rewrite constructor argument
365 : SExpr(Vd), Name(Vd.Name), Definition(D), Cvdecl(Vd.Cvdecl) {
366 Flags = Vd.kind();
659 Function(Variable *Vd, SExpr *Bd) argument
660 : SExpr(COP_Function), VarDecl(Vd), Body(Bd) {
661 Vd->setKind(Variable::VK_Fun);
663 Function(const Function &F, Variable *Vd, SExpr *Bd) // rewrite constructor argument
664 : SExpr(F), VarDecl(Vd), Bod
710 SFunction(Variable *Vd, SExpr *B) argument
716 SFunction(const SFunction &F, Variable *Vd, SExpr *B) argument
1866 Let(Variable *Vd, SExpr *Bd) argument
1869 Let(const Let &L, Variable *Vd, SExpr *Bd) argument
[all...]
/external/clang/lib/Analysis/
H A DThreadSafety.cpp243 bool containsMutexDecl(FactManager &FM, const ValueDecl* Vd) const {
245 return FM[ID].valueDecl() == Vd;
275 BeforeInfo* insertAttrExprs(const ValueDecl* Vd,
278 BeforeInfo *getBeforeInfoForDecl(const ValueDecl *Vd,
281 void checkBeforeAfter(const ValueDecl* Vd,
966 /// Process acquired_before and acquired_after attributes on Vd.
967 BeforeSet::BeforeInfo* BeforeSet::insertAttrExprs(const ValueDecl* Vd,
969 // Create a new entry for Vd.
974 std::unique_ptr<BeforeInfo> &InfoPtr = BMap[Vd];
980 for (Attr* At : Vd
[all...]
/external/v8/benchmarks/
H A Draytrace.js481 var Vd = this.position.dot(ray.direction);
482 if(Vd == 0) return info; // no intersection
484 var t = -(this.position.dot(ray.position) + this.d) / Vd;
/external/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1249 unsigned Vd = fieldFromInstruction(Val, 8, 5); local
1253 if (regs == 0 || (Vd + regs) > 32) {
1254 regs = Vd + regs > 32 ? 32 - Vd : regs;
1259 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1262 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1273 unsigned Vd = fieldFromInstruction(Val, 8, 5); local
1277 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1278 regs = Vd + regs > 32 ? 32 - Vd
5129 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); local
5188 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); local
[all...]
/external/valgrind/VEX/priv/
H A Dhost_arm_defs.c3922 UInt D, Vd, M, Vm; local
3925 Vd = rDst & 0xF;
3929 Vd = (rDst >> 1) & 0xF;
3934 vassert(D <= 1 && Vd <= 15 && M <= 1 && Vm <= 15);
3935 *p++ = XXXXXXXX(0xE, X1110, X1011 | (D << 2), X0110, Vd,
3947 UInt D, Vd, N, Vn, M, Vm; local
3950 Vd = rDst & 0xF;
3956 Vd = (rDst >> 1) & 0xF;
3963 vassert(D <= 1 && Vd <= 15 && M <= 1 && Vm <= 15 && N <= 1
3965 *p++ = XXXXXXXX(X1111,X1110, X1000 | (D << 2), Vn, Vd,
4726 UInt Vd = regD & 0xF; local
[all...]
H A Dguest_arm_toIR.c13540 T1/A1: 111111101 D 1110 rm Vd 101 1 01 M 0 Vm VRINT{A,N,P,M}.F64 Dd, Dm
13541 T1/A1: 111111101 D 1110 rm Vd 101 0 01 M 0 Vm VRINT{A,N,P,M}.F32 Sd, Sm
13592 T1: 1110 11101 D 110110 Vd 1011 op 1 M 0 Vm VRINT<r><c>.F64.F64 Dd, Dm
13593 A1: cond 11101 D 110110 Vd 1011 op 1 M 0 Vm
13595 T1: 1110 11101 D 110110 Vd 1010 op 1 M 0 Vm VRINT<r><c>.F32.F32 Sd, Sm
13596 A1: cond 11101 D 110110 Vd 1010 op 1 M 0 Vm
13634 T1/A1: 1111 11101 D 1111 rm Vd 101 sz op 1 M 0 Vm
13696 1111 11101 D 00 Vn Vd 101 1 N op M 0 Vm V{MIN,MAX}NM.F64 Dd, Dn, Dm
13697 1111 11101 D 00 Vn Vd 101 0 N op M 0 Vm V{MIN,MAX}NM.F32 Sd, Sn, Sm
13740 T1: 1110 11101 D 110111 Vd 10
15796 UInt Vd = INSN(15,12); local
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1130 unsigned Vd = fieldFromInstruction32(Val, 8, 4); local
1133 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1136 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1147 unsigned Vd = fieldFromInstruction32(Val, 8, 4); local
1150 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1153 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
/external/llvm/tools/llvm-objdump/
H A DMachODump.cpp8945 MachO::version_min_command Vd = Obj->getVersionMinLoadCommand(Command); local
8946 PrintVersionMinLoadCommand(Vd);
/external/webrtc/data/voice_engine/stereo_rtp_files/
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/external/webrtc/talk/media/testdata/
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