CGBuiltin.cpp revision 9631939f82c0eaa6fb3936a0ce58a41adfbc9011 
1//===---- CGBuiltin.cpp - Emit LLVM Code for builtins ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This contains code to emit Builtin calls as LLVM code.
11//
12//===----------------------------------------------------------------------===//
13
14#include "TargetInfo.h"
15#include "CodeGenFunction.h"
16#include "CodeGenModule.h"
17#include "CGObjCRuntime.h"
18#include "clang/Basic/TargetInfo.h"
19#include "clang/AST/APValue.h"
20#include "clang/AST/ASTContext.h"
21#include "clang/AST/Decl.h"
22#include "clang/Basic/TargetBuiltins.h"
23#include "llvm/Intrinsics.h"
24#include "llvm/Target/TargetData.h"
25
26using namespace clang;
27using namespace CodeGen;
28using namespace llvm;
29
30/// getBuiltinLibFunction - Given a builtin id for a function like
31/// "__builtin_fabsf", return a Function* for "fabsf".
32llvm::Value *CodeGenModule::getBuiltinLibFunction(const FunctionDecl *FD,
33                                                  unsigned BuiltinID) {
34  assert(Context.BuiltinInfo.isLibFunction(BuiltinID));
35
36  // Get the name, skip over the __builtin_ prefix (if necessary).
37  StringRef Name;
38  GlobalDecl D(FD);
39
40  // If the builtin has been declared explicitly with an assembler label,
41  // use the mangled name. This differs from the plain label on platforms
42  // that prefix labels.
43  if (FD->hasAttr<AsmLabelAttr>())
44    Name = getMangledName(D);
45  else
46    Name = Context.BuiltinInfo.GetName(BuiltinID) + 10;
47
48  llvm::FunctionType *Ty =
49    cast<llvm::FunctionType>(getTypes().ConvertType(FD->getType()));
50
51  return GetOrCreateLLVMFunction(Name, Ty, D, /*ForVTable=*/false);
52}
53
54/// Emit the conversions required to turn the given value into an
55/// integer of the given size.
56static Value *EmitToInt(CodeGenFunction &CGF, llvm::Value *V,
57                        QualType T, llvm::IntegerType *IntType) {
58  V = CGF.EmitToMemory(V, T);
59
60  if (V->getType()->isPointerTy())
61    return CGF.Builder.CreatePtrToInt(V, IntType);
62
63  assert(V->getType() == IntType);
64  return V;
65}
66
67static Value *EmitFromInt(CodeGenFunction &CGF, llvm::Value *V,
68                          QualType T, llvm::Type *ResultType) {
69  V = CGF.EmitFromMemory(V, T);
70
71  if (ResultType->isPointerTy())
72    return CGF.Builder.CreateIntToPtr(V, ResultType);
73
74  assert(V->getType() == ResultType);
75  return V;
76}
77
78/// Utility to insert an atomic instruction based on Instrinsic::ID
79/// and the expression node.
80static RValue EmitBinaryAtomic(CodeGenFunction &CGF,
81                               llvm::AtomicRMWInst::BinOp Kind,
82                               const CallExpr *E) {
83  QualType T = E->getType();
84  assert(E->getArg(0)->getType()->isPointerType());
85  assert(CGF.getContext().hasSameUnqualifiedType(T,
86                                  E->getArg(0)->getType()->getPointeeType()));
87  assert(CGF.getContext().hasSameUnqualifiedType(T, E->getArg(1)->getType()));
88
89  llvm::Value *DestPtr = CGF.EmitScalarExpr(E->getArg(0));
90  unsigned AddrSpace =
91    cast<llvm::PointerType>(DestPtr->getType())->getAddressSpace();
92
93  llvm::IntegerType *IntType =
94    llvm::IntegerType::get(CGF.getLLVMContext(),
95                           CGF.getContext().getTypeSize(T));
96  llvm::Type *IntPtrType = IntType->getPointerTo(AddrSpace);
97
98  llvm::Value *Args[2];
99  Args[0] = CGF.Builder.CreateBitCast(DestPtr, IntPtrType);
100  Args[1] = CGF.EmitScalarExpr(E->getArg(1));
101  llvm::Type *ValueType = Args[1]->getType();
102  Args[1] = EmitToInt(CGF, Args[1], T, IntType);
103
104  llvm::Value *Result =
105      CGF.Builder.CreateAtomicRMW(Kind, Args[0], Args[1],
106                                  llvm::SequentiallyConsistent);
107  Result = EmitFromInt(CGF, Result, T, ValueType);
108  return RValue::get(Result);
109}
110
111/// Utility to insert an atomic instruction based Instrinsic::ID and
112/// the expression node, where the return value is the result of the
113/// operation.
114static RValue EmitBinaryAtomicPost(CodeGenFunction &CGF,
115                                   llvm::AtomicRMWInst::BinOp Kind,
116                                   const CallExpr *E,
117                                   Instruction::BinaryOps Op) {
118  QualType T = E->getType();
119  assert(E->getArg(0)->getType()->isPointerType());
120  assert(CGF.getContext().hasSameUnqualifiedType(T,
121                                  E->getArg(0)->getType()->getPointeeType()));
122  assert(CGF.getContext().hasSameUnqualifiedType(T, E->getArg(1)->getType()));
123
124  llvm::Value *DestPtr = CGF.EmitScalarExpr(E->getArg(0));
125  unsigned AddrSpace =
126    cast<llvm::PointerType>(DestPtr->getType())->getAddressSpace();
127
128  llvm::IntegerType *IntType =
129    llvm::IntegerType::get(CGF.getLLVMContext(),
130                           CGF.getContext().getTypeSize(T));
131  llvm::Type *IntPtrType = IntType->getPointerTo(AddrSpace);
132
133  llvm::Value *Args[2];
134  Args[1] = CGF.EmitScalarExpr(E->getArg(1));
135  llvm::Type *ValueType = Args[1]->getType();
136  Args[1] = EmitToInt(CGF, Args[1], T, IntType);
137  Args[0] = CGF.Builder.CreateBitCast(DestPtr, IntPtrType);
138
139  llvm::Value *Result =
140      CGF.Builder.CreateAtomicRMW(Kind, Args[0], Args[1],
141                                  llvm::SequentiallyConsistent);
142  Result = CGF.Builder.CreateBinOp(Op, Result, Args[1]);
143  Result = EmitFromInt(CGF, Result, T, ValueType);
144  return RValue::get(Result);
145}
146
147/// EmitFAbs - Emit a call to fabs/fabsf/fabsl, depending on the type of ValTy,
148/// which must be a scalar floating point type.
149static Value *EmitFAbs(CodeGenFunction &CGF, Value *V, QualType ValTy) {
150  const BuiltinType *ValTyP = ValTy->getAs<BuiltinType>();
151  assert(ValTyP && "isn't scalar fp type!");
152
153  StringRef FnName;
154  switch (ValTyP->getKind()) {
155  default: llvm_unreachable("Isn't a scalar fp type!");
156  case BuiltinType::Float:      FnName = "fabsf"; break;
157  case BuiltinType::Double:     FnName = "fabs"; break;
158  case BuiltinType::LongDouble: FnName = "fabsl"; break;
159  }
160
161  // The prototype is something that takes and returns whatever V's type is.
162  llvm::FunctionType *FT = llvm::FunctionType::get(V->getType(), V->getType(),
163                                                   false);
164  llvm::Value *Fn = CGF.CGM.CreateRuntimeFunction(FT, FnName);
165
166  return CGF.Builder.CreateCall(Fn, V, "abs");
167}
168
169static RValue emitLibraryCall(CodeGenFunction &CGF, const FunctionDecl *Fn,
170                              const CallExpr *E, llvm::Value *calleeValue) {
171  return CGF.EmitCall(E->getCallee()->getType(), calleeValue,
172                      ReturnValueSlot(), E->arg_begin(), E->arg_end(), Fn);
173}
174
175RValue CodeGenFunction::EmitBuiltinExpr(const FunctionDecl *FD,
176                                        unsigned BuiltinID, const CallExpr *E) {
177  // See if we can constant fold this builtin.  If so, don't emit it at all.
178  Expr::EvalResult Result;
179  if (E->EvaluateAsRValue(Result, CGM.getContext()) &&
180      !Result.hasSideEffects()) {
181    if (Result.Val.isInt())
182      return RValue::get(llvm::ConstantInt::get(getLLVMContext(),
183                                                Result.Val.getInt()));
184    if (Result.Val.isFloat())
185      return RValue::get(llvm::ConstantFP::get(getLLVMContext(),
186                                               Result.Val.getFloat()));
187  }
188
189  switch (BuiltinID) {
190  default: break;  // Handle intrinsics and libm functions below.
191  case Builtin::BI__builtin___CFStringMakeConstantString:
192  case Builtin::BI__builtin___NSStringMakeConstantString:
193    return RValue::get(CGM.EmitConstantExpr(E, E->getType(), 0));
194  case Builtin::BI__builtin_stdarg_start:
195  case Builtin::BI__builtin_va_start:
196  case Builtin::BI__builtin_va_end: {
197    Value *ArgValue = EmitVAListRef(E->getArg(0));
198    llvm::Type *DestType = Int8PtrTy;
199    if (ArgValue->getType() != DestType)
200      ArgValue = Builder.CreateBitCast(ArgValue, DestType,
201                                       ArgValue->getName().data());
202
203    Intrinsic::ID inst = (BuiltinID == Builtin::BI__builtin_va_end) ?
204      Intrinsic::vaend : Intrinsic::vastart;
205    return RValue::get(Builder.CreateCall(CGM.getIntrinsic(inst), ArgValue));
206  }
207  case Builtin::BI__builtin_va_copy: {
208    Value *DstPtr = EmitVAListRef(E->getArg(0));
209    Value *SrcPtr = EmitVAListRef(E->getArg(1));
210
211    llvm::Type *Type = Int8PtrTy;
212
213    DstPtr = Builder.CreateBitCast(DstPtr, Type);
214    SrcPtr = Builder.CreateBitCast(SrcPtr, Type);
215    return RValue::get(Builder.CreateCall2(CGM.getIntrinsic(Intrinsic::vacopy),
216                                           DstPtr, SrcPtr));
217  }
218  case Builtin::BI__builtin_abs: {
219    Value *ArgValue = EmitScalarExpr(E->getArg(0));
220
221    Value *NegOp = Builder.CreateNeg(ArgValue, "neg");
222    Value *CmpResult =
223    Builder.CreateICmpSGE(ArgValue,
224                          llvm::Constant::getNullValue(ArgValue->getType()),
225                                                            "abscond");
226    Value *Result =
227      Builder.CreateSelect(CmpResult, ArgValue, NegOp, "abs");
228
229    return RValue::get(Result);
230  }
231  case Builtin::BI__builtin_ctz:
232  case Builtin::BI__builtin_ctzl:
233  case Builtin::BI__builtin_ctzll: {
234    Value *ArgValue = EmitScalarExpr(E->getArg(0));
235
236    llvm::Type *ArgType = ArgValue->getType();
237    Value *F = CGM.getIntrinsic(Intrinsic::cttz, ArgType);
238
239    llvm::Type *ResultType = ConvertType(E->getType());
240    Value *Result = Builder.CreateCall2(F, ArgValue, Builder.getTrue());
241    if (Result->getType() != ResultType)
242      Result = Builder.CreateIntCast(Result, ResultType, /*isSigned*/true,
243                                     "cast");
244    return RValue::get(Result);
245  }
246  case Builtin::BI__builtin_clz:
247  case Builtin::BI__builtin_clzl:
248  case Builtin::BI__builtin_clzll: {
249    Value *ArgValue = EmitScalarExpr(E->getArg(0));
250
251    llvm::Type *ArgType = ArgValue->getType();
252    Value *F = CGM.getIntrinsic(Intrinsic::ctlz, ArgType);
253
254    llvm::Type *ResultType = ConvertType(E->getType());
255    Value *Result = Builder.CreateCall2(F, ArgValue, Builder.getTrue());
256    if (Result->getType() != ResultType)
257      Result = Builder.CreateIntCast(Result, ResultType, /*isSigned*/true,
258                                     "cast");
259    return RValue::get(Result);
260  }
261  case Builtin::BI__builtin_ffs:
262  case Builtin::BI__builtin_ffsl:
263  case Builtin::BI__builtin_ffsll: {
264    // ffs(x) -> x ? cttz(x) + 1 : 0
265    Value *ArgValue = EmitScalarExpr(E->getArg(0));
266
267    llvm::Type *ArgType = ArgValue->getType();
268    Value *F = CGM.getIntrinsic(Intrinsic::cttz, ArgType);
269
270    llvm::Type *ResultType = ConvertType(E->getType());
271    Value *Tmp = Builder.CreateAdd(Builder.CreateCall2(F, ArgValue,
272                                                       Builder.getTrue()),
273                                   llvm::ConstantInt::get(ArgType, 1));
274    Value *Zero = llvm::Constant::getNullValue(ArgType);
275    Value *IsZero = Builder.CreateICmpEQ(ArgValue, Zero, "iszero");
276    Value *Result = Builder.CreateSelect(IsZero, Zero, Tmp, "ffs");
277    if (Result->getType() != ResultType)
278      Result = Builder.CreateIntCast(Result, ResultType, /*isSigned*/true,
279                                     "cast");
280    return RValue::get(Result);
281  }
282  case Builtin::BI__builtin_parity:
283  case Builtin::BI__builtin_parityl:
284  case Builtin::BI__builtin_parityll: {
285    // parity(x) -> ctpop(x) & 1
286    Value *ArgValue = EmitScalarExpr(E->getArg(0));
287
288    llvm::Type *ArgType = ArgValue->getType();
289    Value *F = CGM.getIntrinsic(Intrinsic::ctpop, ArgType);
290
291    llvm::Type *ResultType = ConvertType(E->getType());
292    Value *Tmp = Builder.CreateCall(F, ArgValue);
293    Value *Result = Builder.CreateAnd(Tmp, llvm::ConstantInt::get(ArgType, 1));
294    if (Result->getType() != ResultType)
295      Result = Builder.CreateIntCast(Result, ResultType, /*isSigned*/true,
296                                     "cast");
297    return RValue::get(Result);
298  }
299  case Builtin::BI__builtin_popcount:
300  case Builtin::BI__builtin_popcountl:
301  case Builtin::BI__builtin_popcountll: {
302    Value *ArgValue = EmitScalarExpr(E->getArg(0));
303
304    llvm::Type *ArgType = ArgValue->getType();
305    Value *F = CGM.getIntrinsic(Intrinsic::ctpop, ArgType);
306
307    llvm::Type *ResultType = ConvertType(E->getType());
308    Value *Result = Builder.CreateCall(F, ArgValue);
309    if (Result->getType() != ResultType)
310      Result = Builder.CreateIntCast(Result, ResultType, /*isSigned*/true,
311                                     "cast");
312    return RValue::get(Result);
313  }
314  case Builtin::BI__builtin_expect: {
315    Value *ArgValue = EmitScalarExpr(E->getArg(0));
316    llvm::Type *ArgType = ArgValue->getType();
317
318    Value *FnExpect = CGM.getIntrinsic(Intrinsic::expect, ArgType);
319    Value *ExpectedValue = EmitScalarExpr(E->getArg(1));
320
321    Value *Result = Builder.CreateCall2(FnExpect, ArgValue, ExpectedValue,
322                                        "expval");
323    return RValue::get(Result);
324  }
325  case Builtin::BI__builtin_bswap32:
326  case Builtin::BI__builtin_bswap64: {
327    Value *ArgValue = EmitScalarExpr(E->getArg(0));
328    llvm::Type *ArgType = ArgValue->getType();
329    Value *F = CGM.getIntrinsic(Intrinsic::bswap, ArgType);
330    return RValue::get(Builder.CreateCall(F, ArgValue));
331  }
332  case Builtin::BI__builtin_object_size: {
333    // We pass this builtin onto the optimizer so that it can
334    // figure out the object size in more complex cases.
335    llvm::Type *ResType = ConvertType(E->getType());
336
337    // LLVM only supports 0 and 2, make sure that we pass along that
338    // as a boolean.
339    Value *Ty = EmitScalarExpr(E->getArg(1));
340    ConstantInt *CI = dyn_cast<ConstantInt>(Ty);
341    assert(CI);
342    uint64_t val = CI->getZExtValue();
343    CI = ConstantInt::get(Builder.getInt1Ty(), (val & 0x2) >> 1);
344
345    Value *F = CGM.getIntrinsic(Intrinsic::objectsize, ResType);
346    return RValue::get(Builder.CreateCall2(F,
347                                           EmitScalarExpr(E->getArg(0)),
348                                           CI));
349  }
350  case Builtin::BI__builtin_prefetch: {
351    Value *Locality, *RW, *Address = EmitScalarExpr(E->getArg(0));
352    // FIXME: Technically these constants should of type 'int', yes?
353    RW = (E->getNumArgs() > 1) ? EmitScalarExpr(E->getArg(1)) :
354      llvm::ConstantInt::get(Int32Ty, 0);
355    Locality = (E->getNumArgs() > 2) ? EmitScalarExpr(E->getArg(2)) :
356      llvm::ConstantInt::get(Int32Ty, 3);
357    Value *Data = llvm::ConstantInt::get(Int32Ty, 1);
358    Value *F = CGM.getIntrinsic(Intrinsic::prefetch);
359    return RValue::get(Builder.CreateCall4(F, Address, RW, Locality, Data));
360  }
361  case Builtin::BI__builtin_trap: {
362    Value *F = CGM.getIntrinsic(Intrinsic::trap);
363    return RValue::get(Builder.CreateCall(F));
364  }
365  case Builtin::BI__builtin_unreachable: {
366    if (CatchUndefined)
367      EmitBranch(getTrapBB());
368    else
369      Builder.CreateUnreachable();
370
371    // We do need to preserve an insertion point.
372    EmitBlock(createBasicBlock("unreachable.cont"));
373
374    return RValue::get(0);
375  }
376
377  case Builtin::BI__builtin_powi:
378  case Builtin::BI__builtin_powif:
379  case Builtin::BI__builtin_powil: {
380    Value *Base = EmitScalarExpr(E->getArg(0));
381    Value *Exponent = EmitScalarExpr(E->getArg(1));
382    llvm::Type *ArgType = Base->getType();
383    Value *F = CGM.getIntrinsic(Intrinsic::powi, ArgType);
384    return RValue::get(Builder.CreateCall2(F, Base, Exponent));
385  }
386
387  case Builtin::BI__builtin_isgreater:
388  case Builtin::BI__builtin_isgreaterequal:
389  case Builtin::BI__builtin_isless:
390  case Builtin::BI__builtin_islessequal:
391  case Builtin::BI__builtin_islessgreater:
392  case Builtin::BI__builtin_isunordered: {
393    // Ordered comparisons: we know the arguments to these are matching scalar
394    // floating point values.
395    Value *LHS = EmitScalarExpr(E->getArg(0));
396    Value *RHS = EmitScalarExpr(E->getArg(1));
397
398    switch (BuiltinID) {
399    default: llvm_unreachable("Unknown ordered comparison");
400    case Builtin::BI__builtin_isgreater:
401      LHS = Builder.CreateFCmpOGT(LHS, RHS, "cmp");
402      break;
403    case Builtin::BI__builtin_isgreaterequal:
404      LHS = Builder.CreateFCmpOGE(LHS, RHS, "cmp");
405      break;
406    case Builtin::BI__builtin_isless:
407      LHS = Builder.CreateFCmpOLT(LHS, RHS, "cmp");
408      break;
409    case Builtin::BI__builtin_islessequal:
410      LHS = Builder.CreateFCmpOLE(LHS, RHS, "cmp");
411      break;
412    case Builtin::BI__builtin_islessgreater:
413      LHS = Builder.CreateFCmpONE(LHS, RHS, "cmp");
414      break;
415    case Builtin::BI__builtin_isunordered:
416      LHS = Builder.CreateFCmpUNO(LHS, RHS, "cmp");
417      break;
418    }
419    // ZExt bool to int type.
420    return RValue::get(Builder.CreateZExt(LHS, ConvertType(E->getType())));
421  }
422  case Builtin::BI__builtin_isnan: {
423    Value *V = EmitScalarExpr(E->getArg(0));
424    V = Builder.CreateFCmpUNO(V, V, "cmp");
425    return RValue::get(Builder.CreateZExt(V, ConvertType(E->getType())));
426  }
427
428  case Builtin::BI__builtin_isinf: {
429    // isinf(x) --> fabs(x) == infinity
430    Value *V = EmitScalarExpr(E->getArg(0));
431    V = EmitFAbs(*this, V, E->getArg(0)->getType());
432
433    V = Builder.CreateFCmpOEQ(V, ConstantFP::getInfinity(V->getType()),"isinf");
434    return RValue::get(Builder.CreateZExt(V, ConvertType(E->getType())));
435  }
436
437  // TODO: BI__builtin_isinf_sign
438  //   isinf_sign(x) -> isinf(x) ? (signbit(x) ? -1 : 1) : 0
439
440  case Builtin::BI__builtin_isnormal: {
441    // isnormal(x) --> x == x && fabsf(x) < infinity && fabsf(x) >= float_min
442    Value *V = EmitScalarExpr(E->getArg(0));
443    Value *Eq = Builder.CreateFCmpOEQ(V, V, "iseq");
444
445    Value *Abs = EmitFAbs(*this, V, E->getArg(0)->getType());
446    Value *IsLessThanInf =
447      Builder.CreateFCmpULT(Abs, ConstantFP::getInfinity(V->getType()),"isinf");
448    APFloat Smallest = APFloat::getSmallestNormalized(
449                   getContext().getFloatTypeSemantics(E->getArg(0)->getType()));
450    Value *IsNormal =
451      Builder.CreateFCmpUGE(Abs, ConstantFP::get(V->getContext(), Smallest),
452                            "isnormal");
453    V = Builder.CreateAnd(Eq, IsLessThanInf, "and");
454    V = Builder.CreateAnd(V, IsNormal, "and");
455    return RValue::get(Builder.CreateZExt(V, ConvertType(E->getType())));
456  }
457
458  case Builtin::BI__builtin_isfinite: {
459    // isfinite(x) --> x == x && fabs(x) != infinity;
460    Value *V = EmitScalarExpr(E->getArg(0));
461    Value *Eq = Builder.CreateFCmpOEQ(V, V, "iseq");
462
463    Value *Abs = EmitFAbs(*this, V, E->getArg(0)->getType());
464    Value *IsNotInf =
465      Builder.CreateFCmpUNE(Abs, ConstantFP::getInfinity(V->getType()),"isinf");
466
467    V = Builder.CreateAnd(Eq, IsNotInf, "and");
468    return RValue::get(Builder.CreateZExt(V, ConvertType(E->getType())));
469  }
470
471  case Builtin::BI__builtin_fpclassify: {
472    Value *V = EmitScalarExpr(E->getArg(5));
473    llvm::Type *Ty = ConvertType(E->getArg(5)->getType());
474
475    // Create Result
476    BasicBlock *Begin = Builder.GetInsertBlock();
477    BasicBlock *End = createBasicBlock("fpclassify_end", this->CurFn);
478    Builder.SetInsertPoint(End);
479    PHINode *Result =
480      Builder.CreatePHI(ConvertType(E->getArg(0)->getType()), 4,
481                        "fpclassify_result");
482
483    // if (V==0) return FP_ZERO
484    Builder.SetInsertPoint(Begin);
485    Value *IsZero = Builder.CreateFCmpOEQ(V, Constant::getNullValue(Ty),
486                                          "iszero");
487    Value *ZeroLiteral = EmitScalarExpr(E->getArg(4));
488    BasicBlock *NotZero = createBasicBlock("fpclassify_not_zero", this->CurFn);
489    Builder.CreateCondBr(IsZero, End, NotZero);
490    Result->addIncoming(ZeroLiteral, Begin);
491
492    // if (V != V) return FP_NAN
493    Builder.SetInsertPoint(NotZero);
494    Value *IsNan = Builder.CreateFCmpUNO(V, V, "cmp");
495    Value *NanLiteral = EmitScalarExpr(E->getArg(0));
496    BasicBlock *NotNan = createBasicBlock("fpclassify_not_nan", this->CurFn);
497    Builder.CreateCondBr(IsNan, End, NotNan);
498    Result->addIncoming(NanLiteral, NotZero);
499
500    // if (fabs(V) == infinity) return FP_INFINITY
501    Builder.SetInsertPoint(NotNan);
502    Value *VAbs = EmitFAbs(*this, V, E->getArg(5)->getType());
503    Value *IsInf =
504      Builder.CreateFCmpOEQ(VAbs, ConstantFP::getInfinity(V->getType()),
505                            "isinf");
506    Value *InfLiteral = EmitScalarExpr(E->getArg(1));
507    BasicBlock *NotInf = createBasicBlock("fpclassify_not_inf", this->CurFn);
508    Builder.CreateCondBr(IsInf, End, NotInf);
509    Result->addIncoming(InfLiteral, NotNan);
510
511    // if (fabs(V) >= MIN_NORMAL) return FP_NORMAL else FP_SUBNORMAL
512    Builder.SetInsertPoint(NotInf);
513    APFloat Smallest = APFloat::getSmallestNormalized(
514        getContext().getFloatTypeSemantics(E->getArg(5)->getType()));
515    Value *IsNormal =
516      Builder.CreateFCmpUGE(VAbs, ConstantFP::get(V->getContext(), Smallest),
517                            "isnormal");
518    Value *NormalResult =
519      Builder.CreateSelect(IsNormal, EmitScalarExpr(E->getArg(2)),
520                           EmitScalarExpr(E->getArg(3)));
521    Builder.CreateBr(End);
522    Result->addIncoming(NormalResult, NotInf);
523
524    // return Result
525    Builder.SetInsertPoint(End);
526    return RValue::get(Result);
527  }
528
529  case Builtin::BIalloca:
530  case Builtin::BI__builtin_alloca: {
531    Value *Size = EmitScalarExpr(E->getArg(0));
532    return RValue::get(Builder.CreateAlloca(Builder.getInt8Ty(), Size));
533  }
534  case Builtin::BIbzero:
535  case Builtin::BI__builtin_bzero: {
536    Value *Address = EmitScalarExpr(E->getArg(0));
537    Value *SizeVal = EmitScalarExpr(E->getArg(1));
538    Builder.CreateMemSet(Address, Builder.getInt8(0), SizeVal, 1, false);
539    return RValue::get(Address);
540  }
541  case Builtin::BImemcpy:
542  case Builtin::BI__builtin_memcpy: {
543    Value *Address = EmitScalarExpr(E->getArg(0));
544    Value *SrcAddr = EmitScalarExpr(E->getArg(1));
545    Value *SizeVal = EmitScalarExpr(E->getArg(2));
546    Builder.CreateMemCpy(Address, SrcAddr, SizeVal, 1, false);
547    return RValue::get(Address);
548  }
549
550  case Builtin::BI__builtin___memcpy_chk: {
551    // fold __builtin_memcpy_chk(x, y, cst1, cst2) to memset iff cst1<=cst2.
552    llvm::APSInt Size, DstSize;
553    if (!E->getArg(2)->EvaluateAsInt(Size, CGM.getContext()) ||
554        !E->getArg(3)->EvaluateAsInt(DstSize, CGM.getContext()))
555      break;
556    if (Size.ugt(DstSize))
557      break;
558    Value *Dest = EmitScalarExpr(E->getArg(0));
559    Value *Src = EmitScalarExpr(E->getArg(1));
560    Value *SizeVal = llvm::ConstantInt::get(Builder.getContext(), Size);
561    Builder.CreateMemCpy(Dest, Src, SizeVal, 1, false);
562    return RValue::get(Dest);
563  }
564
565  case Builtin::BI__builtin_objc_memmove_collectable: {
566    Value *Address = EmitScalarExpr(E->getArg(0));
567    Value *SrcAddr = EmitScalarExpr(E->getArg(1));
568    Value *SizeVal = EmitScalarExpr(E->getArg(2));
569    CGM.getObjCRuntime().EmitGCMemmoveCollectable(*this,
570                                                  Address, SrcAddr, SizeVal);
571    return RValue::get(Address);
572  }
573
574  case Builtin::BI__builtin___memmove_chk: {
575    // fold __builtin_memmove_chk(x, y, cst1, cst2) to memset iff cst1<=cst2.
576    llvm::APSInt Size, DstSize;
577    if (!E->getArg(2)->EvaluateAsInt(Size, CGM.getContext()) ||
578        !E->getArg(3)->EvaluateAsInt(DstSize, CGM.getContext()))
579      break;
580    if (Size.ugt(DstSize))
581      break;
582    Value *Dest = EmitScalarExpr(E->getArg(0));
583    Value *Src = EmitScalarExpr(E->getArg(1));
584    Value *SizeVal = llvm::ConstantInt::get(Builder.getContext(), Size);
585    Builder.CreateMemMove(Dest, Src, SizeVal, 1, false);
586    return RValue::get(Dest);
587  }
588
589  case Builtin::BImemmove:
590  case Builtin::BI__builtin_memmove: {
591    Value *Address = EmitScalarExpr(E->getArg(0));
592    Value *SrcAddr = EmitScalarExpr(E->getArg(1));
593    Value *SizeVal = EmitScalarExpr(E->getArg(2));
594    Builder.CreateMemMove(Address, SrcAddr, SizeVal, 1, false);
595    return RValue::get(Address);
596  }
597  case Builtin::BImemset:
598  case Builtin::BI__builtin_memset: {
599    Value *Address = EmitScalarExpr(E->getArg(0));
600    Value *ByteVal = Builder.CreateTrunc(EmitScalarExpr(E->getArg(1)),
601                                         Builder.getInt8Ty());
602    Value *SizeVal = EmitScalarExpr(E->getArg(2));
603    Builder.CreateMemSet(Address, ByteVal, SizeVal, 1, false);
604    return RValue::get(Address);
605  }
606  case Builtin::BI__builtin___memset_chk: {
607    // fold __builtin_memset_chk(x, y, cst1, cst2) to memset iff cst1<=cst2.
608    llvm::APSInt Size, DstSize;
609    if (!E->getArg(2)->EvaluateAsInt(Size, CGM.getContext()) ||
610        !E->getArg(3)->EvaluateAsInt(DstSize, CGM.getContext()))
611      break;
612    if (Size.ugt(DstSize))
613      break;
614    Value *Address = EmitScalarExpr(E->getArg(0));
615    Value *ByteVal = Builder.CreateTrunc(EmitScalarExpr(E->getArg(1)),
616                                         Builder.getInt8Ty());
617    Value *SizeVal = llvm::ConstantInt::get(Builder.getContext(), Size);
618    Builder.CreateMemSet(Address, ByteVal, SizeVal, 1, false);
619
620    return RValue::get(Address);
621  }
622  case Builtin::BI__builtin_dwarf_cfa: {
623    // The offset in bytes from the first argument to the CFA.
624    //
625    // Why on earth is this in the frontend?  Is there any reason at
626    // all that the backend can't reasonably determine this while
627    // lowering llvm.eh.dwarf.cfa()?
628    //
629    // TODO: If there's a satisfactory reason, add a target hook for
630    // this instead of hard-coding 0, which is correct for most targets.
631    int32_t Offset = 0;
632
633    Value *F = CGM.getIntrinsic(Intrinsic::eh_dwarf_cfa);
634    return RValue::get(Builder.CreateCall(F,
635                                      llvm::ConstantInt::get(Int32Ty, Offset)));
636  }
637  case Builtin::BI__builtin_return_address: {
638    Value *Depth = EmitScalarExpr(E->getArg(0));
639    Depth = Builder.CreateIntCast(Depth, Int32Ty, false);
640    Value *F = CGM.getIntrinsic(Intrinsic::returnaddress);
641    return RValue::get(Builder.CreateCall(F, Depth));
642  }
643  case Builtin::BI__builtin_frame_address: {
644    Value *Depth = EmitScalarExpr(E->getArg(0));
645    Depth = Builder.CreateIntCast(Depth, Int32Ty, false);
646    Value *F = CGM.getIntrinsic(Intrinsic::frameaddress);
647    return RValue::get(Builder.CreateCall(F, Depth));
648  }
649  case Builtin::BI__builtin_extract_return_addr: {
650    Value *Address = EmitScalarExpr(E->getArg(0));
651    Value *Result = getTargetHooks().decodeReturnAddress(*this, Address);
652    return RValue::get(Result);
653  }
654  case Builtin::BI__builtin_frob_return_addr: {
655    Value *Address = EmitScalarExpr(E->getArg(0));
656    Value *Result = getTargetHooks().encodeReturnAddress(*this, Address);
657    return RValue::get(Result);
658  }
659  case Builtin::BI__builtin_dwarf_sp_column: {
660    llvm::IntegerType *Ty
661      = cast<llvm::IntegerType>(ConvertType(E->getType()));
662    int Column = getTargetHooks().getDwarfEHStackPointer(CGM);
663    if (Column == -1) {
664      CGM.ErrorUnsupported(E, "__builtin_dwarf_sp_column");
665      return RValue::get(llvm::UndefValue::get(Ty));
666    }
667    return RValue::get(llvm::ConstantInt::get(Ty, Column, true));
668  }
669  case Builtin::BI__builtin_init_dwarf_reg_size_table: {
670    Value *Address = EmitScalarExpr(E->getArg(0));
671    if (getTargetHooks().initDwarfEHRegSizeTable(*this, Address))
672      CGM.ErrorUnsupported(E, "__builtin_init_dwarf_reg_size_table");
673    return RValue::get(llvm::UndefValue::get(ConvertType(E->getType())));
674  }
675  case Builtin::BI__builtin_eh_return: {
676    Value *Int = EmitScalarExpr(E->getArg(0));
677    Value *Ptr = EmitScalarExpr(E->getArg(1));
678
679    llvm::IntegerType *IntTy = cast<llvm::IntegerType>(Int->getType());
680    assert((IntTy->getBitWidth() == 32 || IntTy->getBitWidth() == 64) &&
681           "LLVM's __builtin_eh_return only supports 32- and 64-bit variants");
682    Value *F = CGM.getIntrinsic(IntTy->getBitWidth() == 32
683                                  ? Intrinsic::eh_return_i32
684                                  : Intrinsic::eh_return_i64);
685    Builder.CreateCall2(F, Int, Ptr);
686    Builder.CreateUnreachable();
687
688    // We do need to preserve an insertion point.
689    EmitBlock(createBasicBlock("builtin_eh_return.cont"));
690
691    return RValue::get(0);
692  }
693  case Builtin::BI__builtin_unwind_init: {
694    Value *F = CGM.getIntrinsic(Intrinsic::eh_unwind_init);
695    return RValue::get(Builder.CreateCall(F));
696  }
697  case Builtin::BI__builtin_extend_pointer: {
698    // Extends a pointer to the size of an _Unwind_Word, which is
699    // uint64_t on all platforms.  Generally this gets poked into a
700    // register and eventually used as an address, so if the
701    // addressing registers are wider than pointers and the platform
702    // doesn't implicitly ignore high-order bits when doing
703    // addressing, we need to make sure we zext / sext based on
704    // the platform's expectations.
705    //
706    // See: http://gcc.gnu.org/ml/gcc-bugs/2002-02/msg00237.html
707
708    // Cast the pointer to intptr_t.
709    Value *Ptr = EmitScalarExpr(E->getArg(0));
710    Value *Result = Builder.CreatePtrToInt(Ptr, IntPtrTy, "extend.cast");
711
712    // If that's 64 bits, we're done.
713    if (IntPtrTy->getBitWidth() == 64)
714      return RValue::get(Result);
715
716    // Otherwise, ask the codegen data what to do.
717    if (getTargetHooks().extendPointerWithSExt())
718      return RValue::get(Builder.CreateSExt(Result, Int64Ty, "extend.sext"));
719    else
720      return RValue::get(Builder.CreateZExt(Result, Int64Ty, "extend.zext"));
721  }
722  case Builtin::BI__builtin_setjmp: {
723    // Buffer is a void**.
724    Value *Buf = EmitScalarExpr(E->getArg(0));
725
726    // Store the frame pointer to the setjmp buffer.
727    Value *FrameAddr =
728      Builder.CreateCall(CGM.getIntrinsic(Intrinsic::frameaddress),
729                         ConstantInt::get(Int32Ty, 0));
730    Builder.CreateStore(FrameAddr, Buf);
731
732    // Store the stack pointer to the setjmp buffer.
733    Value *StackAddr =
734      Builder.CreateCall(CGM.getIntrinsic(Intrinsic::stacksave));
735    Value *StackSaveSlot =
736      Builder.CreateGEP(Buf, ConstantInt::get(Int32Ty, 2));
737    Builder.CreateStore(StackAddr, StackSaveSlot);
738
739    // Call LLVM's EH setjmp, which is lightweight.
740    Value *F = CGM.getIntrinsic(Intrinsic::eh_sjlj_setjmp);
741    Buf = Builder.CreateBitCast(Buf, Int8PtrTy);
742    return RValue::get(Builder.CreateCall(F, Buf));
743  }
744  case Builtin::BI__builtin_longjmp: {
745    Value *Buf = EmitScalarExpr(E->getArg(0));
746    Buf = Builder.CreateBitCast(Buf, Int8PtrTy);
747
748    // Call LLVM's EH longjmp, which is lightweight.
749    Builder.CreateCall(CGM.getIntrinsic(Intrinsic::eh_sjlj_longjmp), Buf);
750
751    // longjmp doesn't return; mark this as unreachable.
752    Builder.CreateUnreachable();
753
754    // We do need to preserve an insertion point.
755    EmitBlock(createBasicBlock("longjmp.cont"));
756
757    return RValue::get(0);
758  }
759  case Builtin::BI__sync_fetch_and_add:
760  case Builtin::BI__sync_fetch_and_sub:
761  case Builtin::BI__sync_fetch_and_or:
762  case Builtin::BI__sync_fetch_and_and:
763  case Builtin::BI__sync_fetch_and_xor:
764  case Builtin::BI__sync_add_and_fetch:
765  case Builtin::BI__sync_sub_and_fetch:
766  case Builtin::BI__sync_and_and_fetch:
767  case Builtin::BI__sync_or_and_fetch:
768  case Builtin::BI__sync_xor_and_fetch:
769  case Builtin::BI__sync_val_compare_and_swap:
770  case Builtin::BI__sync_bool_compare_and_swap:
771  case Builtin::BI__sync_lock_test_and_set:
772  case Builtin::BI__sync_lock_release:
773  case Builtin::BI__sync_swap:
774    llvm_unreachable("Shouldn't make it through sema");
775  case Builtin::BI__sync_fetch_and_add_1:
776  case Builtin::BI__sync_fetch_and_add_2:
777  case Builtin::BI__sync_fetch_and_add_4:
778  case Builtin::BI__sync_fetch_and_add_8:
779  case Builtin::BI__sync_fetch_and_add_16:
780    return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::Add, E);
781  case Builtin::BI__sync_fetch_and_sub_1:
782  case Builtin::BI__sync_fetch_and_sub_2:
783  case Builtin::BI__sync_fetch_and_sub_4:
784  case Builtin::BI__sync_fetch_and_sub_8:
785  case Builtin::BI__sync_fetch_and_sub_16:
786    return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::Sub, E);
787  case Builtin::BI__sync_fetch_and_or_1:
788  case Builtin::BI__sync_fetch_and_or_2:
789  case Builtin::BI__sync_fetch_and_or_4:
790  case Builtin::BI__sync_fetch_and_or_8:
791  case Builtin::BI__sync_fetch_and_or_16:
792    return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::Or, E);
793  case Builtin::BI__sync_fetch_and_and_1:
794  case Builtin::BI__sync_fetch_and_and_2:
795  case Builtin::BI__sync_fetch_and_and_4:
796  case Builtin::BI__sync_fetch_and_and_8:
797  case Builtin::BI__sync_fetch_and_and_16:
798    return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::And, E);
799  case Builtin::BI__sync_fetch_and_xor_1:
800  case Builtin::BI__sync_fetch_and_xor_2:
801  case Builtin::BI__sync_fetch_and_xor_4:
802  case Builtin::BI__sync_fetch_and_xor_8:
803  case Builtin::BI__sync_fetch_and_xor_16:
804    return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::Xor, E);
805
806  // Clang extensions: not overloaded yet.
807  case Builtin::BI__sync_fetch_and_min:
808    return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::Min, E);
809  case Builtin::BI__sync_fetch_and_max:
810    return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::Max, E);
811  case Builtin::BI__sync_fetch_and_umin:
812    return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::UMin, E);
813  case Builtin::BI__sync_fetch_and_umax:
814    return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::UMax, E);
815
816  case Builtin::BI__sync_add_and_fetch_1:
817  case Builtin::BI__sync_add_and_fetch_2:
818  case Builtin::BI__sync_add_and_fetch_4:
819  case Builtin::BI__sync_add_and_fetch_8:
820  case Builtin::BI__sync_add_and_fetch_16:
821    return EmitBinaryAtomicPost(*this, llvm::AtomicRMWInst::Add, E,
822                                llvm::Instruction::Add);
823  case Builtin::BI__sync_sub_and_fetch_1:
824  case Builtin::BI__sync_sub_and_fetch_2:
825  case Builtin::BI__sync_sub_and_fetch_4:
826  case Builtin::BI__sync_sub_and_fetch_8:
827  case Builtin::BI__sync_sub_and_fetch_16:
828    return EmitBinaryAtomicPost(*this, llvm::AtomicRMWInst::Sub, E,
829                                llvm::Instruction::Sub);
830  case Builtin::BI__sync_and_and_fetch_1:
831  case Builtin::BI__sync_and_and_fetch_2:
832  case Builtin::BI__sync_and_and_fetch_4:
833  case Builtin::BI__sync_and_and_fetch_8:
834  case Builtin::BI__sync_and_and_fetch_16:
835    return EmitBinaryAtomicPost(*this, llvm::AtomicRMWInst::And, E,
836                                llvm::Instruction::And);
837  case Builtin::BI__sync_or_and_fetch_1:
838  case Builtin::BI__sync_or_and_fetch_2:
839  case Builtin::BI__sync_or_and_fetch_4:
840  case Builtin::BI__sync_or_and_fetch_8:
841  case Builtin::BI__sync_or_and_fetch_16:
842    return EmitBinaryAtomicPost(*this, llvm::AtomicRMWInst::Or, E,
843                                llvm::Instruction::Or);
844  case Builtin::BI__sync_xor_and_fetch_1:
845  case Builtin::BI__sync_xor_and_fetch_2:
846  case Builtin::BI__sync_xor_and_fetch_4:
847  case Builtin::BI__sync_xor_and_fetch_8:
848  case Builtin::BI__sync_xor_and_fetch_16:
849    return EmitBinaryAtomicPost(*this, llvm::AtomicRMWInst::Xor, E,
850                                llvm::Instruction::Xor);
851
852  case Builtin::BI__sync_val_compare_and_swap_1:
853  case Builtin::BI__sync_val_compare_and_swap_2:
854  case Builtin::BI__sync_val_compare_and_swap_4:
855  case Builtin::BI__sync_val_compare_and_swap_8:
856  case Builtin::BI__sync_val_compare_and_swap_16: {
857    QualType T = E->getType();
858    llvm::Value *DestPtr = EmitScalarExpr(E->getArg(0));
859    unsigned AddrSpace =
860      cast<llvm::PointerType>(DestPtr->getType())->getAddressSpace();
861
862    llvm::IntegerType *IntType =
863      llvm::IntegerType::get(getLLVMContext(),
864                             getContext().getTypeSize(T));
865    llvm::Type *IntPtrType = IntType->getPointerTo(AddrSpace);
866
867    Value *Args[3];
868    Args[0] = Builder.CreateBitCast(DestPtr, IntPtrType);
869    Args[1] = EmitScalarExpr(E->getArg(1));
870    llvm::Type *ValueType = Args[1]->getType();
871    Args[1] = EmitToInt(*this, Args[1], T, IntType);
872    Args[2] = EmitToInt(*this, EmitScalarExpr(E->getArg(2)), T, IntType);
873
874    Value *Result = Builder.CreateAtomicCmpXchg(Args[0], Args[1], Args[2],
875                                                llvm::SequentiallyConsistent);
876    Result = EmitFromInt(*this, Result, T, ValueType);
877    return RValue::get(Result);
878  }
879
880  case Builtin::BI__sync_bool_compare_and_swap_1:
881  case Builtin::BI__sync_bool_compare_and_swap_2:
882  case Builtin::BI__sync_bool_compare_and_swap_4:
883  case Builtin::BI__sync_bool_compare_and_swap_8:
884  case Builtin::BI__sync_bool_compare_and_swap_16: {
885    QualType T = E->getArg(1)->getType();
886    llvm::Value *DestPtr = EmitScalarExpr(E->getArg(0));
887    unsigned AddrSpace =
888      cast<llvm::PointerType>(DestPtr->getType())->getAddressSpace();
889
890    llvm::IntegerType *IntType =
891      llvm::IntegerType::get(getLLVMContext(),
892                             getContext().getTypeSize(T));
893    llvm::Type *IntPtrType = IntType->getPointerTo(AddrSpace);
894
895    Value *Args[3];
896    Args[0] = Builder.CreateBitCast(DestPtr, IntPtrType);
897    Args[1] = EmitToInt(*this, EmitScalarExpr(E->getArg(1)), T, IntType);
898    Args[2] = EmitToInt(*this, EmitScalarExpr(E->getArg(2)), T, IntType);
899
900    Value *OldVal = Args[1];
901    Value *PrevVal = Builder.CreateAtomicCmpXchg(Args[0], Args[1], Args[2],
902                                                 llvm::SequentiallyConsistent);
903    Value *Result = Builder.CreateICmpEQ(PrevVal, OldVal);
904    // zext bool to int.
905    Result = Builder.CreateZExt(Result, ConvertType(E->getType()));
906    return RValue::get(Result);
907  }
908
909  case Builtin::BI__sync_swap_1:
910  case Builtin::BI__sync_swap_2:
911  case Builtin::BI__sync_swap_4:
912  case Builtin::BI__sync_swap_8:
913  case Builtin::BI__sync_swap_16:
914    return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::Xchg, E);
915
916  case Builtin::BI__sync_lock_test_and_set_1:
917  case Builtin::BI__sync_lock_test_and_set_2:
918  case Builtin::BI__sync_lock_test_and_set_4:
919  case Builtin::BI__sync_lock_test_and_set_8:
920  case Builtin::BI__sync_lock_test_and_set_16:
921    return EmitBinaryAtomic(*this, llvm::AtomicRMWInst::Xchg, E);
922
923  case Builtin::BI__sync_lock_release_1:
924  case Builtin::BI__sync_lock_release_2:
925  case Builtin::BI__sync_lock_release_4:
926  case Builtin::BI__sync_lock_release_8:
927  case Builtin::BI__sync_lock_release_16: {
928    Value *Ptr = EmitScalarExpr(E->getArg(0));
929    llvm::Type *ElLLVMTy =
930      cast<llvm::PointerType>(Ptr->getType())->getElementType();
931    llvm::StoreInst *Store =
932      Builder.CreateStore(llvm::Constant::getNullValue(ElLLVMTy), Ptr);
933    QualType ElTy = E->getArg(0)->getType()->getPointeeType();
934    CharUnits StoreSize = getContext().getTypeSizeInChars(ElTy);
935    Store->setAlignment(StoreSize.getQuantity());
936    Store->setAtomic(llvm::Release);
937    return RValue::get(0);
938  }
939
940  case Builtin::BI__sync_synchronize: {
941    // We assume this is supposed to correspond to a C++0x-style
942    // sequentially-consistent fence (i.e. this is only usable for
943    // synchonization, not device I/O or anything like that). This intrinsic
944    // is really badly designed in the sense that in theory, there isn't
945    // any way to safely use it... but in practice, it mostly works
946    // to use it with non-atomic loads and stores to get acquire/release
947    // semantics.
948    Builder.CreateFence(llvm::SequentiallyConsistent);
949    return RValue::get(0);
950  }
951
952  case Builtin::BI__atomic_thread_fence:
953  case Builtin::BI__atomic_signal_fence: {
954    llvm::SynchronizationScope Scope;
955    if (BuiltinID == Builtin::BI__atomic_signal_fence)
956      Scope = llvm::SingleThread;
957    else
958      Scope = llvm::CrossThread;
959    Value *Order = EmitScalarExpr(E->getArg(0));
960    if (isa<llvm::ConstantInt>(Order)) {
961      int ord = cast<llvm::ConstantInt>(Order)->getZExtValue();
962      switch (ord) {
963      case 0:  // memory_order_relaxed
964      default: // invalid order
965        break;
966      case 1:  // memory_order_consume
967      case 2:  // memory_order_acquire
968        Builder.CreateFence(llvm::Acquire, Scope);
969        break;
970      case 3:  // memory_order_release
971        Builder.CreateFence(llvm::Release, Scope);
972        break;
973      case 4:  // memory_order_acq_rel
974        Builder.CreateFence(llvm::AcquireRelease, Scope);
975        break;
976      case 5:  // memory_order_seq_cst
977        Builder.CreateFence(llvm::SequentiallyConsistent, Scope);
978        break;
979      }
980      return RValue::get(0);
981    }
982
983    llvm::BasicBlock *AcquireBB, *ReleaseBB, *AcqRelBB, *SeqCstBB;
984    AcquireBB = createBasicBlock("acquire", CurFn);
985    ReleaseBB = createBasicBlock("release", CurFn);
986    AcqRelBB = createBasicBlock("acqrel", CurFn);
987    SeqCstBB = createBasicBlock("seqcst", CurFn);
988    llvm::BasicBlock *ContBB = createBasicBlock("atomic.continue", CurFn);
989
990    Order = Builder.CreateIntCast(Order, Builder.getInt32Ty(), false);
991    llvm::SwitchInst *SI = Builder.CreateSwitch(Order, ContBB);
992
993    Builder.SetInsertPoint(AcquireBB);
994    Builder.CreateFence(llvm::Acquire, Scope);
995    Builder.CreateBr(ContBB);
996    SI->addCase(Builder.getInt32(1), AcquireBB);
997    SI->addCase(Builder.getInt32(2), AcquireBB);
998
999    Builder.SetInsertPoint(ReleaseBB);
1000    Builder.CreateFence(llvm::Release, Scope);
1001    Builder.CreateBr(ContBB);
1002    SI->addCase(Builder.getInt32(3), ReleaseBB);
1003
1004    Builder.SetInsertPoint(AcqRelBB);
1005    Builder.CreateFence(llvm::AcquireRelease, Scope);
1006    Builder.CreateBr(ContBB);
1007    SI->addCase(Builder.getInt32(4), AcqRelBB);
1008
1009    Builder.SetInsertPoint(SeqCstBB);
1010    Builder.CreateFence(llvm::SequentiallyConsistent, Scope);
1011    Builder.CreateBr(ContBB);
1012    SI->addCase(Builder.getInt32(5), SeqCstBB);
1013
1014    Builder.SetInsertPoint(ContBB);
1015    return RValue::get(0);
1016  }
1017
1018    // Library functions with special handling.
1019  case Builtin::BIsqrt:
1020  case Builtin::BIsqrtf:
1021  case Builtin::BIsqrtl: {
1022    // TODO: there is currently no set of optimizer flags
1023    // sufficient for us to rewrite sqrt to @llvm.sqrt.
1024    // -fmath-errno=0 is not good enough; we need finiteness.
1025    // We could probably precondition the call with an ult
1026    // against 0, but is that worth the complexity?
1027    break;
1028  }
1029
1030  case Builtin::BIpow:
1031  case Builtin::BIpowf:
1032  case Builtin::BIpowl: {
1033    // Rewrite sqrt to intrinsic if allowed.
1034    if (!FD->hasAttr<ConstAttr>())
1035      break;
1036    Value *Base = EmitScalarExpr(E->getArg(0));
1037    Value *Exponent = EmitScalarExpr(E->getArg(1));
1038    llvm::Type *ArgType = Base->getType();
1039    Value *F = CGM.getIntrinsic(Intrinsic::pow, ArgType);
1040    return RValue::get(Builder.CreateCall2(F, Base, Exponent));
1041  }
1042
1043  case Builtin::BIfma:
1044  case Builtin::BIfmaf:
1045  case Builtin::BIfmal:
1046  case Builtin::BI__builtin_fma:
1047  case Builtin::BI__builtin_fmaf:
1048  case Builtin::BI__builtin_fmal: {
1049    // Rewrite fma to intrinsic.
1050    Value *FirstArg = EmitScalarExpr(E->getArg(0));
1051    llvm::Type *ArgType = FirstArg->getType();
1052    Value *F = CGM.getIntrinsic(Intrinsic::fma, ArgType);
1053    return RValue::get(Builder.CreateCall3(F, FirstArg,
1054                                              EmitScalarExpr(E->getArg(1)),
1055                                              EmitScalarExpr(E->getArg(2))));
1056  }
1057
1058  case Builtin::BI__builtin_signbit:
1059  case Builtin::BI__builtin_signbitf:
1060  case Builtin::BI__builtin_signbitl: {
1061    LLVMContext &C = CGM.getLLVMContext();
1062
1063    Value *Arg = EmitScalarExpr(E->getArg(0));
1064    llvm::Type *ArgTy = Arg->getType();
1065    if (ArgTy->isPPC_FP128Ty())
1066      break; // FIXME: I'm not sure what the right implementation is here.
1067    int ArgWidth = ArgTy->getPrimitiveSizeInBits();
1068    llvm::Type *ArgIntTy = llvm::IntegerType::get(C, ArgWidth);
1069    Value *BCArg = Builder.CreateBitCast(Arg, ArgIntTy);
1070    Value *ZeroCmp = llvm::Constant::getNullValue(ArgIntTy);
1071    Value *Result = Builder.CreateICmpSLT(BCArg, ZeroCmp);
1072    return RValue::get(Builder.CreateZExt(Result, ConvertType(E->getType())));
1073  }
1074  case Builtin::BI__builtin_annotation: {
1075    llvm::Value *AnnVal = EmitScalarExpr(E->getArg(0));
1076    llvm::Value *F = CGM.getIntrinsic(llvm::Intrinsic::annotation,
1077                                      AnnVal->getType());
1078
1079    // Get the annotation string, go through casts. Sema requires this to be a
1080    // non-wide string literal, potentially casted, so the cast<> is safe.
1081    const Expr *AnnotationStrExpr = E->getArg(1)->IgnoreParenCasts();
1082    llvm::StringRef Str = cast<StringLiteral>(AnnotationStrExpr)->getString();
1083    return RValue::get(EmitAnnotationCall(F, AnnVal, Str, E->getExprLoc()));
1084  }
1085  }
1086
1087  // If this is an alias for a lib function (e.g. __builtin_sin), emit
1088  // the call using the normal call path, but using the unmangled
1089  // version of the function name.
1090  if (getContext().BuiltinInfo.isLibFunction(BuiltinID))
1091    return emitLibraryCall(*this, FD, E,
1092                           CGM.getBuiltinLibFunction(FD, BuiltinID));
1093
1094  // If this is a predefined lib function (e.g. malloc), emit the call
1095  // using exactly the normal call path.
1096  if (getContext().BuiltinInfo.isPredefinedLibFunction(BuiltinID))
1097    return emitLibraryCall(*this, FD, E, EmitScalarExpr(E->getCallee()));
1098
1099  // See if we have a target specific intrinsic.
1100  const char *Name = getContext().BuiltinInfo.GetName(BuiltinID);
1101  Intrinsic::ID IntrinsicID = Intrinsic::not_intrinsic;
1102  if (const char *Prefix =
1103      llvm::Triple::getArchTypePrefix(Target.getTriple().getArch()))
1104    IntrinsicID = Intrinsic::getIntrinsicForGCCBuiltin(Prefix, Name);
1105
1106  if (IntrinsicID != Intrinsic::not_intrinsic) {
1107    SmallVector<Value*, 16> Args;
1108
1109    // Find out if any arguments are required to be integer constant
1110    // expressions.
1111    unsigned ICEArguments = 0;
1112    ASTContext::GetBuiltinTypeError Error;
1113    getContext().GetBuiltinType(BuiltinID, Error, &ICEArguments);
1114    assert(Error == ASTContext::GE_None && "Should not codegen an error");
1115
1116    Function *F = CGM.getIntrinsic(IntrinsicID);
1117    llvm::FunctionType *FTy = F->getFunctionType();
1118
1119    for (unsigned i = 0, e = E->getNumArgs(); i != e; ++i) {
1120      Value *ArgValue;
1121      // If this is a normal argument, just emit it as a scalar.
1122      if ((ICEArguments & (1 << i)) == 0) {
1123        ArgValue = EmitScalarExpr(E->getArg(i));
1124      } else {
1125        // If this is required to be a constant, constant fold it so that we
1126        // know that the generated intrinsic gets a ConstantInt.
1127        llvm::APSInt Result;
1128        bool IsConst = E->getArg(i)->isIntegerConstantExpr(Result,getContext());
1129        assert(IsConst && "Constant arg isn't actually constant?");
1130        (void)IsConst;
1131        ArgValue = llvm::ConstantInt::get(getLLVMContext(), Result);
1132      }
1133
1134      // If the intrinsic arg type is different from the builtin arg type
1135      // we need to do a bit cast.
1136      llvm::Type *PTy = FTy->getParamType(i);
1137      if (PTy != ArgValue->getType()) {
1138        assert(PTy->canLosslesslyBitCastTo(FTy->getParamType(i)) &&
1139               "Must be able to losslessly bit cast to param");
1140        ArgValue = Builder.CreateBitCast(ArgValue, PTy);
1141      }
1142
1143      Args.push_back(ArgValue);
1144    }
1145
1146    Value *V = Builder.CreateCall(F, Args);
1147    QualType BuiltinRetType = E->getType();
1148
1149    llvm::Type *RetTy = llvm::Type::getVoidTy(getLLVMContext());
1150    if (!BuiltinRetType->isVoidType()) RetTy = ConvertType(BuiltinRetType);
1151
1152    if (RetTy != V->getType()) {
1153      assert(V->getType()->canLosslesslyBitCastTo(RetTy) &&
1154             "Must be able to losslessly bit cast result type");
1155      V = Builder.CreateBitCast(V, RetTy);
1156    }
1157
1158    return RValue::get(V);
1159  }
1160
1161  // See if we have a target specific builtin that needs to be lowered.
1162  if (Value *V = EmitTargetBuiltinExpr(BuiltinID, E))
1163    return RValue::get(V);
1164
1165  ErrorUnsupported(E, "builtin function");
1166
1167  // Unknown builtin, for now just dump it out and return undef.
1168  if (hasAggregateLLVMType(E->getType()))
1169    return RValue::getAggregate(CreateMemTemp(E->getType()));
1170  return RValue::get(llvm::UndefValue::get(ConvertType(E->getType())));
1171}
1172
1173Value *CodeGenFunction::EmitTargetBuiltinExpr(unsigned BuiltinID,
1174                                              const CallExpr *E) {
1175  switch (Target.getTriple().getArch()) {
1176  case llvm::Triple::arm:
1177  case llvm::Triple::thumb:
1178    return EmitARMBuiltinExpr(BuiltinID, E);
1179  case llvm::Triple::x86:
1180  case llvm::Triple::x86_64:
1181    return EmitX86BuiltinExpr(BuiltinID, E);
1182  case llvm::Triple::ppc:
1183  case llvm::Triple::ppc64:
1184    return EmitPPCBuiltinExpr(BuiltinID, E);
1185  case llvm::Triple::hexagon:
1186    return EmitHexagonBuiltinExpr(BuiltinID, E);
1187  default:
1188    return 0;
1189  }
1190}
1191
1192static llvm::VectorType *GetNeonType(LLVMContext &C, NeonTypeFlags TypeFlags) {
1193  int IsQuad = TypeFlags.isQuad();
1194  switch (TypeFlags.getEltType()) {
1195  default: break;
1196  case NeonTypeFlags::Int8:
1197  case NeonTypeFlags::Poly8:
1198    return llvm::VectorType::get(llvm::Type::getInt8Ty(C), 8 << IsQuad);
1199  case NeonTypeFlags::Int16:
1200  case NeonTypeFlags::Poly16:
1201  case NeonTypeFlags::Float16:
1202    return llvm::VectorType::get(llvm::Type::getInt16Ty(C), 4 << IsQuad);
1203  case NeonTypeFlags::Int32:
1204    return llvm::VectorType::get(llvm::Type::getInt32Ty(C), 2 << IsQuad);
1205  case NeonTypeFlags::Int64:
1206    return llvm::VectorType::get(llvm::Type::getInt64Ty(C), 1 << IsQuad);
1207  case NeonTypeFlags::Float32:
1208    return llvm::VectorType::get(llvm::Type::getFloatTy(C), 2 << IsQuad);
1209  };
1210  return 0;
1211}
1212
1213Value *CodeGenFunction::EmitNeonSplat(Value *V, Constant *C) {
1214  unsigned nElts = cast<llvm::VectorType>(V->getType())->getNumElements();
1215  SmallVector<Constant*, 16> Indices(nElts, C);
1216  Value* SV = llvm::ConstantVector::get(Indices);
1217  return Builder.CreateShuffleVector(V, V, SV, "lane");
1218}
1219
1220Value *CodeGenFunction::EmitNeonCall(Function *F, SmallVectorImpl<Value*> &Ops,
1221                                     const char *name,
1222                                     unsigned shift, bool rightshift) {
1223  unsigned j = 0;
1224  for (Function::const_arg_iterator ai = F->arg_begin(), ae = F->arg_end();
1225       ai != ae; ++ai, ++j)
1226    if (shift > 0 && shift == j)
1227      Ops[j] = EmitNeonShiftVector(Ops[j], ai->getType(), rightshift);
1228    else
1229      Ops[j] = Builder.CreateBitCast(Ops[j], ai->getType(), name);
1230
1231  return Builder.CreateCall(F, Ops, name);
1232}
1233
1234Value *CodeGenFunction::EmitNeonShiftVector(Value *V, llvm::Type *Ty,
1235                                            bool neg) {
1236  ConstantInt *CI = cast<ConstantInt>(V);
1237  int SV = CI->getSExtValue();
1238
1239  llvm::VectorType *VTy = cast<llvm::VectorType>(Ty);
1240  llvm::Constant *C = ConstantInt::get(VTy->getElementType(), neg ? -SV : SV);
1241  SmallVector<llvm::Constant*, 16> CV(VTy->getNumElements(), C);
1242  return llvm::ConstantVector::get(CV);
1243}
1244
1245/// GetPointeeAlignment - Given an expression with a pointer type, find the
1246/// alignment of the type referenced by the pointer.  Skip over implicit
1247/// casts.
1248static Value *GetPointeeAlignment(CodeGenFunction &CGF, const Expr *Addr) {
1249  unsigned Align = 1;
1250  // Check if the type is a pointer.  The implicit cast operand might not be.
1251  while (Addr->getType()->isPointerType()) {
1252    QualType PtTy = Addr->getType()->getPointeeType();
1253    unsigned NewA = CGF.getContext().getTypeAlignInChars(PtTy).getQuantity();
1254    if (NewA > Align)
1255      Align = NewA;
1256
1257    // If the address is an implicit cast, repeat with the cast operand.
1258    if (const ImplicitCastExpr *CastAddr = dyn_cast<ImplicitCastExpr>(Addr)) {
1259      Addr = CastAddr->getSubExpr();
1260      continue;
1261    }
1262    break;
1263  }
1264  return llvm::ConstantInt::get(CGF.Int32Ty, Align);
1265}
1266
1267Value *CodeGenFunction::EmitARMBuiltinExpr(unsigned BuiltinID,
1268                                           const CallExpr *E) {
1269  if (BuiltinID == ARM::BI__clear_cache) {
1270    const FunctionDecl *FD = E->getDirectCallee();
1271    // Oddly people write this call without args on occasion and gcc accepts
1272    // it - it's also marked as varargs in the description file.
1273    SmallVector<Value*, 2> Ops;
1274    for (unsigned i = 0; i < E->getNumArgs(); i++)
1275      Ops.push_back(EmitScalarExpr(E->getArg(i)));
1276    llvm::Type *Ty = CGM.getTypes().ConvertType(FD->getType());
1277    llvm::FunctionType *FTy = cast<llvm::FunctionType>(Ty);
1278    StringRef Name = FD->getName();
1279    return Builder.CreateCall(CGM.CreateRuntimeFunction(FTy, Name), Ops);
1280  }
1281
1282  if (BuiltinID == ARM::BI__builtin_arm_ldrexd) {
1283    Function *F = CGM.getIntrinsic(Intrinsic::arm_ldrexd);
1284
1285    Value *LdPtr = EmitScalarExpr(E->getArg(0));
1286    Value *Val = Builder.CreateCall(F, LdPtr, "ldrexd");
1287
1288    Value *Val0 = Builder.CreateExtractValue(Val, 1);
1289    Value *Val1 = Builder.CreateExtractValue(Val, 0);
1290    Val0 = Builder.CreateZExt(Val0, Int64Ty);
1291    Val1 = Builder.CreateZExt(Val1, Int64Ty);
1292
1293    Value *ShiftCst = llvm::ConstantInt::get(Int64Ty, 32);
1294    Val = Builder.CreateShl(Val0, ShiftCst, "shl", true /* nuw */);
1295    return Builder.CreateOr(Val, Val1);
1296  }
1297
1298  if (BuiltinID == ARM::BI__builtin_arm_strexd) {
1299    Function *F = CGM.getIntrinsic(Intrinsic::arm_strexd);
1300    llvm::Type *STy = llvm::StructType::get(Int32Ty, Int32Ty, NULL);
1301
1302    Value *One = llvm::ConstantInt::get(Int32Ty, 1);
1303    Value *Tmp = Builder.CreateAlloca(Int64Ty, One);
1304    Value *Val = EmitScalarExpr(E->getArg(0));
1305    Builder.CreateStore(Val, Tmp);
1306
1307    Value *LdPtr = Builder.CreateBitCast(Tmp,llvm::PointerType::getUnqual(STy));
1308    Val = Builder.CreateLoad(LdPtr);
1309
1310    Value *Arg0 = Builder.CreateExtractValue(Val, 0);
1311    Value *Arg1 = Builder.CreateExtractValue(Val, 1);
1312    Value *StPtr = EmitScalarExpr(E->getArg(1));
1313    return Builder.CreateCall3(F, Arg0, Arg1, StPtr, "strexd");
1314  }
1315
1316  SmallVector<Value*, 4> Ops;
1317  for (unsigned i = 0, e = E->getNumArgs() - 1; i != e; i++)
1318    Ops.push_back(EmitScalarExpr(E->getArg(i)));
1319
1320  // vget_lane and vset_lane are not overloaded and do not have an extra
1321  // argument that specifies the vector type.
1322  switch (BuiltinID) {
1323  default: break;
1324  case ARM::BI__builtin_neon_vget_lane_i8:
1325  case ARM::BI__builtin_neon_vget_lane_i16:
1326  case ARM::BI__builtin_neon_vget_lane_i32:
1327  case ARM::BI__builtin_neon_vget_lane_i64:
1328  case ARM::BI__builtin_neon_vget_lane_f32:
1329  case ARM::BI__builtin_neon_vgetq_lane_i8:
1330  case ARM::BI__builtin_neon_vgetq_lane_i16:
1331  case ARM::BI__builtin_neon_vgetq_lane_i32:
1332  case ARM::BI__builtin_neon_vgetq_lane_i64:
1333  case ARM::BI__builtin_neon_vgetq_lane_f32:
1334    return Builder.CreateExtractElement(Ops[0], EmitScalarExpr(E->getArg(1)),
1335                                        "vget_lane");
1336  case ARM::BI__builtin_neon_vset_lane_i8:
1337  case ARM::BI__builtin_neon_vset_lane_i16:
1338  case ARM::BI__builtin_neon_vset_lane_i32:
1339  case ARM::BI__builtin_neon_vset_lane_i64:
1340  case ARM::BI__builtin_neon_vset_lane_f32:
1341  case ARM::BI__builtin_neon_vsetq_lane_i8:
1342  case ARM::BI__builtin_neon_vsetq_lane_i16:
1343  case ARM::BI__builtin_neon_vsetq_lane_i32:
1344  case ARM::BI__builtin_neon_vsetq_lane_i64:
1345  case ARM::BI__builtin_neon_vsetq_lane_f32:
1346    Ops.push_back(EmitScalarExpr(E->getArg(2)));
1347    return Builder.CreateInsertElement(Ops[1], Ops[0], Ops[2], "vset_lane");
1348  }
1349
1350  // Get the last argument, which specifies the vector type.
1351  llvm::APSInt Result;
1352  const Expr *Arg = E->getArg(E->getNumArgs()-1);
1353  if (!Arg->isIntegerConstantExpr(Result, getContext()))
1354    return 0;
1355
1356  if (BuiltinID == ARM::BI__builtin_arm_vcvtr_f ||
1357      BuiltinID == ARM::BI__builtin_arm_vcvtr_d) {
1358    // Determine the overloaded type of this builtin.
1359    llvm::Type *Ty;
1360    if (BuiltinID == ARM::BI__builtin_arm_vcvtr_f)
1361      Ty = llvm::Type::getFloatTy(getLLVMContext());
1362    else
1363      Ty = llvm::Type::getDoubleTy(getLLVMContext());
1364
1365    // Determine whether this is an unsigned conversion or not.
1366    bool usgn = Result.getZExtValue() == 1;
1367    unsigned Int = usgn ? Intrinsic::arm_vcvtru : Intrinsic::arm_vcvtr;
1368
1369    // Call the appropriate intrinsic.
1370    Function *F = CGM.getIntrinsic(Int, Ty);
1371    return Builder.CreateCall(F, Ops, "vcvtr");
1372  }
1373
1374  // Determine the type of this overloaded NEON intrinsic.
1375  NeonTypeFlags Type(Result.getZExtValue());
1376  bool usgn = Type.isUnsigned();
1377  bool quad = Type.isQuad();
1378  bool rightShift = false;
1379
1380  llvm::VectorType *VTy = GetNeonType(getLLVMContext(), Type);
1381  llvm::Type *Ty = VTy;
1382  if (!Ty)
1383    return 0;
1384
1385  unsigned Int;
1386  switch (BuiltinID) {
1387  default: return 0;
1388  case ARM::BI__builtin_neon_vabd_v:
1389  case ARM::BI__builtin_neon_vabdq_v:
1390    Int = usgn ? Intrinsic::arm_neon_vabdu : Intrinsic::arm_neon_vabds;
1391    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vabd");
1392  case ARM::BI__builtin_neon_vabs_v:
1393  case ARM::BI__builtin_neon_vabsq_v:
1394    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vabs, Ty),
1395                        Ops, "vabs");
1396  case ARM::BI__builtin_neon_vaddhn_v:
1397    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vaddhn, Ty),
1398                        Ops, "vaddhn");
1399  case ARM::BI__builtin_neon_vcale_v:
1400    std::swap(Ops[0], Ops[1]);
1401  case ARM::BI__builtin_neon_vcage_v: {
1402    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vacged);
1403    return EmitNeonCall(F, Ops, "vcage");
1404  }
1405  case ARM::BI__builtin_neon_vcaleq_v:
1406    std::swap(Ops[0], Ops[1]);
1407  case ARM::BI__builtin_neon_vcageq_v: {
1408    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vacgeq);
1409    return EmitNeonCall(F, Ops, "vcage");
1410  }
1411  case ARM::BI__builtin_neon_vcalt_v:
1412    std::swap(Ops[0], Ops[1]);
1413  case ARM::BI__builtin_neon_vcagt_v: {
1414    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vacgtd);
1415    return EmitNeonCall(F, Ops, "vcagt");
1416  }
1417  case ARM::BI__builtin_neon_vcaltq_v:
1418    std::swap(Ops[0], Ops[1]);
1419  case ARM::BI__builtin_neon_vcagtq_v: {
1420    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vacgtq);
1421    return EmitNeonCall(F, Ops, "vcagt");
1422  }
1423  case ARM::BI__builtin_neon_vcls_v:
1424  case ARM::BI__builtin_neon_vclsq_v: {
1425    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vcls, Ty);
1426    return EmitNeonCall(F, Ops, "vcls");
1427  }
1428  case ARM::BI__builtin_neon_vclz_v:
1429  case ARM::BI__builtin_neon_vclzq_v: {
1430    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vclz, Ty);
1431    return EmitNeonCall(F, Ops, "vclz");
1432  }
1433  case ARM::BI__builtin_neon_vcnt_v:
1434  case ARM::BI__builtin_neon_vcntq_v: {
1435    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vcnt, Ty);
1436    return EmitNeonCall(F, Ops, "vcnt");
1437  }
1438  case ARM::BI__builtin_neon_vcvt_f16_v: {
1439    assert(Type.getEltType() == NeonTypeFlags::Float16 && !quad &&
1440           "unexpected vcvt_f16_v builtin");
1441    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vcvtfp2hf);
1442    return EmitNeonCall(F, Ops, "vcvt");
1443  }
1444  case ARM::BI__builtin_neon_vcvt_f32_f16: {
1445    assert(Type.getEltType() == NeonTypeFlags::Float16 && !quad &&
1446           "unexpected vcvt_f32_f16 builtin");
1447    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vcvthf2fp);
1448    return EmitNeonCall(F, Ops, "vcvt");
1449  }
1450  case ARM::BI__builtin_neon_vcvt_f32_v:
1451  case ARM::BI__builtin_neon_vcvtq_f32_v:
1452    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1453    Ty = GetNeonType(getLLVMContext(),
1454                     NeonTypeFlags(NeonTypeFlags::Float32, false, quad));
1455    return usgn ? Builder.CreateUIToFP(Ops[0], Ty, "vcvt")
1456                : Builder.CreateSIToFP(Ops[0], Ty, "vcvt");
1457  case ARM::BI__builtin_neon_vcvt_s32_v:
1458  case ARM::BI__builtin_neon_vcvt_u32_v:
1459  case ARM::BI__builtin_neon_vcvtq_s32_v:
1460  case ARM::BI__builtin_neon_vcvtq_u32_v: {
1461    llvm::Type *FloatTy =
1462      GetNeonType(getLLVMContext(),
1463                  NeonTypeFlags(NeonTypeFlags::Float32, false, quad));
1464    Ops[0] = Builder.CreateBitCast(Ops[0], FloatTy);
1465    return usgn ? Builder.CreateFPToUI(Ops[0], Ty, "vcvt")
1466                : Builder.CreateFPToSI(Ops[0], Ty, "vcvt");
1467  }
1468  case ARM::BI__builtin_neon_vcvt_n_f32_v:
1469  case ARM::BI__builtin_neon_vcvtq_n_f32_v: {
1470    llvm::Type *FloatTy =
1471      GetNeonType(getLLVMContext(),
1472                  NeonTypeFlags(NeonTypeFlags::Float32, false, quad));
1473    llvm::Type *Tys[2] = { FloatTy, Ty };
1474    Int = usgn ? Intrinsic::arm_neon_vcvtfxu2fp
1475               : Intrinsic::arm_neon_vcvtfxs2fp;
1476    Function *F = CGM.getIntrinsic(Int, Tys);
1477    return EmitNeonCall(F, Ops, "vcvt_n");
1478  }
1479  case ARM::BI__builtin_neon_vcvt_n_s32_v:
1480  case ARM::BI__builtin_neon_vcvt_n_u32_v:
1481  case ARM::BI__builtin_neon_vcvtq_n_s32_v:
1482  case ARM::BI__builtin_neon_vcvtq_n_u32_v: {
1483    llvm::Type *FloatTy =
1484      GetNeonType(getLLVMContext(),
1485                  NeonTypeFlags(NeonTypeFlags::Float32, false, quad));
1486    llvm::Type *Tys[2] = { Ty, FloatTy };
1487    Int = usgn ? Intrinsic::arm_neon_vcvtfp2fxu
1488               : Intrinsic::arm_neon_vcvtfp2fxs;
1489    Function *F = CGM.getIntrinsic(Int, Tys);
1490    return EmitNeonCall(F, Ops, "vcvt_n");
1491  }
1492  case ARM::BI__builtin_neon_vext_v:
1493  case ARM::BI__builtin_neon_vextq_v: {
1494    int CV = cast<ConstantInt>(Ops[2])->getSExtValue();
1495    SmallVector<Constant*, 16> Indices;
1496    for (unsigned i = 0, e = VTy->getNumElements(); i != e; ++i)
1497      Indices.push_back(ConstantInt::get(Int32Ty, i+CV));
1498
1499    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1500    Ops[1] = Builder.CreateBitCast(Ops[1], Ty);
1501    Value *SV = llvm::ConstantVector::get(Indices);
1502    return Builder.CreateShuffleVector(Ops[0], Ops[1], SV, "vext");
1503  }
1504  case ARM::BI__builtin_neon_vhadd_v:
1505  case ARM::BI__builtin_neon_vhaddq_v:
1506    Int = usgn ? Intrinsic::arm_neon_vhaddu : Intrinsic::arm_neon_vhadds;
1507    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vhadd");
1508  case ARM::BI__builtin_neon_vhsub_v:
1509  case ARM::BI__builtin_neon_vhsubq_v:
1510    Int = usgn ? Intrinsic::arm_neon_vhsubu : Intrinsic::arm_neon_vhsubs;
1511    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vhsub");
1512  case ARM::BI__builtin_neon_vld1_v:
1513  case ARM::BI__builtin_neon_vld1q_v:
1514    Ops.push_back(GetPointeeAlignment(*this, E->getArg(0)));
1515    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vld1, Ty),
1516                        Ops, "vld1");
1517  case ARM::BI__builtin_neon_vld1_lane_v:
1518  case ARM::BI__builtin_neon_vld1q_lane_v:
1519    Ops[1] = Builder.CreateBitCast(Ops[1], Ty);
1520    Ty = llvm::PointerType::getUnqual(VTy->getElementType());
1521    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1522    Ops[0] = Builder.CreateLoad(Ops[0]);
1523    return Builder.CreateInsertElement(Ops[1], Ops[0], Ops[2], "vld1_lane");
1524  case ARM::BI__builtin_neon_vld1_dup_v:
1525  case ARM::BI__builtin_neon_vld1q_dup_v: {
1526    Value *V = UndefValue::get(Ty);
1527    Ty = llvm::PointerType::getUnqual(VTy->getElementType());
1528    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1529    Ops[0] = Builder.CreateLoad(Ops[0]);
1530    llvm::Constant *CI = ConstantInt::get(Int32Ty, 0);
1531    Ops[0] = Builder.CreateInsertElement(V, Ops[0], CI);
1532    return EmitNeonSplat(Ops[0], CI);
1533  }
1534  case ARM::BI__builtin_neon_vld2_v:
1535  case ARM::BI__builtin_neon_vld2q_v: {
1536    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vld2, Ty);
1537    Value *Align = GetPointeeAlignment(*this, E->getArg(1));
1538    Ops[1] = Builder.CreateCall2(F, Ops[1], Align, "vld2");
1539    Ty = llvm::PointerType::getUnqual(Ops[1]->getType());
1540    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1541    return Builder.CreateStore(Ops[1], Ops[0]);
1542  }
1543  case ARM::BI__builtin_neon_vld3_v:
1544  case ARM::BI__builtin_neon_vld3q_v: {
1545    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vld3, Ty);
1546    Value *Align = GetPointeeAlignment(*this, E->getArg(1));
1547    Ops[1] = Builder.CreateCall2(F, Ops[1], Align, "vld3");
1548    Ty = llvm::PointerType::getUnqual(Ops[1]->getType());
1549    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1550    return Builder.CreateStore(Ops[1], Ops[0]);
1551  }
1552  case ARM::BI__builtin_neon_vld4_v:
1553  case ARM::BI__builtin_neon_vld4q_v: {
1554    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vld4, Ty);
1555    Value *Align = GetPointeeAlignment(*this, E->getArg(1));
1556    Ops[1] = Builder.CreateCall2(F, Ops[1], Align, "vld4");
1557    Ty = llvm::PointerType::getUnqual(Ops[1]->getType());
1558    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1559    return Builder.CreateStore(Ops[1], Ops[0]);
1560  }
1561  case ARM::BI__builtin_neon_vld2_lane_v:
1562  case ARM::BI__builtin_neon_vld2q_lane_v: {
1563    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vld2lane, Ty);
1564    Ops[2] = Builder.CreateBitCast(Ops[2], Ty);
1565    Ops[3] = Builder.CreateBitCast(Ops[3], Ty);
1566    Ops.push_back(GetPointeeAlignment(*this, E->getArg(1)));
1567    Ops[1] = Builder.CreateCall(F, makeArrayRef(Ops).slice(1), "vld2_lane");
1568    Ty = llvm::PointerType::getUnqual(Ops[1]->getType());
1569    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1570    return Builder.CreateStore(Ops[1], Ops[0]);
1571  }
1572  case ARM::BI__builtin_neon_vld3_lane_v:
1573  case ARM::BI__builtin_neon_vld3q_lane_v: {
1574    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vld3lane, Ty);
1575    Ops[2] = Builder.CreateBitCast(Ops[2], Ty);
1576    Ops[3] = Builder.CreateBitCast(Ops[3], Ty);
1577    Ops[4] = Builder.CreateBitCast(Ops[4], Ty);
1578    Ops.push_back(GetPointeeAlignment(*this, E->getArg(1)));
1579    Ops[1] = Builder.CreateCall(F, makeArrayRef(Ops).slice(1), "vld3_lane");
1580    Ty = llvm::PointerType::getUnqual(Ops[1]->getType());
1581    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1582    return Builder.CreateStore(Ops[1], Ops[0]);
1583  }
1584  case ARM::BI__builtin_neon_vld4_lane_v:
1585  case ARM::BI__builtin_neon_vld4q_lane_v: {
1586    Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vld4lane, Ty);
1587    Ops[2] = Builder.CreateBitCast(Ops[2], Ty);
1588    Ops[3] = Builder.CreateBitCast(Ops[3], Ty);
1589    Ops[4] = Builder.CreateBitCast(Ops[4], Ty);
1590    Ops[5] = Builder.CreateBitCast(Ops[5], Ty);
1591    Ops.push_back(GetPointeeAlignment(*this, E->getArg(1)));
1592    Ops[1] = Builder.CreateCall(F, makeArrayRef(Ops).slice(1), "vld3_lane");
1593    Ty = llvm::PointerType::getUnqual(Ops[1]->getType());
1594    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1595    return Builder.CreateStore(Ops[1], Ops[0]);
1596  }
1597  case ARM::BI__builtin_neon_vld2_dup_v:
1598  case ARM::BI__builtin_neon_vld3_dup_v:
1599  case ARM::BI__builtin_neon_vld4_dup_v: {
1600    // Handle 64-bit elements as a special-case.  There is no "dup" needed.
1601    if (VTy->getElementType()->getPrimitiveSizeInBits() == 64) {
1602      switch (BuiltinID) {
1603      case ARM::BI__builtin_neon_vld2_dup_v:
1604        Int = Intrinsic::arm_neon_vld2;
1605        break;
1606      case ARM::BI__builtin_neon_vld3_dup_v:
1607        Int = Intrinsic::arm_neon_vld2;
1608        break;
1609      case ARM::BI__builtin_neon_vld4_dup_v:
1610        Int = Intrinsic::arm_neon_vld2;
1611        break;
1612      default: llvm_unreachable("unknown vld_dup intrinsic?");
1613      }
1614      Function *F = CGM.getIntrinsic(Int, Ty);
1615      Value *Align = GetPointeeAlignment(*this, E->getArg(1));
1616      Ops[1] = Builder.CreateCall2(F, Ops[1], Align, "vld_dup");
1617      Ty = llvm::PointerType::getUnqual(Ops[1]->getType());
1618      Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1619      return Builder.CreateStore(Ops[1], Ops[0]);
1620    }
1621    switch (BuiltinID) {
1622    case ARM::BI__builtin_neon_vld2_dup_v:
1623      Int = Intrinsic::arm_neon_vld2lane;
1624      break;
1625    case ARM::BI__builtin_neon_vld3_dup_v:
1626      Int = Intrinsic::arm_neon_vld2lane;
1627      break;
1628    case ARM::BI__builtin_neon_vld4_dup_v:
1629      Int = Intrinsic::arm_neon_vld2lane;
1630      break;
1631    default: llvm_unreachable("unknown vld_dup intrinsic?");
1632    }
1633    Function *F = CGM.getIntrinsic(Int, Ty);
1634    llvm::StructType *STy = cast<llvm::StructType>(F->getReturnType());
1635
1636    SmallVector<Value*, 6> Args;
1637    Args.push_back(Ops[1]);
1638    Args.append(STy->getNumElements(), UndefValue::get(Ty));
1639
1640    llvm::Constant *CI = ConstantInt::get(Int32Ty, 0);
1641    Args.push_back(CI);
1642    Args.push_back(GetPointeeAlignment(*this, E->getArg(1)));
1643
1644    Ops[1] = Builder.CreateCall(F, Args, "vld_dup");
1645    // splat lane 0 to all elts in each vector of the result.
1646    for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1647      Value *Val = Builder.CreateExtractValue(Ops[1], i);
1648      Value *Elt = Builder.CreateBitCast(Val, Ty);
1649      Elt = EmitNeonSplat(Elt, CI);
1650      Elt = Builder.CreateBitCast(Elt, Val->getType());
1651      Ops[1] = Builder.CreateInsertValue(Ops[1], Elt, i);
1652    }
1653    Ty = llvm::PointerType::getUnqual(Ops[1]->getType());
1654    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1655    return Builder.CreateStore(Ops[1], Ops[0]);
1656  }
1657  case ARM::BI__builtin_neon_vmax_v:
1658  case ARM::BI__builtin_neon_vmaxq_v:
1659    Int = usgn ? Intrinsic::arm_neon_vmaxu : Intrinsic::arm_neon_vmaxs;
1660    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vmax");
1661  case ARM::BI__builtin_neon_vmin_v:
1662  case ARM::BI__builtin_neon_vminq_v:
1663    Int = usgn ? Intrinsic::arm_neon_vminu : Intrinsic::arm_neon_vmins;
1664    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vmin");
1665  case ARM::BI__builtin_neon_vmovl_v: {
1666    llvm::Type *DTy =llvm::VectorType::getTruncatedElementVectorType(VTy);
1667    Ops[0] = Builder.CreateBitCast(Ops[0], DTy);
1668    if (usgn)
1669      return Builder.CreateZExt(Ops[0], Ty, "vmovl");
1670    return Builder.CreateSExt(Ops[0], Ty, "vmovl");
1671  }
1672  case ARM::BI__builtin_neon_vmovn_v: {
1673    llvm::Type *QTy = llvm::VectorType::getExtendedElementVectorType(VTy);
1674    Ops[0] = Builder.CreateBitCast(Ops[0], QTy);
1675    return Builder.CreateTrunc(Ops[0], Ty, "vmovn");
1676  }
1677  case ARM::BI__builtin_neon_vmul_v:
1678  case ARM::BI__builtin_neon_vmulq_v:
1679    assert(Type.isPoly() && "vmul builtin only supported for polynomial types");
1680    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vmulp, Ty),
1681                        Ops, "vmul");
1682  case ARM::BI__builtin_neon_vmull_v:
1683    Int = usgn ? Intrinsic::arm_neon_vmullu : Intrinsic::arm_neon_vmulls;
1684    Int = Type.isPoly() ? (unsigned)Intrinsic::arm_neon_vmullp : Int;
1685    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vmull");
1686  case ARM::BI__builtin_neon_vpadal_v:
1687  case ARM::BI__builtin_neon_vpadalq_v: {
1688    Int = usgn ? Intrinsic::arm_neon_vpadalu : Intrinsic::arm_neon_vpadals;
1689    // The source operand type has twice as many elements of half the size.
1690    unsigned EltBits = VTy->getElementType()->getPrimitiveSizeInBits();
1691    llvm::Type *EltTy =
1692      llvm::IntegerType::get(getLLVMContext(), EltBits / 2);
1693    llvm::Type *NarrowTy =
1694      llvm::VectorType::get(EltTy, VTy->getNumElements() * 2);
1695    llvm::Type *Tys[2] = { Ty, NarrowTy };
1696    return EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vpadal");
1697  }
1698  case ARM::BI__builtin_neon_vpadd_v:
1699    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vpadd, Ty),
1700                        Ops, "vpadd");
1701  case ARM::BI__builtin_neon_vpaddl_v:
1702  case ARM::BI__builtin_neon_vpaddlq_v: {
1703    Int = usgn ? Intrinsic::arm_neon_vpaddlu : Intrinsic::arm_neon_vpaddls;
1704    // The source operand type has twice as many elements of half the size.
1705    unsigned EltBits = VTy->getElementType()->getPrimitiveSizeInBits();
1706    llvm::Type *EltTy = llvm::IntegerType::get(getLLVMContext(), EltBits / 2);
1707    llvm::Type *NarrowTy =
1708      llvm::VectorType::get(EltTy, VTy->getNumElements() * 2);
1709    llvm::Type *Tys[2] = { Ty, NarrowTy };
1710    return EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vpaddl");
1711  }
1712  case ARM::BI__builtin_neon_vpmax_v:
1713    Int = usgn ? Intrinsic::arm_neon_vpmaxu : Intrinsic::arm_neon_vpmaxs;
1714    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vpmax");
1715  case ARM::BI__builtin_neon_vpmin_v:
1716    Int = usgn ? Intrinsic::arm_neon_vpminu : Intrinsic::arm_neon_vpmins;
1717    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vpmin");
1718  case ARM::BI__builtin_neon_vqabs_v:
1719  case ARM::BI__builtin_neon_vqabsq_v:
1720    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqabs, Ty),
1721                        Ops, "vqabs");
1722  case ARM::BI__builtin_neon_vqadd_v:
1723  case ARM::BI__builtin_neon_vqaddq_v:
1724    Int = usgn ? Intrinsic::arm_neon_vqaddu : Intrinsic::arm_neon_vqadds;
1725    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqadd");
1726  case ARM::BI__builtin_neon_vqdmlal_v:
1727    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqdmlal, Ty),
1728                        Ops, "vqdmlal");
1729  case ARM::BI__builtin_neon_vqdmlsl_v:
1730    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqdmlsl, Ty),
1731                        Ops, "vqdmlsl");
1732  case ARM::BI__builtin_neon_vqdmulh_v:
1733  case ARM::BI__builtin_neon_vqdmulhq_v:
1734    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqdmulh, Ty),
1735                        Ops, "vqdmulh");
1736  case ARM::BI__builtin_neon_vqdmull_v:
1737    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqdmull, Ty),
1738                        Ops, "vqdmull");
1739  case ARM::BI__builtin_neon_vqmovn_v:
1740    Int = usgn ? Intrinsic::arm_neon_vqmovnu : Intrinsic::arm_neon_vqmovns;
1741    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqmovn");
1742  case ARM::BI__builtin_neon_vqmovun_v:
1743    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqmovnsu, Ty),
1744                        Ops, "vqdmull");
1745  case ARM::BI__builtin_neon_vqneg_v:
1746  case ARM::BI__builtin_neon_vqnegq_v:
1747    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqneg, Ty),
1748                        Ops, "vqneg");
1749  case ARM::BI__builtin_neon_vqrdmulh_v:
1750  case ARM::BI__builtin_neon_vqrdmulhq_v:
1751    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqrdmulh, Ty),
1752                        Ops, "vqrdmulh");
1753  case ARM::BI__builtin_neon_vqrshl_v:
1754  case ARM::BI__builtin_neon_vqrshlq_v:
1755    Int = usgn ? Intrinsic::arm_neon_vqrshiftu : Intrinsic::arm_neon_vqrshifts;
1756    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqrshl");
1757  case ARM::BI__builtin_neon_vqrshrn_n_v:
1758    Int = usgn ? Intrinsic::arm_neon_vqrshiftnu : Intrinsic::arm_neon_vqrshiftns;
1759    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqrshrn_n",
1760                        1, true);
1761  case ARM::BI__builtin_neon_vqrshrun_n_v:
1762    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqrshiftnsu, Ty),
1763                        Ops, "vqrshrun_n", 1, true);
1764  case ARM::BI__builtin_neon_vqshl_v:
1765  case ARM::BI__builtin_neon_vqshlq_v:
1766    Int = usgn ? Intrinsic::arm_neon_vqshiftu : Intrinsic::arm_neon_vqshifts;
1767    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqshl");
1768  case ARM::BI__builtin_neon_vqshl_n_v:
1769  case ARM::BI__builtin_neon_vqshlq_n_v:
1770    Int = usgn ? Intrinsic::arm_neon_vqshiftu : Intrinsic::arm_neon_vqshifts;
1771    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqshl_n",
1772                        1, false);
1773  case ARM::BI__builtin_neon_vqshlu_n_v:
1774  case ARM::BI__builtin_neon_vqshluq_n_v:
1775    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqshiftsu, Ty),
1776                        Ops, "vqshlu", 1, false);
1777  case ARM::BI__builtin_neon_vqshrn_n_v:
1778    Int = usgn ? Intrinsic::arm_neon_vqshiftnu : Intrinsic::arm_neon_vqshiftns;
1779    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqshrn_n",
1780                        1, true);
1781  case ARM::BI__builtin_neon_vqshrun_n_v:
1782    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vqshiftnsu, Ty),
1783                        Ops, "vqshrun_n", 1, true);
1784  case ARM::BI__builtin_neon_vqsub_v:
1785  case ARM::BI__builtin_neon_vqsubq_v:
1786    Int = usgn ? Intrinsic::arm_neon_vqsubu : Intrinsic::arm_neon_vqsubs;
1787    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vqsub");
1788  case ARM::BI__builtin_neon_vraddhn_v:
1789    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vraddhn, Ty),
1790                        Ops, "vraddhn");
1791  case ARM::BI__builtin_neon_vrecpe_v:
1792  case ARM::BI__builtin_neon_vrecpeq_v:
1793    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vrecpe, Ty),
1794                        Ops, "vrecpe");
1795  case ARM::BI__builtin_neon_vrecps_v:
1796  case ARM::BI__builtin_neon_vrecpsq_v:
1797    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vrecps, Ty),
1798                        Ops, "vrecps");
1799  case ARM::BI__builtin_neon_vrhadd_v:
1800  case ARM::BI__builtin_neon_vrhaddq_v:
1801    Int = usgn ? Intrinsic::arm_neon_vrhaddu : Intrinsic::arm_neon_vrhadds;
1802    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vrhadd");
1803  case ARM::BI__builtin_neon_vrshl_v:
1804  case ARM::BI__builtin_neon_vrshlq_v:
1805    Int = usgn ? Intrinsic::arm_neon_vrshiftu : Intrinsic::arm_neon_vrshifts;
1806    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vrshl");
1807  case ARM::BI__builtin_neon_vrshrn_n_v:
1808    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vrshiftn, Ty),
1809                        Ops, "vrshrn_n", 1, true);
1810  case ARM::BI__builtin_neon_vrshr_n_v:
1811  case ARM::BI__builtin_neon_vrshrq_n_v:
1812    Int = usgn ? Intrinsic::arm_neon_vrshiftu : Intrinsic::arm_neon_vrshifts;
1813    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vrshr_n", 1, true);
1814  case ARM::BI__builtin_neon_vrsqrte_v:
1815  case ARM::BI__builtin_neon_vrsqrteq_v:
1816    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vrsqrte, Ty),
1817                        Ops, "vrsqrte");
1818  case ARM::BI__builtin_neon_vrsqrts_v:
1819  case ARM::BI__builtin_neon_vrsqrtsq_v:
1820    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vrsqrts, Ty),
1821                        Ops, "vrsqrts");
1822  case ARM::BI__builtin_neon_vrsra_n_v:
1823  case ARM::BI__builtin_neon_vrsraq_n_v:
1824    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1825    Ops[1] = Builder.CreateBitCast(Ops[1], Ty);
1826    Ops[2] = EmitNeonShiftVector(Ops[2], Ty, true);
1827    Int = usgn ? Intrinsic::arm_neon_vrshiftu : Intrinsic::arm_neon_vrshifts;
1828    Ops[1] = Builder.CreateCall2(CGM.getIntrinsic(Int, Ty), Ops[1], Ops[2]);
1829    return Builder.CreateAdd(Ops[0], Ops[1], "vrsra_n");
1830  case ARM::BI__builtin_neon_vrsubhn_v:
1831    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vrsubhn, Ty),
1832                        Ops, "vrsubhn");
1833  case ARM::BI__builtin_neon_vshl_v:
1834  case ARM::BI__builtin_neon_vshlq_v:
1835    Int = usgn ? Intrinsic::arm_neon_vshiftu : Intrinsic::arm_neon_vshifts;
1836    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vshl");
1837  case ARM::BI__builtin_neon_vshll_n_v:
1838    Int = usgn ? Intrinsic::arm_neon_vshiftlu : Intrinsic::arm_neon_vshiftls;
1839    return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "vshll", 1);
1840  case ARM::BI__builtin_neon_vshl_n_v:
1841  case ARM::BI__builtin_neon_vshlq_n_v:
1842    Ops[1] = EmitNeonShiftVector(Ops[1], Ty, false);
1843    return Builder.CreateShl(Builder.CreateBitCast(Ops[0],Ty), Ops[1], "vshl_n");
1844  case ARM::BI__builtin_neon_vshrn_n_v:
1845    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vshiftn, Ty),
1846                        Ops, "vshrn_n", 1, true);
1847  case ARM::BI__builtin_neon_vshr_n_v:
1848  case ARM::BI__builtin_neon_vshrq_n_v:
1849    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1850    Ops[1] = EmitNeonShiftVector(Ops[1], Ty, false);
1851    if (usgn)
1852      return Builder.CreateLShr(Ops[0], Ops[1], "vshr_n");
1853    else
1854      return Builder.CreateAShr(Ops[0], Ops[1], "vshr_n");
1855  case ARM::BI__builtin_neon_vsri_n_v:
1856  case ARM::BI__builtin_neon_vsriq_n_v:
1857    rightShift = true;
1858  case ARM::BI__builtin_neon_vsli_n_v:
1859  case ARM::BI__builtin_neon_vsliq_n_v:
1860    Ops[2] = EmitNeonShiftVector(Ops[2], Ty, rightShift);
1861    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vshiftins, Ty),
1862                        Ops, "vsli_n");
1863  case ARM::BI__builtin_neon_vsra_n_v:
1864  case ARM::BI__builtin_neon_vsraq_n_v:
1865    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1866    Ops[1] = Builder.CreateBitCast(Ops[1], Ty);
1867    Ops[2] = EmitNeonShiftVector(Ops[2], Ty, false);
1868    if (usgn)
1869      Ops[1] = Builder.CreateLShr(Ops[1], Ops[2], "vsra_n");
1870    else
1871      Ops[1] = Builder.CreateAShr(Ops[1], Ops[2], "vsra_n");
1872    return Builder.CreateAdd(Ops[0], Ops[1]);
1873  case ARM::BI__builtin_neon_vst1_v:
1874  case ARM::BI__builtin_neon_vst1q_v:
1875    Ops.push_back(GetPointeeAlignment(*this, E->getArg(0)));
1876    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vst1, Ty),
1877                        Ops, "");
1878  case ARM::BI__builtin_neon_vst1_lane_v:
1879  case ARM::BI__builtin_neon_vst1q_lane_v:
1880    Ops[1] = Builder.CreateBitCast(Ops[1], Ty);
1881    Ops[1] = Builder.CreateExtractElement(Ops[1], Ops[2]);
1882    Ty = llvm::PointerType::getUnqual(Ops[1]->getType());
1883    return Builder.CreateStore(Ops[1], Builder.CreateBitCast(Ops[0], Ty));
1884  case ARM::BI__builtin_neon_vst2_v:
1885  case ARM::BI__builtin_neon_vst2q_v:
1886    Ops.push_back(GetPointeeAlignment(*this, E->getArg(0)));
1887    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vst2, Ty),
1888                        Ops, "");
1889  case ARM::BI__builtin_neon_vst2_lane_v:
1890  case ARM::BI__builtin_neon_vst2q_lane_v:
1891    Ops.push_back(GetPointeeAlignment(*this, E->getArg(0)));
1892    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vst2lane, Ty),
1893                        Ops, "");
1894  case ARM::BI__builtin_neon_vst3_v:
1895  case ARM::BI__builtin_neon_vst3q_v:
1896    Ops.push_back(GetPointeeAlignment(*this, E->getArg(0)));
1897    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vst3, Ty),
1898                        Ops, "");
1899  case ARM::BI__builtin_neon_vst3_lane_v:
1900  case ARM::BI__builtin_neon_vst3q_lane_v:
1901    Ops.push_back(GetPointeeAlignment(*this, E->getArg(0)));
1902    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vst3lane, Ty),
1903                        Ops, "");
1904  case ARM::BI__builtin_neon_vst4_v:
1905  case ARM::BI__builtin_neon_vst4q_v:
1906    Ops.push_back(GetPointeeAlignment(*this, E->getArg(0)));
1907    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vst4, Ty),
1908                        Ops, "");
1909  case ARM::BI__builtin_neon_vst4_lane_v:
1910  case ARM::BI__builtin_neon_vst4q_lane_v:
1911    Ops.push_back(GetPointeeAlignment(*this, E->getArg(0)));
1912    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vst4lane, Ty),
1913                        Ops, "");
1914  case ARM::BI__builtin_neon_vsubhn_v:
1915    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vsubhn, Ty),
1916                        Ops, "vsubhn");
1917  case ARM::BI__builtin_neon_vtbl1_v:
1918    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vtbl1),
1919                        Ops, "vtbl1");
1920  case ARM::BI__builtin_neon_vtbl2_v:
1921    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vtbl2),
1922                        Ops, "vtbl2");
1923  case ARM::BI__builtin_neon_vtbl3_v:
1924    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vtbl3),
1925                        Ops, "vtbl3");
1926  case ARM::BI__builtin_neon_vtbl4_v:
1927    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vtbl4),
1928                        Ops, "vtbl4");
1929  case ARM::BI__builtin_neon_vtbx1_v:
1930    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vtbx1),
1931                        Ops, "vtbx1");
1932  case ARM::BI__builtin_neon_vtbx2_v:
1933    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vtbx2),
1934                        Ops, "vtbx2");
1935  case ARM::BI__builtin_neon_vtbx3_v:
1936    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vtbx3),
1937                        Ops, "vtbx3");
1938  case ARM::BI__builtin_neon_vtbx4_v:
1939    return EmitNeonCall(CGM.getIntrinsic(Intrinsic::arm_neon_vtbx4),
1940                        Ops, "vtbx4");
1941  case ARM::BI__builtin_neon_vtst_v:
1942  case ARM::BI__builtin_neon_vtstq_v: {
1943    Ops[0] = Builder.CreateBitCast(Ops[0], Ty);
1944    Ops[1] = Builder.CreateBitCast(Ops[1], Ty);
1945    Ops[0] = Builder.CreateAnd(Ops[0], Ops[1]);
1946    Ops[0] = Builder.CreateICmp(ICmpInst::ICMP_NE, Ops[0],
1947                                ConstantAggregateZero::get(Ty));
1948    return Builder.CreateSExt(Ops[0], Ty, "vtst");
1949  }
1950  case ARM::BI__builtin_neon_vtrn_v:
1951  case ARM::BI__builtin_neon_vtrnq_v: {
1952    Ops[0] = Builder.CreateBitCast(Ops[0], llvm::PointerType::getUnqual(Ty));
1953    Ops[1] = Builder.CreateBitCast(Ops[1], Ty);
1954    Ops[2] = Builder.CreateBitCast(Ops[2], Ty);
1955    Value *SV = 0;
1956
1957    for (unsigned vi = 0; vi != 2; ++vi) {
1958      SmallVector<Constant*, 16> Indices;
1959      for (unsigned i = 0, e = VTy->getNumElements(); i != e; i += 2) {
1960        Indices.push_back(ConstantInt::get(Int32Ty, i+vi));
1961        Indices.push_back(ConstantInt::get(Int32Ty, i+e+vi));
1962      }
1963      Value *Addr = Builder.CreateConstInBoundsGEP1_32(Ops[0], vi);
1964      SV = llvm::ConstantVector::get(Indices);
1965      SV = Builder.CreateShuffleVector(Ops[1], Ops[2], SV, "vtrn");
1966      SV = Builder.CreateStore(SV, Addr);
1967    }
1968    return SV;
1969  }
1970  case ARM::BI__builtin_neon_vuzp_v:
1971  case ARM::BI__builtin_neon_vuzpq_v: {
1972    Ops[0] = Builder.CreateBitCast(Ops[0], llvm::PointerType::getUnqual(Ty));
1973    Ops[1] = Builder.CreateBitCast(Ops[1], Ty);
1974    Ops[2] = Builder.CreateBitCast(Ops[2], Ty);
1975    Value *SV = 0;
1976
1977    for (unsigned vi = 0; vi != 2; ++vi) {
1978      SmallVector<Constant*, 16> Indices;
1979      for (unsigned i = 0, e = VTy->getNumElements(); i != e; ++i)
1980        Indices.push_back(ConstantInt::get(Int32Ty, 2*i+vi));
1981
1982      Value *Addr = Builder.CreateConstInBoundsGEP1_32(Ops[0], vi);
1983      SV = llvm::ConstantVector::get(Indices);
1984      SV = Builder.CreateShuffleVector(Ops[1], Ops[2], SV, "vuzp");
1985      SV = Builder.CreateStore(SV, Addr);
1986    }
1987    return SV;
1988  }
1989  case ARM::BI__builtin_neon_vzip_v:
1990  case ARM::BI__builtin_neon_vzipq_v: {
1991    Ops[0] = Builder.CreateBitCast(Ops[0], llvm::PointerType::getUnqual(Ty));
1992    Ops[1] = Builder.CreateBitCast(Ops[1], Ty);
1993    Ops[2] = Builder.CreateBitCast(Ops[2], Ty);
1994    Value *SV = 0;
1995
1996    for (unsigned vi = 0; vi != 2; ++vi) {
1997      SmallVector<Constant*, 16> Indices;
1998      for (unsigned i = 0, e = VTy->getNumElements(); i != e; i += 2) {
1999        Indices.push_back(ConstantInt::get(Int32Ty, (i + vi*e) >> 1));
2000        Indices.push_back(ConstantInt::get(Int32Ty, ((i + vi*e) >> 1)+e));
2001      }
2002      Value *Addr = Builder.CreateConstInBoundsGEP1_32(Ops[0], vi);
2003      SV = llvm::ConstantVector::get(Indices);
2004      SV = Builder.CreateShuffleVector(Ops[1], Ops[2], SV, "vzip");
2005      SV = Builder.CreateStore(SV, Addr);
2006    }
2007    return SV;
2008  }
2009  }
2010}
2011
2012llvm::Value *CodeGenFunction::
2013BuildVector(const SmallVectorImpl<llvm::Value*> &Ops) {
2014  assert((Ops.size() & (Ops.size() - 1)) == 0 &&
2015         "Not a power-of-two sized vector!");
2016  bool AllConstants = true;
2017  for (unsigned i = 0, e = Ops.size(); i != e && AllConstants; ++i)
2018    AllConstants &= isa<Constant>(Ops[i]);
2019
2020  // If this is a constant vector, create a ConstantVector.
2021  if (AllConstants) {
2022    std::vector<llvm::Constant*> CstOps;
2023    for (unsigned i = 0, e = Ops.size(); i != e; ++i)
2024      CstOps.push_back(cast<Constant>(Ops[i]));
2025    return llvm::ConstantVector::get(CstOps);
2026  }
2027
2028  // Otherwise, insertelement the values to build the vector.
2029  Value *Result =
2030    llvm::UndefValue::get(llvm::VectorType::get(Ops[0]->getType(), Ops.size()));
2031
2032  for (unsigned i = 0, e = Ops.size(); i != e; ++i)
2033    Result = Builder.CreateInsertElement(Result, Ops[i],
2034               llvm::ConstantInt::get(llvm::Type::getInt32Ty(getLLVMContext()), i));
2035
2036  return Result;
2037}
2038
2039Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned BuiltinID,
2040                                           const CallExpr *E) {
2041  SmallVector<Value*, 4> Ops;
2042
2043  // Find out if any arguments are required to be integer constant expressions.
2044  unsigned ICEArguments = 0;
2045  ASTContext::GetBuiltinTypeError Error;
2046  getContext().GetBuiltinType(BuiltinID, Error, &ICEArguments);
2047  assert(Error == ASTContext::GE_None && "Should not codegen an error");
2048
2049  for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) {
2050    // If this is a normal argument, just emit it as a scalar.
2051    if ((ICEArguments & (1 << i)) == 0) {
2052      Ops.push_back(EmitScalarExpr(E->getArg(i)));
2053      continue;
2054    }
2055
2056    // If this is required to be a constant, constant fold it so that we know
2057    // that the generated intrinsic gets a ConstantInt.
2058    llvm::APSInt Result;
2059    bool IsConst = E->getArg(i)->isIntegerConstantExpr(Result, getContext());
2060    assert(IsConst && "Constant arg isn't actually constant?"); (void)IsConst;
2061    Ops.push_back(llvm::ConstantInt::get(getLLVMContext(), Result));
2062  }
2063
2064  switch (BuiltinID) {
2065  default: return 0;
2066  case X86::BI__builtin_ia32_pslldi128:
2067  case X86::BI__builtin_ia32_psllqi128:
2068  case X86::BI__builtin_ia32_psllwi128:
2069  case X86::BI__builtin_ia32_psradi128:
2070  case X86::BI__builtin_ia32_psrawi128:
2071  case X86::BI__builtin_ia32_psrldi128:
2072  case X86::BI__builtin_ia32_psrlqi128:
2073  case X86::BI__builtin_ia32_psrlwi128: {
2074    Ops[1] = Builder.CreateZExt(Ops[1], Int64Ty, "zext");
2075    llvm::Type *Ty = llvm::VectorType::get(Int64Ty, 2);
2076    llvm::Value *Zero = llvm::ConstantInt::get(Int32Ty, 0);
2077    Ops[1] = Builder.CreateInsertElement(llvm::UndefValue::get(Ty),
2078                                         Ops[1], Zero, "insert");
2079    Ops[1] = Builder.CreateBitCast(Ops[1], Ops[0]->getType(), "bitcast");
2080    const char *name = 0;
2081    Intrinsic::ID ID = Intrinsic::not_intrinsic;
2082
2083    switch (BuiltinID) {
2084    default: llvm_unreachable("Unsupported shift intrinsic!");
2085    case X86::BI__builtin_ia32_pslldi128:
2086      name = "pslldi";
2087      ID = Intrinsic::x86_sse2_psll_d;
2088      break;
2089    case X86::BI__builtin_ia32_psllqi128:
2090      name = "psllqi";
2091      ID = Intrinsic::x86_sse2_psll_q;
2092      break;
2093    case X86::BI__builtin_ia32_psllwi128:
2094      name = "psllwi";
2095      ID = Intrinsic::x86_sse2_psll_w;
2096      break;
2097    case X86::BI__builtin_ia32_psradi128:
2098      name = "psradi";
2099      ID = Intrinsic::x86_sse2_psra_d;
2100      break;
2101    case X86::BI__builtin_ia32_psrawi128:
2102      name = "psrawi";
2103      ID = Intrinsic::x86_sse2_psra_w;
2104      break;
2105    case X86::BI__builtin_ia32_psrldi128:
2106      name = "psrldi";
2107      ID = Intrinsic::x86_sse2_psrl_d;
2108      break;
2109    case X86::BI__builtin_ia32_psrlqi128:
2110      name = "psrlqi";
2111      ID = Intrinsic::x86_sse2_psrl_q;
2112      break;
2113    case X86::BI__builtin_ia32_psrlwi128:
2114      name = "psrlwi";
2115      ID = Intrinsic::x86_sse2_psrl_w;
2116      break;
2117    }
2118    llvm::Function *F = CGM.getIntrinsic(ID);
2119    return Builder.CreateCall(F, Ops, name);
2120  }
2121  case X86::BI__builtin_ia32_vec_init_v8qi:
2122  case X86::BI__builtin_ia32_vec_init_v4hi:
2123  case X86::BI__builtin_ia32_vec_init_v2si:
2124    return Builder.CreateBitCast(BuildVector(Ops),
2125                                 llvm::Type::getX86_MMXTy(getLLVMContext()));
2126  case X86::BI__builtin_ia32_vec_ext_v2si:
2127    return Builder.CreateExtractElement(Ops[0],
2128                                  llvm::ConstantInt::get(Ops[1]->getType(), 0));
2129  case X86::BI__builtin_ia32_pslldi:
2130  case X86::BI__builtin_ia32_psllqi:
2131  case X86::BI__builtin_ia32_psllwi:
2132  case X86::BI__builtin_ia32_psradi:
2133  case X86::BI__builtin_ia32_psrawi:
2134  case X86::BI__builtin_ia32_psrldi:
2135  case X86::BI__builtin_ia32_psrlqi:
2136  case X86::BI__builtin_ia32_psrlwi: {
2137    Ops[1] = Builder.CreateZExt(Ops[1], Int64Ty, "zext");
2138    llvm::Type *Ty = llvm::VectorType::get(Int64Ty, 1);
2139    Ops[1] = Builder.CreateBitCast(Ops[1], Ty, "bitcast");
2140    const char *name = 0;
2141    Intrinsic::ID ID = Intrinsic::not_intrinsic;
2142
2143    switch (BuiltinID) {
2144    default: llvm_unreachable("Unsupported shift intrinsic!");
2145    case X86::BI__builtin_ia32_pslldi:
2146      name = "pslldi";
2147      ID = Intrinsic::x86_mmx_psll_d;
2148      break;
2149    case X86::BI__builtin_ia32_psllqi:
2150      name = "psllqi";
2151      ID = Intrinsic::x86_mmx_psll_q;
2152      break;
2153    case X86::BI__builtin_ia32_psllwi:
2154      name = "psllwi";
2155      ID = Intrinsic::x86_mmx_psll_w;
2156      break;
2157    case X86::BI__builtin_ia32_psradi:
2158      name = "psradi";
2159      ID = Intrinsic::x86_mmx_psra_d;
2160      break;
2161    case X86::BI__builtin_ia32_psrawi:
2162      name = "psrawi";
2163      ID = Intrinsic::x86_mmx_psra_w;
2164      break;
2165    case X86::BI__builtin_ia32_psrldi:
2166      name = "psrldi";
2167      ID = Intrinsic::x86_mmx_psrl_d;
2168      break;
2169    case X86::BI__builtin_ia32_psrlqi:
2170      name = "psrlqi";
2171      ID = Intrinsic::x86_mmx_psrl_q;
2172      break;
2173    case X86::BI__builtin_ia32_psrlwi:
2174      name = "psrlwi";
2175      ID = Intrinsic::x86_mmx_psrl_w;
2176      break;
2177    }
2178    llvm::Function *F = CGM.getIntrinsic(ID);
2179    return Builder.CreateCall(F, Ops, name);
2180  }
2181  case X86::BI__builtin_ia32_cmpps: {
2182    llvm::Function *F = CGM.getIntrinsic(Intrinsic::x86_sse_cmp_ps);
2183    return Builder.CreateCall(F, Ops, "cmpps");
2184  }
2185  case X86::BI__builtin_ia32_cmpss: {
2186    llvm::Function *F = CGM.getIntrinsic(Intrinsic::x86_sse_cmp_ss);
2187    return Builder.CreateCall(F, Ops, "cmpss");
2188  }
2189  case X86::BI__builtin_ia32_ldmxcsr: {
2190    llvm::Type *PtrTy = Int8PtrTy;
2191    Value *One = llvm::ConstantInt::get(Int32Ty, 1);
2192    Value *Tmp = Builder.CreateAlloca(Int32Ty, One);
2193    Builder.CreateStore(Ops[0], Tmp);
2194    return Builder.CreateCall(CGM.getIntrinsic(Intrinsic::x86_sse_ldmxcsr),
2195                              Builder.CreateBitCast(Tmp, PtrTy));
2196  }
2197  case X86::BI__builtin_ia32_stmxcsr: {
2198    llvm::Type *PtrTy = Int8PtrTy;
2199    Value *One = llvm::ConstantInt::get(Int32Ty, 1);
2200    Value *Tmp = Builder.CreateAlloca(Int32Ty, One);
2201    Builder.CreateCall(CGM.getIntrinsic(Intrinsic::x86_sse_stmxcsr),
2202                       Builder.CreateBitCast(Tmp, PtrTy));
2203    return Builder.CreateLoad(Tmp, "stmxcsr");
2204  }
2205  case X86::BI__builtin_ia32_cmppd: {
2206    llvm::Function *F = CGM.getIntrinsic(Intrinsic::x86_sse2_cmp_pd);
2207    return Builder.CreateCall(F, Ops, "cmppd");
2208  }
2209  case X86::BI__builtin_ia32_cmpsd: {
2210    llvm::Function *F = CGM.getIntrinsic(Intrinsic::x86_sse2_cmp_sd);
2211    return Builder.CreateCall(F, Ops, "cmpsd");
2212  }
2213  case X86::BI__builtin_ia32_storehps:
2214  case X86::BI__builtin_ia32_storelps: {
2215    llvm::Type *PtrTy = llvm::PointerType::getUnqual(Int64Ty);
2216    llvm::Type *VecTy = llvm::VectorType::get(Int64Ty, 2);
2217
2218    // cast val v2i64
2219    Ops[1] = Builder.CreateBitCast(Ops[1], VecTy, "cast");
2220
2221    // extract (0, 1)
2222    unsigned Index = BuiltinID == X86::BI__builtin_ia32_storelps ? 0 : 1;
2223    llvm::Value *Idx = llvm::ConstantInt::get(Int32Ty, Index);
2224    Ops[1] = Builder.CreateExtractElement(Ops[1], Idx, "extract");
2225
2226    // cast pointer to i64 & store
2227    Ops[0] = Builder.CreateBitCast(Ops[0], PtrTy);
2228    return Builder.CreateStore(Ops[1], Ops[0]);
2229  }
2230  case X86::BI__builtin_ia32_palignr: {
2231    unsigned shiftVal = cast<llvm::ConstantInt>(Ops[2])->getZExtValue();
2232
2233    // If palignr is shifting the pair of input vectors less than 9 bytes,
2234    // emit a shuffle instruction.
2235    if (shiftVal <= 8) {
2236      SmallVector<llvm::Constant*, 8> Indices;
2237      for (unsigned i = 0; i != 8; ++i)
2238        Indices.push_back(llvm::ConstantInt::get(Int32Ty, shiftVal + i));
2239
2240      Value* SV = llvm::ConstantVector::get(Indices);
2241      return Builder.CreateShuffleVector(Ops[1], Ops[0], SV, "palignr");
2242    }
2243
2244    // If palignr is shifting the pair of input vectors more than 8 but less
2245    // than 16 bytes, emit a logical right shift of the destination.
2246    if (shiftVal < 16) {
2247      // MMX has these as 1 x i64 vectors for some odd optimization reasons.
2248      llvm::Type *VecTy = llvm::VectorType::get(Int64Ty, 1);
2249
2250      Ops[0] = Builder.CreateBitCast(Ops[0], VecTy, "cast");
2251      Ops[1] = llvm::ConstantInt::get(VecTy, (shiftVal-8) * 8);
2252
2253      // create i32 constant
2254      llvm::Function *F = CGM.getIntrinsic(Intrinsic::x86_mmx_psrl_q);
2255      return Builder.CreateCall(F, makeArrayRef(&Ops[0], 2), "palignr");
2256    }
2257
2258    // If palignr is shifting the pair of vectors more than 16 bytes, emit zero.
2259    return llvm::Constant::getNullValue(ConvertType(E->getType()));
2260  }
2261  case X86::BI__builtin_ia32_palignr128: {
2262    unsigned shiftVal = cast<llvm::ConstantInt>(Ops[2])->getZExtValue();
2263
2264    // If palignr is shifting the pair of input vectors less than 17 bytes,
2265    // emit a shuffle instruction.
2266    if (shiftVal <= 16) {
2267      SmallVector<llvm::Constant*, 16> Indices;
2268      for (unsigned i = 0; i != 16; ++i)
2269        Indices.push_back(llvm::ConstantInt::get(Int32Ty, shiftVal + i));
2270
2271      Value* SV = llvm::ConstantVector::get(Indices);
2272      return Builder.CreateShuffleVector(Ops[1], Ops[0], SV, "palignr");
2273    }
2274
2275    // If palignr is shifting the pair of input vectors more than 16 but less
2276    // than 32 bytes, emit a logical right shift of the destination.
2277    if (shiftVal < 32) {
2278      llvm::Type *VecTy = llvm::VectorType::get(Int64Ty, 2);
2279
2280      Ops[0] = Builder.CreateBitCast(Ops[0], VecTy, "cast");
2281      Ops[1] = llvm::ConstantInt::get(Int32Ty, (shiftVal-16) * 8);
2282
2283      // create i32 constant
2284      llvm::Function *F = CGM.getIntrinsic(Intrinsic::x86_sse2_psrl_dq);
2285      return Builder.CreateCall(F, makeArrayRef(&Ops[0], 2), "palignr");
2286    }
2287
2288    // If palignr is shifting the pair of vectors more than 32 bytes, emit zero.
2289    return llvm::Constant::getNullValue(ConvertType(E->getType()));
2290  }
2291  case X86::BI__builtin_ia32_movntps:
2292  case X86::BI__builtin_ia32_movntpd:
2293  case X86::BI__builtin_ia32_movntdq:
2294  case X86::BI__builtin_ia32_movnti: {
2295    llvm::MDNode *Node = llvm::MDNode::get(getLLVMContext(),
2296                                           Builder.getInt32(1));
2297
2298    // Convert the type of the pointer to a pointer to the stored type.
2299    Value *BC = Builder.CreateBitCast(Ops[0],
2300                                llvm::PointerType::getUnqual(Ops[1]->getType()),
2301                                      "cast");
2302    StoreInst *SI = Builder.CreateStore(Ops[1], BC);
2303    SI->setMetadata(CGM.getModule().getMDKindID("nontemporal"), Node);
2304    SI->setAlignment(16);
2305    return SI;
2306  }
2307  // 3DNow!
2308  case X86::BI__builtin_ia32_pavgusb:
2309  case X86::BI__builtin_ia32_pf2id:
2310  case X86::BI__builtin_ia32_pfacc:
2311  case X86::BI__builtin_ia32_pfadd:
2312  case X86::BI__builtin_ia32_pfcmpeq:
2313  case X86::BI__builtin_ia32_pfcmpge:
2314  case X86::BI__builtin_ia32_pfcmpgt:
2315  case X86::BI__builtin_ia32_pfmax:
2316  case X86::BI__builtin_ia32_pfmin:
2317  case X86::BI__builtin_ia32_pfmul:
2318  case X86::BI__builtin_ia32_pfrcp:
2319  case X86::BI__builtin_ia32_pfrcpit1:
2320  case X86::BI__builtin_ia32_pfrcpit2:
2321  case X86::BI__builtin_ia32_pfrsqrt:
2322  case X86::BI__builtin_ia32_pfrsqit1:
2323  case X86::BI__builtin_ia32_pfrsqrtit1:
2324  case X86::BI__builtin_ia32_pfsub:
2325  case X86::BI__builtin_ia32_pfsubr:
2326  case X86::BI__builtin_ia32_pi2fd:
2327  case X86::BI__builtin_ia32_pmulhrw:
2328  case X86::BI__builtin_ia32_pf2iw:
2329  case X86::BI__builtin_ia32_pfnacc:
2330  case X86::BI__builtin_ia32_pfpnacc:
2331  case X86::BI__builtin_ia32_pi2fw:
2332  case X86::BI__builtin_ia32_pswapdsf:
2333  case X86::BI__builtin_ia32_pswapdsi: {
2334    const char *name = 0;
2335    Intrinsic::ID ID = Intrinsic::not_intrinsic;
2336    switch(BuiltinID) {
2337    case X86::BI__builtin_ia32_pavgusb:
2338      name = "pavgusb";
2339      ID = Intrinsic::x86_3dnow_pavgusb;
2340      break;
2341    case X86::BI__builtin_ia32_pf2id:
2342      name = "pf2id";
2343      ID = Intrinsic::x86_3dnow_pf2id;
2344      break;
2345    case X86::BI__builtin_ia32_pfacc:
2346      name = "pfacc";
2347      ID = Intrinsic::x86_3dnow_pfacc;
2348      break;
2349    case X86::BI__builtin_ia32_pfadd:
2350      name = "pfadd";
2351      ID = Intrinsic::x86_3dnow_pfadd;
2352      break;
2353    case X86::BI__builtin_ia32_pfcmpeq:
2354      name = "pfcmpeq";
2355      ID = Intrinsic::x86_3dnow_pfcmpeq;
2356      break;
2357    case X86::BI__builtin_ia32_pfcmpge:
2358      name = "pfcmpge";
2359      ID = Intrinsic::x86_3dnow_pfcmpge;
2360      break;
2361    case X86::BI__builtin_ia32_pfcmpgt:
2362      name = "pfcmpgt";
2363      ID = Intrinsic::x86_3dnow_pfcmpgt;
2364      break;
2365    case X86::BI__builtin_ia32_pfmax:
2366      name = "pfmax";
2367      ID = Intrinsic::x86_3dnow_pfmax;
2368      break;
2369    case X86::BI__builtin_ia32_pfmin:
2370      name = "pfmin";
2371      ID = Intrinsic::x86_3dnow_pfmin;
2372      break;
2373    case X86::BI__builtin_ia32_pfmul:
2374      name = "pfmul";
2375      ID = Intrinsic::x86_3dnow_pfmul;
2376      break;
2377    case X86::BI__builtin_ia32_pfrcp:
2378      name = "pfrcp";
2379      ID = Intrinsic::x86_3dnow_pfrcp;
2380      break;
2381    case X86::BI__builtin_ia32_pfrcpit1:
2382      name = "pfrcpit1";
2383      ID = Intrinsic::x86_3dnow_pfrcpit1;
2384      break;
2385    case X86::BI__builtin_ia32_pfrcpit2:
2386      name = "pfrcpit2";
2387      ID = Intrinsic::x86_3dnow_pfrcpit2;
2388      break;
2389    case X86::BI__builtin_ia32_pfrsqrt:
2390      name = "pfrsqrt";
2391      ID = Intrinsic::x86_3dnow_pfrsqrt;
2392      break;
2393    case X86::BI__builtin_ia32_pfrsqit1:
2394    case X86::BI__builtin_ia32_pfrsqrtit1:
2395      name = "pfrsqit1";
2396      ID = Intrinsic::x86_3dnow_pfrsqit1;
2397      break;
2398    case X86::BI__builtin_ia32_pfsub:
2399      name = "pfsub";
2400      ID = Intrinsic::x86_3dnow_pfsub;
2401      break;
2402    case X86::BI__builtin_ia32_pfsubr:
2403      name = "pfsubr";
2404      ID = Intrinsic::x86_3dnow_pfsubr;
2405      break;
2406    case X86::BI__builtin_ia32_pi2fd:
2407      name = "pi2fd";
2408      ID = Intrinsic::x86_3dnow_pi2fd;
2409      break;
2410    case X86::BI__builtin_ia32_pmulhrw:
2411      name = "pmulhrw";
2412      ID = Intrinsic::x86_3dnow_pmulhrw;
2413      break;
2414    case X86::BI__builtin_ia32_pf2iw:
2415      name = "pf2iw";
2416      ID = Intrinsic::x86_3dnowa_pf2iw;
2417      break;
2418    case X86::BI__builtin_ia32_pfnacc:
2419      name = "pfnacc";
2420      ID = Intrinsic::x86_3dnowa_pfnacc;
2421      break;
2422    case X86::BI__builtin_ia32_pfpnacc:
2423      name = "pfpnacc";
2424      ID = Intrinsic::x86_3dnowa_pfpnacc;
2425      break;
2426    case X86::BI__builtin_ia32_pi2fw:
2427      name = "pi2fw";
2428      ID = Intrinsic::x86_3dnowa_pi2fw;
2429      break;
2430    case X86::BI__builtin_ia32_pswapdsf:
2431    case X86::BI__builtin_ia32_pswapdsi:
2432      name = "pswapd";
2433      ID = Intrinsic::x86_3dnowa_pswapd;
2434      break;
2435    }
2436    llvm::Function *F = CGM.getIntrinsic(ID);
2437    return Builder.CreateCall(F, Ops, name);
2438  }
2439  }
2440}
2441
2442
2443Value *CodeGenFunction::EmitHexagonBuiltinExpr(unsigned BuiltinID,
2444                                             const CallExpr *E) {
2445  llvm::SmallVector<Value*, 4> Ops;
2446
2447  for (unsigned i = 0, e = E->getNumArgs(); i != e; i++)
2448    Ops.push_back(EmitScalarExpr(E->getArg(i)));
2449
2450  Intrinsic::ID ID = Intrinsic::not_intrinsic;
2451
2452  switch (BuiltinID) {
2453  default: return 0;
2454
2455  case Hexagon::BI__builtin_HEXAGON_C2_cmpeq:
2456    ID = Intrinsic::hexagon_C2_cmpeq; break;
2457
2458  case Hexagon::BI__builtin_HEXAGON_C2_cmpgt:
2459    ID = Intrinsic::hexagon_C2_cmpgt; break;
2460
2461  case Hexagon::BI__builtin_HEXAGON_C2_cmpgtu:
2462    ID = Intrinsic::hexagon_C2_cmpgtu; break;
2463
2464  case Hexagon::BI__builtin_HEXAGON_C2_cmpeqp:
2465    ID = Intrinsic::hexagon_C2_cmpeqp; break;
2466
2467  case Hexagon::BI__builtin_HEXAGON_C2_cmpgtp:
2468    ID = Intrinsic::hexagon_C2_cmpgtp; break;
2469
2470  case Hexagon::BI__builtin_HEXAGON_C2_cmpgtup:
2471    ID = Intrinsic::hexagon_C2_cmpgtup; break;
2472
2473  case Hexagon::BI__builtin_HEXAGON_C2_bitsset:
2474    ID = Intrinsic::hexagon_C2_bitsset; break;
2475
2476  case Hexagon::BI__builtin_HEXAGON_C2_bitsclr:
2477    ID = Intrinsic::hexagon_C2_bitsclr; break;
2478
2479  case Hexagon::BI__builtin_HEXAGON_C2_cmpeqi:
2480    ID = Intrinsic::hexagon_C2_cmpeqi; break;
2481
2482  case Hexagon::BI__builtin_HEXAGON_C2_cmpgti:
2483    ID = Intrinsic::hexagon_C2_cmpgti; break;
2484
2485  case Hexagon::BI__builtin_HEXAGON_C2_cmpgtui:
2486    ID = Intrinsic::hexagon_C2_cmpgtui; break;
2487
2488  case Hexagon::BI__builtin_HEXAGON_C2_cmpgei:
2489    ID = Intrinsic::hexagon_C2_cmpgei; break;
2490
2491  case Hexagon::BI__builtin_HEXAGON_C2_cmpgeui:
2492    ID = Intrinsic::hexagon_C2_cmpgeui; break;
2493
2494  case Hexagon::BI__builtin_HEXAGON_C2_cmplt:
2495    ID = Intrinsic::hexagon_C2_cmplt; break;
2496
2497  case Hexagon::BI__builtin_HEXAGON_C2_cmpltu:
2498    ID = Intrinsic::hexagon_C2_cmpltu; break;
2499
2500  case Hexagon::BI__builtin_HEXAGON_C2_bitsclri:
2501    ID = Intrinsic::hexagon_C2_bitsclri; break;
2502
2503  case Hexagon::BI__builtin_HEXAGON_C2_and:
2504    ID = Intrinsic::hexagon_C2_and; break;
2505
2506  case Hexagon::BI__builtin_HEXAGON_C2_or:
2507    ID = Intrinsic::hexagon_C2_or; break;
2508
2509  case Hexagon::BI__builtin_HEXAGON_C2_xor:
2510    ID = Intrinsic::hexagon_C2_xor; break;
2511
2512  case Hexagon::BI__builtin_HEXAGON_C2_andn:
2513    ID = Intrinsic::hexagon_C2_andn; break;
2514
2515  case Hexagon::BI__builtin_HEXAGON_C2_not:
2516    ID = Intrinsic::hexagon_C2_not; break;
2517
2518  case Hexagon::BI__builtin_HEXAGON_C2_orn:
2519    ID = Intrinsic::hexagon_C2_orn; break;
2520
2521  case Hexagon::BI__builtin_HEXAGON_C2_pxfer_map:
2522    ID = Intrinsic::hexagon_C2_pxfer_map; break;
2523
2524  case Hexagon::BI__builtin_HEXAGON_C2_any8:
2525    ID = Intrinsic::hexagon_C2_any8; break;
2526
2527  case Hexagon::BI__builtin_HEXAGON_C2_all8:
2528    ID = Intrinsic::hexagon_C2_all8; break;
2529
2530  case Hexagon::BI__builtin_HEXAGON_C2_vitpack:
2531    ID = Intrinsic::hexagon_C2_vitpack; break;
2532
2533  case Hexagon::BI__builtin_HEXAGON_C2_mux:
2534    ID = Intrinsic::hexagon_C2_mux; break;
2535
2536  case Hexagon::BI__builtin_HEXAGON_C2_muxii:
2537    ID = Intrinsic::hexagon_C2_muxii; break;
2538
2539  case Hexagon::BI__builtin_HEXAGON_C2_muxir:
2540    ID = Intrinsic::hexagon_C2_muxir; break;
2541
2542  case Hexagon::BI__builtin_HEXAGON_C2_muxri:
2543    ID = Intrinsic::hexagon_C2_muxri; break;
2544
2545  case Hexagon::BI__builtin_HEXAGON_C2_vmux:
2546    ID = Intrinsic::hexagon_C2_vmux; break;
2547
2548  case Hexagon::BI__builtin_HEXAGON_C2_mask:
2549    ID = Intrinsic::hexagon_C2_mask; break;
2550
2551  case Hexagon::BI__builtin_HEXAGON_A2_vcmpbeq:
2552    ID = Intrinsic::hexagon_A2_vcmpbeq; break;
2553
2554  case Hexagon::BI__builtin_HEXAGON_A2_vcmpbgtu:
2555    ID = Intrinsic::hexagon_A2_vcmpbgtu; break;
2556
2557  case Hexagon::BI__builtin_HEXAGON_A2_vcmpheq:
2558    ID = Intrinsic::hexagon_A2_vcmpheq; break;
2559
2560  case Hexagon::BI__builtin_HEXAGON_A2_vcmphgt:
2561    ID = Intrinsic::hexagon_A2_vcmphgt; break;
2562
2563  case Hexagon::BI__builtin_HEXAGON_A2_vcmphgtu:
2564    ID = Intrinsic::hexagon_A2_vcmphgtu; break;
2565
2566  case Hexagon::BI__builtin_HEXAGON_A2_vcmpweq:
2567    ID = Intrinsic::hexagon_A2_vcmpweq; break;
2568
2569  case Hexagon::BI__builtin_HEXAGON_A2_vcmpwgt:
2570    ID = Intrinsic::hexagon_A2_vcmpwgt; break;
2571
2572  case Hexagon::BI__builtin_HEXAGON_A2_vcmpwgtu:
2573    ID = Intrinsic::hexagon_A2_vcmpwgtu; break;
2574
2575  case Hexagon::BI__builtin_HEXAGON_C2_tfrpr:
2576    ID = Intrinsic::hexagon_C2_tfrpr; break;
2577
2578  case Hexagon::BI__builtin_HEXAGON_C2_tfrrp:
2579    ID = Intrinsic::hexagon_C2_tfrrp; break;
2580
2581  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_hh_s0:
2582    ID = Intrinsic::hexagon_M2_mpy_acc_hh_s0; break;
2583
2584  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_hh_s1:
2585    ID = Intrinsic::hexagon_M2_mpy_acc_hh_s1; break;
2586
2587  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_hl_s0:
2588    ID = Intrinsic::hexagon_M2_mpy_acc_hl_s0; break;
2589
2590  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_hl_s1:
2591    ID = Intrinsic::hexagon_M2_mpy_acc_hl_s1; break;
2592
2593  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_lh_s0:
2594    ID = Intrinsic::hexagon_M2_mpy_acc_lh_s0; break;
2595
2596  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_lh_s1:
2597    ID = Intrinsic::hexagon_M2_mpy_acc_lh_s1; break;
2598
2599  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_ll_s0:
2600    ID = Intrinsic::hexagon_M2_mpy_acc_ll_s0; break;
2601
2602  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_ll_s1:
2603    ID = Intrinsic::hexagon_M2_mpy_acc_ll_s1; break;
2604
2605  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_hh_s0:
2606    ID = Intrinsic::hexagon_M2_mpy_nac_hh_s0; break;
2607
2608  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_hh_s1:
2609    ID = Intrinsic::hexagon_M2_mpy_nac_hh_s1; break;
2610
2611  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_hl_s0:
2612    ID = Intrinsic::hexagon_M2_mpy_nac_hl_s0; break;
2613
2614  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_hl_s1:
2615    ID = Intrinsic::hexagon_M2_mpy_nac_hl_s1; break;
2616
2617  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_lh_s0:
2618    ID = Intrinsic::hexagon_M2_mpy_nac_lh_s0; break;
2619
2620  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_lh_s1:
2621    ID = Intrinsic::hexagon_M2_mpy_nac_lh_s1; break;
2622
2623  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_ll_s0:
2624    ID = Intrinsic::hexagon_M2_mpy_nac_ll_s0; break;
2625
2626  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_ll_s1:
2627    ID = Intrinsic::hexagon_M2_mpy_nac_ll_s1; break;
2628
2629  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_sat_hh_s0:
2630    ID = Intrinsic::hexagon_M2_mpy_acc_sat_hh_s0; break;
2631
2632  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_sat_hh_s1:
2633    ID = Intrinsic::hexagon_M2_mpy_acc_sat_hh_s1; break;
2634
2635  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_sat_hl_s0:
2636    ID = Intrinsic::hexagon_M2_mpy_acc_sat_hl_s0; break;
2637
2638  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_sat_hl_s1:
2639    ID = Intrinsic::hexagon_M2_mpy_acc_sat_hl_s1; break;
2640
2641  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_sat_lh_s0:
2642    ID = Intrinsic::hexagon_M2_mpy_acc_sat_lh_s0; break;
2643
2644  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_sat_lh_s1:
2645    ID = Intrinsic::hexagon_M2_mpy_acc_sat_lh_s1; break;
2646
2647  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_sat_ll_s0:
2648    ID = Intrinsic::hexagon_M2_mpy_acc_sat_ll_s0; break;
2649
2650  case Hexagon::BI__builtin_HEXAGON_M2_mpy_acc_sat_ll_s1:
2651    ID = Intrinsic::hexagon_M2_mpy_acc_sat_ll_s1; break;
2652
2653  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_sat_hh_s0:
2654    ID = Intrinsic::hexagon_M2_mpy_nac_sat_hh_s0; break;
2655
2656  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_sat_hh_s1:
2657    ID = Intrinsic::hexagon_M2_mpy_nac_sat_hh_s1; break;
2658
2659  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_sat_hl_s0:
2660    ID = Intrinsic::hexagon_M2_mpy_nac_sat_hl_s0; break;
2661
2662  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_sat_hl_s1:
2663    ID = Intrinsic::hexagon_M2_mpy_nac_sat_hl_s1; break;
2664
2665  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_sat_lh_s0:
2666    ID = Intrinsic::hexagon_M2_mpy_nac_sat_lh_s0; break;
2667
2668  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_sat_lh_s1:
2669    ID = Intrinsic::hexagon_M2_mpy_nac_sat_lh_s1; break;
2670
2671  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_sat_ll_s0:
2672    ID = Intrinsic::hexagon_M2_mpy_nac_sat_ll_s0; break;
2673
2674  case Hexagon::BI__builtin_HEXAGON_M2_mpy_nac_sat_ll_s1:
2675    ID = Intrinsic::hexagon_M2_mpy_nac_sat_ll_s1; break;
2676
2677  case Hexagon::BI__builtin_HEXAGON_M2_mpy_hh_s0:
2678    ID = Intrinsic::hexagon_M2_mpy_hh_s0; break;
2679
2680  case Hexagon::BI__builtin_HEXAGON_M2_mpy_hh_s1:
2681    ID = Intrinsic::hexagon_M2_mpy_hh_s1; break;
2682
2683  case Hexagon::BI__builtin_HEXAGON_M2_mpy_hl_s0:
2684    ID = Intrinsic::hexagon_M2_mpy_hl_s0; break;
2685
2686  case Hexagon::BI__builtin_HEXAGON_M2_mpy_hl_s1:
2687    ID = Intrinsic::hexagon_M2_mpy_hl_s1; break;
2688
2689  case Hexagon::BI__builtin_HEXAGON_M2_mpy_lh_s0:
2690    ID = Intrinsic::hexagon_M2_mpy_lh_s0; break;
2691
2692  case Hexagon::BI__builtin_HEXAGON_M2_mpy_lh_s1:
2693    ID = Intrinsic::hexagon_M2_mpy_lh_s1; break;
2694
2695  case Hexagon::BI__builtin_HEXAGON_M2_mpy_ll_s0:
2696    ID = Intrinsic::hexagon_M2_mpy_ll_s0; break;
2697
2698  case Hexagon::BI__builtin_HEXAGON_M2_mpy_ll_s1:
2699    ID = Intrinsic::hexagon_M2_mpy_ll_s1; break;
2700
2701  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_hh_s0:
2702    ID = Intrinsic::hexagon_M2_mpy_sat_hh_s0; break;
2703
2704  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_hh_s1:
2705    ID = Intrinsic::hexagon_M2_mpy_sat_hh_s1; break;
2706
2707  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_hl_s0:
2708    ID = Intrinsic::hexagon_M2_mpy_sat_hl_s0; break;
2709
2710  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_hl_s1:
2711    ID = Intrinsic::hexagon_M2_mpy_sat_hl_s1; break;
2712
2713  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_lh_s0:
2714    ID = Intrinsic::hexagon_M2_mpy_sat_lh_s0; break;
2715
2716  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_lh_s1:
2717    ID = Intrinsic::hexagon_M2_mpy_sat_lh_s1; break;
2718
2719  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_ll_s0:
2720    ID = Intrinsic::hexagon_M2_mpy_sat_ll_s0; break;
2721
2722  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_ll_s1:
2723    ID = Intrinsic::hexagon_M2_mpy_sat_ll_s1; break;
2724
2725  case Hexagon::BI__builtin_HEXAGON_M2_mpy_rnd_hh_s0:
2726    ID = Intrinsic::hexagon_M2_mpy_rnd_hh_s0; break;
2727
2728  case Hexagon::BI__builtin_HEXAGON_M2_mpy_rnd_hh_s1:
2729    ID = Intrinsic::hexagon_M2_mpy_rnd_hh_s1; break;
2730
2731  case Hexagon::BI__builtin_HEXAGON_M2_mpy_rnd_hl_s0:
2732    ID = Intrinsic::hexagon_M2_mpy_rnd_hl_s0; break;
2733
2734  case Hexagon::BI__builtin_HEXAGON_M2_mpy_rnd_hl_s1:
2735    ID = Intrinsic::hexagon_M2_mpy_rnd_hl_s1; break;
2736
2737  case Hexagon::BI__builtin_HEXAGON_M2_mpy_rnd_lh_s0:
2738    ID = Intrinsic::hexagon_M2_mpy_rnd_lh_s0; break;
2739
2740  case Hexagon::BI__builtin_HEXAGON_M2_mpy_rnd_lh_s1:
2741    ID = Intrinsic::hexagon_M2_mpy_rnd_lh_s1; break;
2742
2743  case Hexagon::BI__builtin_HEXAGON_M2_mpy_rnd_ll_s0:
2744    ID = Intrinsic::hexagon_M2_mpy_rnd_ll_s0; break;
2745
2746  case Hexagon::BI__builtin_HEXAGON_M2_mpy_rnd_ll_s1:
2747    ID = Intrinsic::hexagon_M2_mpy_rnd_ll_s1; break;
2748
2749  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_rnd_hh_s0:
2750    ID = Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s0; break;
2751
2752  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_rnd_hh_s1:
2753    ID = Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s1; break;
2754
2755  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_rnd_hl_s0:
2756    ID = Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s0; break;
2757
2758  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_rnd_hl_s1:
2759    ID = Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s1; break;
2760
2761  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_rnd_lh_s0:
2762    ID = Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s0; break;
2763
2764  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_rnd_lh_s1:
2765    ID = Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s1; break;
2766
2767  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_rnd_ll_s0:
2768    ID = Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s0; break;
2769
2770  case Hexagon::BI__builtin_HEXAGON_M2_mpy_sat_rnd_ll_s1:
2771    ID = Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s1; break;
2772
2773  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_acc_hh_s0:
2774    ID = Intrinsic::hexagon_M2_mpyd_acc_hh_s0; break;
2775
2776  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_acc_hh_s1:
2777    ID = Intrinsic::hexagon_M2_mpyd_acc_hh_s1; break;
2778
2779  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_acc_hl_s0:
2780    ID = Intrinsic::hexagon_M2_mpyd_acc_hl_s0; break;
2781
2782  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_acc_hl_s1:
2783    ID = Intrinsic::hexagon_M2_mpyd_acc_hl_s1; break;
2784
2785  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_acc_lh_s0:
2786    ID = Intrinsic::hexagon_M2_mpyd_acc_lh_s0; break;
2787
2788  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_acc_lh_s1:
2789    ID = Intrinsic::hexagon_M2_mpyd_acc_lh_s1; break;
2790
2791  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_acc_ll_s0:
2792    ID = Intrinsic::hexagon_M2_mpyd_acc_ll_s0; break;
2793
2794  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_acc_ll_s1:
2795    ID = Intrinsic::hexagon_M2_mpyd_acc_ll_s1; break;
2796
2797  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_nac_hh_s0:
2798    ID = Intrinsic::hexagon_M2_mpyd_nac_hh_s0; break;
2799
2800  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_nac_hh_s1:
2801    ID = Intrinsic::hexagon_M2_mpyd_nac_hh_s1; break;
2802
2803  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_nac_hl_s0:
2804    ID = Intrinsic::hexagon_M2_mpyd_nac_hl_s0; break;
2805
2806  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_nac_hl_s1:
2807    ID = Intrinsic::hexagon_M2_mpyd_nac_hl_s1; break;
2808
2809  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_nac_lh_s0:
2810    ID = Intrinsic::hexagon_M2_mpyd_nac_lh_s0; break;
2811
2812  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_nac_lh_s1:
2813    ID = Intrinsic::hexagon_M2_mpyd_nac_lh_s1; break;
2814
2815  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_nac_ll_s0:
2816    ID = Intrinsic::hexagon_M2_mpyd_nac_ll_s0; break;
2817
2818  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_nac_ll_s1:
2819    ID = Intrinsic::hexagon_M2_mpyd_nac_ll_s1; break;
2820
2821  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_hh_s0:
2822    ID = Intrinsic::hexagon_M2_mpyd_hh_s0; break;
2823
2824  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_hh_s1:
2825    ID = Intrinsic::hexagon_M2_mpyd_hh_s1; break;
2826
2827  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_hl_s0:
2828    ID = Intrinsic::hexagon_M2_mpyd_hl_s0; break;
2829
2830  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_hl_s1:
2831    ID = Intrinsic::hexagon_M2_mpyd_hl_s1; break;
2832
2833  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_lh_s0:
2834    ID = Intrinsic::hexagon_M2_mpyd_lh_s0; break;
2835
2836  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_lh_s1:
2837    ID = Intrinsic::hexagon_M2_mpyd_lh_s1; break;
2838
2839  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_ll_s0:
2840    ID = Intrinsic::hexagon_M2_mpyd_ll_s0; break;
2841
2842  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_ll_s1:
2843    ID = Intrinsic::hexagon_M2_mpyd_ll_s1; break;
2844
2845  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_rnd_hh_s0:
2846    ID = Intrinsic::hexagon_M2_mpyd_rnd_hh_s0; break;
2847
2848  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_rnd_hh_s1:
2849    ID = Intrinsic::hexagon_M2_mpyd_rnd_hh_s1; break;
2850
2851  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_rnd_hl_s0:
2852    ID = Intrinsic::hexagon_M2_mpyd_rnd_hl_s0; break;
2853
2854  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_rnd_hl_s1:
2855    ID = Intrinsic::hexagon_M2_mpyd_rnd_hl_s1; break;
2856
2857  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_rnd_lh_s0:
2858    ID = Intrinsic::hexagon_M2_mpyd_rnd_lh_s0; break;
2859
2860  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_rnd_lh_s1:
2861    ID = Intrinsic::hexagon_M2_mpyd_rnd_lh_s1; break;
2862
2863  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_rnd_ll_s0:
2864    ID = Intrinsic::hexagon_M2_mpyd_rnd_ll_s0; break;
2865
2866  case Hexagon::BI__builtin_HEXAGON_M2_mpyd_rnd_ll_s1:
2867    ID = Intrinsic::hexagon_M2_mpyd_rnd_ll_s1; break;
2868
2869  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_acc_hh_s0:
2870    ID = Intrinsic::hexagon_M2_mpyu_acc_hh_s0; break;
2871
2872  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_acc_hh_s1:
2873    ID = Intrinsic::hexagon_M2_mpyu_acc_hh_s1; break;
2874
2875  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_acc_hl_s0:
2876    ID = Intrinsic::hexagon_M2_mpyu_acc_hl_s0; break;
2877
2878  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_acc_hl_s1:
2879    ID = Intrinsic::hexagon_M2_mpyu_acc_hl_s1; break;
2880
2881  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_acc_lh_s0:
2882    ID = Intrinsic::hexagon_M2_mpyu_acc_lh_s0; break;
2883
2884  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_acc_lh_s1:
2885    ID = Intrinsic::hexagon_M2_mpyu_acc_lh_s1; break;
2886
2887  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_acc_ll_s0:
2888    ID = Intrinsic::hexagon_M2_mpyu_acc_ll_s0; break;
2889
2890  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_acc_ll_s1:
2891    ID = Intrinsic::hexagon_M2_mpyu_acc_ll_s1; break;
2892
2893  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_nac_hh_s0:
2894    ID = Intrinsic::hexagon_M2_mpyu_nac_hh_s0; break;
2895
2896  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_nac_hh_s1:
2897    ID = Intrinsic::hexagon_M2_mpyu_nac_hh_s1; break;
2898
2899  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_nac_hl_s0:
2900    ID = Intrinsic::hexagon_M2_mpyu_nac_hl_s0; break;
2901
2902  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_nac_hl_s1:
2903    ID = Intrinsic::hexagon_M2_mpyu_nac_hl_s1; break;
2904
2905  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_nac_lh_s0:
2906    ID = Intrinsic::hexagon_M2_mpyu_nac_lh_s0; break;
2907
2908  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_nac_lh_s1:
2909    ID = Intrinsic::hexagon_M2_mpyu_nac_lh_s1; break;
2910
2911  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_nac_ll_s0:
2912    ID = Intrinsic::hexagon_M2_mpyu_nac_ll_s0; break;
2913
2914  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_nac_ll_s1:
2915    ID = Intrinsic::hexagon_M2_mpyu_nac_ll_s1; break;
2916
2917  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_hh_s0:
2918    ID = Intrinsic::hexagon_M2_mpyu_hh_s0; break;
2919
2920  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_hh_s1:
2921    ID = Intrinsic::hexagon_M2_mpyu_hh_s1; break;
2922
2923  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_hl_s0:
2924    ID = Intrinsic::hexagon_M2_mpyu_hl_s0; break;
2925
2926  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_hl_s1:
2927    ID = Intrinsic::hexagon_M2_mpyu_hl_s1; break;
2928
2929  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_lh_s0:
2930    ID = Intrinsic::hexagon_M2_mpyu_lh_s0; break;
2931
2932  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_lh_s1:
2933    ID = Intrinsic::hexagon_M2_mpyu_lh_s1; break;
2934
2935  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_ll_s0:
2936    ID = Intrinsic::hexagon_M2_mpyu_ll_s0; break;
2937
2938  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_ll_s1:
2939    ID = Intrinsic::hexagon_M2_mpyu_ll_s1; break;
2940
2941  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_acc_hh_s0:
2942    ID = Intrinsic::hexagon_M2_mpyud_acc_hh_s0; break;
2943
2944  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_acc_hh_s1:
2945    ID = Intrinsic::hexagon_M2_mpyud_acc_hh_s1; break;
2946
2947  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_acc_hl_s0:
2948    ID = Intrinsic::hexagon_M2_mpyud_acc_hl_s0; break;
2949
2950  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_acc_hl_s1:
2951    ID = Intrinsic::hexagon_M2_mpyud_acc_hl_s1; break;
2952
2953  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_acc_lh_s0:
2954    ID = Intrinsic::hexagon_M2_mpyud_acc_lh_s0; break;
2955
2956  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_acc_lh_s1:
2957    ID = Intrinsic::hexagon_M2_mpyud_acc_lh_s1; break;
2958
2959  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_acc_ll_s0:
2960    ID = Intrinsic::hexagon_M2_mpyud_acc_ll_s0; break;
2961
2962  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_acc_ll_s1:
2963    ID = Intrinsic::hexagon_M2_mpyud_acc_ll_s1; break;
2964
2965  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_nac_hh_s0:
2966    ID = Intrinsic::hexagon_M2_mpyud_nac_hh_s0; break;
2967
2968  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_nac_hh_s1:
2969    ID = Intrinsic::hexagon_M2_mpyud_nac_hh_s1; break;
2970
2971  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_nac_hl_s0:
2972    ID = Intrinsic::hexagon_M2_mpyud_nac_hl_s0; break;
2973
2974  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_nac_hl_s1:
2975    ID = Intrinsic::hexagon_M2_mpyud_nac_hl_s1; break;
2976
2977  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_nac_lh_s0:
2978    ID = Intrinsic::hexagon_M2_mpyud_nac_lh_s0; break;
2979
2980  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_nac_lh_s1:
2981    ID = Intrinsic::hexagon_M2_mpyud_nac_lh_s1; break;
2982
2983  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_nac_ll_s0:
2984    ID = Intrinsic::hexagon_M2_mpyud_nac_ll_s0; break;
2985
2986  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_nac_ll_s1:
2987    ID = Intrinsic::hexagon_M2_mpyud_nac_ll_s1; break;
2988
2989  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_hh_s0:
2990    ID = Intrinsic::hexagon_M2_mpyud_hh_s0; break;
2991
2992  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_hh_s1:
2993    ID = Intrinsic::hexagon_M2_mpyud_hh_s1; break;
2994
2995  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_hl_s0:
2996    ID = Intrinsic::hexagon_M2_mpyud_hl_s0; break;
2997
2998  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_hl_s1:
2999    ID = Intrinsic::hexagon_M2_mpyud_hl_s1; break;
3000
3001  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_lh_s0:
3002    ID = Intrinsic::hexagon_M2_mpyud_lh_s0; break;
3003
3004  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_lh_s1:
3005    ID = Intrinsic::hexagon_M2_mpyud_lh_s1; break;
3006
3007  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_ll_s0:
3008    ID = Intrinsic::hexagon_M2_mpyud_ll_s0; break;
3009
3010  case Hexagon::BI__builtin_HEXAGON_M2_mpyud_ll_s1:
3011    ID = Intrinsic::hexagon_M2_mpyud_ll_s1; break;
3012
3013  case Hexagon::BI__builtin_HEXAGON_M2_mpysmi:
3014    ID = Intrinsic::hexagon_M2_mpysmi; break;
3015
3016  case Hexagon::BI__builtin_HEXAGON_M2_macsip:
3017    ID = Intrinsic::hexagon_M2_macsip; break;
3018
3019  case Hexagon::BI__builtin_HEXAGON_M2_macsin:
3020    ID = Intrinsic::hexagon_M2_macsin; break;
3021
3022  case Hexagon::BI__builtin_HEXAGON_M2_dpmpyss_s0:
3023    ID = Intrinsic::hexagon_M2_dpmpyss_s0; break;
3024
3025  case Hexagon::BI__builtin_HEXAGON_M2_dpmpyss_acc_s0:
3026    ID = Intrinsic::hexagon_M2_dpmpyss_acc_s0; break;
3027
3028  case Hexagon::BI__builtin_HEXAGON_M2_dpmpyss_nac_s0:
3029    ID = Intrinsic::hexagon_M2_dpmpyss_nac_s0; break;
3030
3031  case Hexagon::BI__builtin_HEXAGON_M2_dpmpyuu_s0:
3032    ID = Intrinsic::hexagon_M2_dpmpyuu_s0; break;
3033
3034  case Hexagon::BI__builtin_HEXAGON_M2_dpmpyuu_acc_s0:
3035    ID = Intrinsic::hexagon_M2_dpmpyuu_acc_s0; break;
3036
3037  case Hexagon::BI__builtin_HEXAGON_M2_dpmpyuu_nac_s0:
3038    ID = Intrinsic::hexagon_M2_dpmpyuu_nac_s0; break;
3039
3040  case Hexagon::BI__builtin_HEXAGON_M2_mpy_up:
3041    ID = Intrinsic::hexagon_M2_mpy_up; break;
3042
3043  case Hexagon::BI__builtin_HEXAGON_M2_mpyu_up:
3044    ID = Intrinsic::hexagon_M2_mpyu_up; break;
3045
3046  case Hexagon::BI__builtin_HEXAGON_M2_dpmpyss_rnd_s0:
3047    ID = Intrinsic::hexagon_M2_dpmpyss_rnd_s0; break;
3048
3049  case Hexagon::BI__builtin_HEXAGON_M2_mpyi:
3050    ID = Intrinsic::hexagon_M2_mpyi; break;
3051
3052  case Hexagon::BI__builtin_HEXAGON_M2_mpyui:
3053    ID = Intrinsic::hexagon_M2_mpyui; break;
3054
3055  case Hexagon::BI__builtin_HEXAGON_M2_maci:
3056    ID = Intrinsic::hexagon_M2_maci; break;
3057
3058  case Hexagon::BI__builtin_HEXAGON_M2_acci:
3059    ID = Intrinsic::hexagon_M2_acci; break;
3060
3061  case Hexagon::BI__builtin_HEXAGON_M2_accii:
3062    ID = Intrinsic::hexagon_M2_accii; break;
3063
3064  case Hexagon::BI__builtin_HEXAGON_M2_nacci:
3065    ID = Intrinsic::hexagon_M2_nacci; break;
3066
3067  case Hexagon::BI__builtin_HEXAGON_M2_naccii:
3068    ID = Intrinsic::hexagon_M2_naccii; break;
3069
3070  case Hexagon::BI__builtin_HEXAGON_M2_subacc:
3071    ID = Intrinsic::hexagon_M2_subacc; break;
3072
3073  case Hexagon::BI__builtin_HEXAGON_M2_vmpy2s_s0:
3074    ID = Intrinsic::hexagon_M2_vmpy2s_s0; break;
3075
3076  case Hexagon::BI__builtin_HEXAGON_M2_vmpy2s_s1:
3077    ID = Intrinsic::hexagon_M2_vmpy2s_s1; break;
3078
3079  case Hexagon::BI__builtin_HEXAGON_M2_vmac2s_s0:
3080    ID = Intrinsic::hexagon_M2_vmac2s_s0; break;
3081
3082  case Hexagon::BI__builtin_HEXAGON_M2_vmac2s_s1:
3083    ID = Intrinsic::hexagon_M2_vmac2s_s1; break;
3084
3085  case Hexagon::BI__builtin_HEXAGON_M2_vmpy2s_s0pack:
3086    ID = Intrinsic::hexagon_M2_vmpy2s_s0pack; break;
3087
3088  case Hexagon::BI__builtin_HEXAGON_M2_vmpy2s_s1pack:
3089    ID = Intrinsic::hexagon_M2_vmpy2s_s1pack; break;
3090
3091  case Hexagon::BI__builtin_HEXAGON_M2_vmac2:
3092    ID = Intrinsic::hexagon_M2_vmac2; break;
3093
3094  case Hexagon::BI__builtin_HEXAGON_M2_vmpy2es_s0:
3095    ID = Intrinsic::hexagon_M2_vmpy2es_s0; break;
3096
3097  case Hexagon::BI__builtin_HEXAGON_M2_vmpy2es_s1:
3098    ID = Intrinsic::hexagon_M2_vmpy2es_s1; break;
3099
3100  case Hexagon::BI__builtin_HEXAGON_M2_vmac2es_s0:
3101    ID = Intrinsic::hexagon_M2_vmac2es_s0; break;
3102
3103  case Hexagon::BI__builtin_HEXAGON_M2_vmac2es_s1:
3104    ID = Intrinsic::hexagon_M2_vmac2es_s1; break;
3105
3106  case Hexagon::BI__builtin_HEXAGON_M2_vmac2es:
3107    ID = Intrinsic::hexagon_M2_vmac2es; break;
3108
3109  case Hexagon::BI__builtin_HEXAGON_M2_vrmac_s0:
3110    ID = Intrinsic::hexagon_M2_vrmac_s0; break;
3111
3112  case Hexagon::BI__builtin_HEXAGON_M2_vrmpy_s0:
3113    ID = Intrinsic::hexagon_M2_vrmpy_s0; break;
3114
3115  case Hexagon::BI__builtin_HEXAGON_M2_vdmpyrs_s0:
3116    ID = Intrinsic::hexagon_M2_vdmpyrs_s0; break;
3117
3118  case Hexagon::BI__builtin_HEXAGON_M2_vdmpyrs_s1:
3119    ID = Intrinsic::hexagon_M2_vdmpyrs_s1; break;
3120
3121  case Hexagon::BI__builtin_HEXAGON_M2_vdmacs_s0:
3122    ID = Intrinsic::hexagon_M2_vdmacs_s0; break;
3123
3124  case Hexagon::BI__builtin_HEXAGON_M2_vdmacs_s1:
3125    ID = Intrinsic::hexagon_M2_vdmacs_s1; break;
3126
3127  case Hexagon::BI__builtin_HEXAGON_M2_vdmpys_s0:
3128    ID = Intrinsic::hexagon_M2_vdmpys_s0; break;
3129
3130  case Hexagon::BI__builtin_HEXAGON_M2_vdmpys_s1:
3131    ID = Intrinsic::hexagon_M2_vdmpys_s1; break;
3132
3133  case Hexagon::BI__builtin_HEXAGON_M2_cmpyrs_s0:
3134    ID = Intrinsic::hexagon_M2_cmpyrs_s0; break;
3135
3136  case Hexagon::BI__builtin_HEXAGON_M2_cmpyrs_s1:
3137    ID = Intrinsic::hexagon_M2_cmpyrs_s1; break;
3138
3139  case Hexagon::BI__builtin_HEXAGON_M2_cmpyrsc_s0:
3140    ID = Intrinsic::hexagon_M2_cmpyrsc_s0; break;
3141
3142  case Hexagon::BI__builtin_HEXAGON_M2_cmpyrsc_s1:
3143    ID = Intrinsic::hexagon_M2_cmpyrsc_s1; break;
3144
3145  case Hexagon::BI__builtin_HEXAGON_M2_cmacs_s0:
3146    ID = Intrinsic::hexagon_M2_cmacs_s0; break;
3147
3148  case Hexagon::BI__builtin_HEXAGON_M2_cmacs_s1:
3149    ID = Intrinsic::hexagon_M2_cmacs_s1; break;
3150
3151  case Hexagon::BI__builtin_HEXAGON_M2_cmacsc_s0:
3152    ID = Intrinsic::hexagon_M2_cmacsc_s0; break;
3153
3154  case Hexagon::BI__builtin_HEXAGON_M2_cmacsc_s1:
3155    ID = Intrinsic::hexagon_M2_cmacsc_s1; break;
3156
3157  case Hexagon::BI__builtin_HEXAGON_M2_cmpys_s0:
3158    ID = Intrinsic::hexagon_M2_cmpys_s0; break;
3159
3160  case Hexagon::BI__builtin_HEXAGON_M2_cmpys_s1:
3161    ID = Intrinsic::hexagon_M2_cmpys_s1; break;
3162
3163  case Hexagon::BI__builtin_HEXAGON_M2_cmpysc_s0:
3164    ID = Intrinsic::hexagon_M2_cmpysc_s0; break;
3165
3166  case Hexagon::BI__builtin_HEXAGON_M2_cmpysc_s1:
3167    ID = Intrinsic::hexagon_M2_cmpysc_s1; break;
3168
3169  case Hexagon::BI__builtin_HEXAGON_M2_cnacs_s0:
3170    ID = Intrinsic::hexagon_M2_cnacs_s0; break;
3171
3172  case Hexagon::BI__builtin_HEXAGON_M2_cnacs_s1:
3173    ID = Intrinsic::hexagon_M2_cnacs_s1; break;
3174
3175  case Hexagon::BI__builtin_HEXAGON_M2_cnacsc_s0:
3176    ID = Intrinsic::hexagon_M2_cnacsc_s0; break;
3177
3178  case Hexagon::BI__builtin_HEXAGON_M2_cnacsc_s1:
3179    ID = Intrinsic::hexagon_M2_cnacsc_s1; break;
3180
3181  case Hexagon::BI__builtin_HEXAGON_M2_vrcmpys_s1:
3182    ID = Intrinsic::hexagon_M2_vrcmpys_s1; break;
3183
3184  case Hexagon::BI__builtin_HEXAGON_M2_vrcmpys_acc_s1:
3185    ID = Intrinsic::hexagon_M2_vrcmpys_acc_s1; break;
3186
3187  case Hexagon::BI__builtin_HEXAGON_M2_vrcmpys_s1rp:
3188    ID = Intrinsic::hexagon_M2_vrcmpys_s1rp; break;
3189
3190  case Hexagon::BI__builtin_HEXAGON_M2_mmacls_s0:
3191    ID = Intrinsic::hexagon_M2_mmacls_s0; break;
3192
3193  case Hexagon::BI__builtin_HEXAGON_M2_mmacls_s1:
3194    ID = Intrinsic::hexagon_M2_mmacls_s1; break;
3195
3196  case Hexagon::BI__builtin_HEXAGON_M2_mmachs_s0:
3197    ID = Intrinsic::hexagon_M2_mmachs_s0; break;
3198
3199  case Hexagon::BI__builtin_HEXAGON_M2_mmachs_s1:
3200    ID = Intrinsic::hexagon_M2_mmachs_s1; break;
3201
3202  case Hexagon::BI__builtin_HEXAGON_M2_mmpyl_s0:
3203    ID = Intrinsic::hexagon_M2_mmpyl_s0; break;
3204
3205  case Hexagon::BI__builtin_HEXAGON_M2_mmpyl_s1:
3206    ID = Intrinsic::hexagon_M2_mmpyl_s1; break;
3207
3208  case Hexagon::BI__builtin_HEXAGON_M2_mmpyh_s0:
3209    ID = Intrinsic::hexagon_M2_mmpyh_s0; break;
3210
3211  case Hexagon::BI__builtin_HEXAGON_M2_mmpyh_s1:
3212    ID = Intrinsic::hexagon_M2_mmpyh_s1; break;
3213
3214  case Hexagon::BI__builtin_HEXAGON_M2_mmacls_rs0:
3215    ID = Intrinsic::hexagon_M2_mmacls_rs0; break;
3216
3217  case Hexagon::BI__builtin_HEXAGON_M2_mmacls_rs1:
3218    ID = Intrinsic::hexagon_M2_mmacls_rs1; break;
3219
3220  case Hexagon::BI__builtin_HEXAGON_M2_mmachs_rs0:
3221    ID = Intrinsic::hexagon_M2_mmachs_rs0; break;
3222
3223  case Hexagon::BI__builtin_HEXAGON_M2_mmachs_rs1:
3224    ID = Intrinsic::hexagon_M2_mmachs_rs1; break;
3225
3226  case Hexagon::BI__builtin_HEXAGON_M2_mmpyl_rs0:
3227    ID = Intrinsic::hexagon_M2_mmpyl_rs0; break;
3228
3229  case Hexagon::BI__builtin_HEXAGON_M2_mmpyl_rs1:
3230    ID = Intrinsic::hexagon_M2_mmpyl_rs1; break;
3231
3232  case Hexagon::BI__builtin_HEXAGON_M2_mmpyh_rs0:
3233    ID = Intrinsic::hexagon_M2_mmpyh_rs0; break;
3234
3235  case Hexagon::BI__builtin_HEXAGON_M2_mmpyh_rs1:
3236    ID = Intrinsic::hexagon_M2_mmpyh_rs1; break;
3237
3238  case Hexagon::BI__builtin_HEXAGON_M2_hmmpyl_rs1:
3239    ID = Intrinsic::hexagon_M2_hmmpyl_rs1; break;
3240
3241  case Hexagon::BI__builtin_HEXAGON_M2_hmmpyh_rs1:
3242    ID = Intrinsic::hexagon_M2_hmmpyh_rs1; break;
3243
3244  case Hexagon::BI__builtin_HEXAGON_M2_mmaculs_s0:
3245    ID = Intrinsic::hexagon_M2_mmaculs_s0; break;
3246
3247  case Hexagon::BI__builtin_HEXAGON_M2_mmaculs_s1:
3248    ID = Intrinsic::hexagon_M2_mmaculs_s1; break;
3249
3250  case Hexagon::BI__builtin_HEXAGON_M2_mmacuhs_s0:
3251    ID = Intrinsic::hexagon_M2_mmacuhs_s0; break;
3252
3253  case Hexagon::BI__builtin_HEXAGON_M2_mmacuhs_s1:
3254    ID = Intrinsic::hexagon_M2_mmacuhs_s1; break;
3255
3256  case Hexagon::BI__builtin_HEXAGON_M2_mmpyul_s0:
3257    ID = Intrinsic::hexagon_M2_mmpyul_s0; break;
3258
3259  case Hexagon::BI__builtin_HEXAGON_M2_mmpyul_s1:
3260    ID = Intrinsic::hexagon_M2_mmpyul_s1; break;
3261
3262  case Hexagon::BI__builtin_HEXAGON_M2_mmpyuh_s0:
3263    ID = Intrinsic::hexagon_M2_mmpyuh_s0; break;
3264
3265  case Hexagon::BI__builtin_HEXAGON_M2_mmpyuh_s1:
3266    ID = Intrinsic::hexagon_M2_mmpyuh_s1; break;
3267
3268  case Hexagon::BI__builtin_HEXAGON_M2_mmaculs_rs0:
3269    ID = Intrinsic::hexagon_M2_mmaculs_rs0; break;
3270
3271  case Hexagon::BI__builtin_HEXAGON_M2_mmaculs_rs1:
3272    ID = Intrinsic::hexagon_M2_mmaculs_rs1; break;
3273
3274  case Hexagon::BI__builtin_HEXAGON_M2_mmacuhs_rs0:
3275    ID = Intrinsic::hexagon_M2_mmacuhs_rs0; break;
3276
3277  case Hexagon::BI__builtin_HEXAGON_M2_mmacuhs_rs1:
3278    ID = Intrinsic::hexagon_M2_mmacuhs_rs1; break;
3279
3280  case Hexagon::BI__builtin_HEXAGON_M2_mmpyul_rs0:
3281    ID = Intrinsic::hexagon_M2_mmpyul_rs0; break;
3282
3283  case Hexagon::BI__builtin_HEXAGON_M2_mmpyul_rs1:
3284    ID = Intrinsic::hexagon_M2_mmpyul_rs1; break;
3285
3286  case Hexagon::BI__builtin_HEXAGON_M2_mmpyuh_rs0:
3287    ID = Intrinsic::hexagon_M2_mmpyuh_rs0; break;
3288
3289  case Hexagon::BI__builtin_HEXAGON_M2_mmpyuh_rs1:
3290    ID = Intrinsic::hexagon_M2_mmpyuh_rs1; break;
3291
3292  case Hexagon::BI__builtin_HEXAGON_M2_vrcmaci_s0:
3293    ID = Intrinsic::hexagon_M2_vrcmaci_s0; break;
3294
3295  case Hexagon::BI__builtin_HEXAGON_M2_vrcmacr_s0:
3296    ID = Intrinsic::hexagon_M2_vrcmacr_s0; break;
3297
3298  case Hexagon::BI__builtin_HEXAGON_M2_vrcmaci_s0c:
3299    ID = Intrinsic::hexagon_M2_vrcmaci_s0c; break;
3300
3301  case Hexagon::BI__builtin_HEXAGON_M2_vrcmacr_s0c:
3302    ID = Intrinsic::hexagon_M2_vrcmacr_s0c; break;
3303
3304  case Hexagon::BI__builtin_HEXAGON_M2_cmaci_s0:
3305    ID = Intrinsic::hexagon_M2_cmaci_s0; break;
3306
3307  case Hexagon::BI__builtin_HEXAGON_M2_cmacr_s0:
3308    ID = Intrinsic::hexagon_M2_cmacr_s0; break;
3309
3310  case Hexagon::BI__builtin_HEXAGON_M2_vrcmpyi_s0:
3311    ID = Intrinsic::hexagon_M2_vrcmpyi_s0; break;
3312
3313  case Hexagon::BI__builtin_HEXAGON_M2_vrcmpyr_s0:
3314    ID = Intrinsic::hexagon_M2_vrcmpyr_s0; break;
3315
3316  case Hexagon::BI__builtin_HEXAGON_M2_vrcmpyi_s0c:
3317    ID = Intrinsic::hexagon_M2_vrcmpyi_s0c; break;
3318
3319  case Hexagon::BI__builtin_HEXAGON_M2_vrcmpyr_s0c:
3320    ID = Intrinsic::hexagon_M2_vrcmpyr_s0c; break;
3321
3322  case Hexagon::BI__builtin_HEXAGON_M2_cmpyi_s0:
3323    ID = Intrinsic::hexagon_M2_cmpyi_s0; break;
3324
3325  case Hexagon::BI__builtin_HEXAGON_M2_cmpyr_s0:
3326    ID = Intrinsic::hexagon_M2_cmpyr_s0; break;
3327
3328  case Hexagon::BI__builtin_HEXAGON_M2_vcmpy_s0_sat_i:
3329    ID = Intrinsic::hexagon_M2_vcmpy_s0_sat_i; break;
3330
3331  case Hexagon::BI__builtin_HEXAGON_M2_vcmpy_s0_sat_r:
3332    ID = Intrinsic::hexagon_M2_vcmpy_s0_sat_r; break;
3333
3334  case Hexagon::BI__builtin_HEXAGON_M2_vcmpy_s1_sat_i:
3335    ID = Intrinsic::hexagon_M2_vcmpy_s1_sat_i; break;
3336
3337  case Hexagon::BI__builtin_HEXAGON_M2_vcmpy_s1_sat_r:
3338    ID = Intrinsic::hexagon_M2_vcmpy_s1_sat_r; break;
3339
3340  case Hexagon::BI__builtin_HEXAGON_M2_vcmac_s0_sat_i:
3341    ID = Intrinsic::hexagon_M2_vcmac_s0_sat_i; break;
3342
3343  case Hexagon::BI__builtin_HEXAGON_M2_vcmac_s0_sat_r:
3344    ID = Intrinsic::hexagon_M2_vcmac_s0_sat_r; break;
3345
3346  case Hexagon::BI__builtin_HEXAGON_S2_vcrotate:
3347    ID = Intrinsic::hexagon_S2_vcrotate; break;
3348
3349  case Hexagon::BI__builtin_HEXAGON_A2_add:
3350    ID = Intrinsic::hexagon_A2_add; break;
3351
3352  case Hexagon::BI__builtin_HEXAGON_A2_sub:
3353    ID = Intrinsic::hexagon_A2_sub; break;
3354
3355  case Hexagon::BI__builtin_HEXAGON_A2_addsat:
3356    ID = Intrinsic::hexagon_A2_addsat; break;
3357
3358  case Hexagon::BI__builtin_HEXAGON_A2_subsat:
3359    ID = Intrinsic::hexagon_A2_subsat; break;
3360
3361  case Hexagon::BI__builtin_HEXAGON_A2_addi:
3362    ID = Intrinsic::hexagon_A2_addi; break;
3363
3364  case Hexagon::BI__builtin_HEXAGON_A2_addh_l16_ll:
3365    ID = Intrinsic::hexagon_A2_addh_l16_ll; break;
3366
3367  case Hexagon::BI__builtin_HEXAGON_A2_addh_l16_hl:
3368    ID = Intrinsic::hexagon_A2_addh_l16_hl; break;
3369
3370  case Hexagon::BI__builtin_HEXAGON_A2_addh_l16_sat_ll:
3371    ID = Intrinsic::hexagon_A2_addh_l16_sat_ll; break;
3372
3373  case Hexagon::BI__builtin_HEXAGON_A2_addh_l16_sat_hl:
3374    ID = Intrinsic::hexagon_A2_addh_l16_sat_hl; break;
3375
3376  case Hexagon::BI__builtin_HEXAGON_A2_subh_l16_ll:
3377    ID = Intrinsic::hexagon_A2_subh_l16_ll; break;
3378
3379  case Hexagon::BI__builtin_HEXAGON_A2_subh_l16_hl:
3380    ID = Intrinsic::hexagon_A2_subh_l16_hl; break;
3381
3382  case Hexagon::BI__builtin_HEXAGON_A2_subh_l16_sat_ll:
3383    ID = Intrinsic::hexagon_A2_subh_l16_sat_ll; break;
3384
3385  case Hexagon::BI__builtin_HEXAGON_A2_subh_l16_sat_hl:
3386    ID = Intrinsic::hexagon_A2_subh_l16_sat_hl; break;
3387
3388  case Hexagon::BI__builtin_HEXAGON_A2_addh_h16_ll:
3389    ID = Intrinsic::hexagon_A2_addh_h16_ll; break;
3390
3391  case Hexagon::BI__builtin_HEXAGON_A2_addh_h16_lh:
3392    ID = Intrinsic::hexagon_A2_addh_h16_lh; break;
3393
3394  case Hexagon::BI__builtin_HEXAGON_A2_addh_h16_hl:
3395    ID = Intrinsic::hexagon_A2_addh_h16_hl; break;
3396
3397  case Hexagon::BI__builtin_HEXAGON_A2_addh_h16_hh:
3398    ID = Intrinsic::hexagon_A2_addh_h16_hh; break;
3399
3400  case Hexagon::BI__builtin_HEXAGON_A2_addh_h16_sat_ll:
3401    ID = Intrinsic::hexagon_A2_addh_h16_sat_ll; break;
3402
3403  case Hexagon::BI__builtin_HEXAGON_A2_addh_h16_sat_lh:
3404    ID = Intrinsic::hexagon_A2_addh_h16_sat_lh; break;
3405
3406  case Hexagon::BI__builtin_HEXAGON_A2_addh_h16_sat_hl:
3407    ID = Intrinsic::hexagon_A2_addh_h16_sat_hl; break;
3408
3409  case Hexagon::BI__builtin_HEXAGON_A2_addh_h16_sat_hh:
3410    ID = Intrinsic::hexagon_A2_addh_h16_sat_hh; break;
3411
3412  case Hexagon::BI__builtin_HEXAGON_A2_subh_h16_ll:
3413    ID = Intrinsic::hexagon_A2_subh_h16_ll; break;
3414
3415  case Hexagon::BI__builtin_HEXAGON_A2_subh_h16_lh:
3416    ID = Intrinsic::hexagon_A2_subh_h16_lh; break;
3417
3418  case Hexagon::BI__builtin_HEXAGON_A2_subh_h16_hl:
3419    ID = Intrinsic::hexagon_A2_subh_h16_hl; break;
3420
3421  case Hexagon::BI__builtin_HEXAGON_A2_subh_h16_hh:
3422    ID = Intrinsic::hexagon_A2_subh_h16_hh; break;
3423
3424  case Hexagon::BI__builtin_HEXAGON_A2_subh_h16_sat_ll:
3425    ID = Intrinsic::hexagon_A2_subh_h16_sat_ll; break;
3426
3427  case Hexagon::BI__builtin_HEXAGON_A2_subh_h16_sat_lh:
3428    ID = Intrinsic::hexagon_A2_subh_h16_sat_lh; break;
3429
3430  case Hexagon::BI__builtin_HEXAGON_A2_subh_h16_sat_hl:
3431    ID = Intrinsic::hexagon_A2_subh_h16_sat_hl; break;
3432
3433  case Hexagon::BI__builtin_HEXAGON_A2_subh_h16_sat_hh:
3434    ID = Intrinsic::hexagon_A2_subh_h16_sat_hh; break;
3435
3436  case Hexagon::BI__builtin_HEXAGON_A2_aslh:
3437    ID = Intrinsic::hexagon_A2_aslh; break;
3438
3439  case Hexagon::BI__builtin_HEXAGON_A2_asrh:
3440    ID = Intrinsic::hexagon_A2_asrh; break;
3441
3442  case Hexagon::BI__builtin_HEXAGON_A2_addp:
3443    ID = Intrinsic::hexagon_A2_addp; break;
3444
3445  case Hexagon::BI__builtin_HEXAGON_A2_addpsat:
3446    ID = Intrinsic::hexagon_A2_addpsat; break;
3447
3448  case Hexagon::BI__builtin_HEXAGON_A2_addsp:
3449    ID = Intrinsic::hexagon_A2_addsp; break;
3450
3451  case Hexagon::BI__builtin_HEXAGON_A2_subp:
3452    ID = Intrinsic::hexagon_A2_subp; break;
3453
3454  case Hexagon::BI__builtin_HEXAGON_A2_neg:
3455    ID = Intrinsic::hexagon_A2_neg; break;
3456
3457  case Hexagon::BI__builtin_HEXAGON_A2_negsat:
3458    ID = Intrinsic::hexagon_A2_negsat; break;
3459
3460  case Hexagon::BI__builtin_HEXAGON_A2_abs:
3461    ID = Intrinsic::hexagon_A2_abs; break;
3462
3463  case Hexagon::BI__builtin_HEXAGON_A2_abssat:
3464    ID = Intrinsic::hexagon_A2_abssat; break;
3465
3466  case Hexagon::BI__builtin_HEXAGON_A2_vconj:
3467    ID = Intrinsic::hexagon_A2_vconj; break;
3468
3469  case Hexagon::BI__builtin_HEXAGON_A2_negp:
3470    ID = Intrinsic::hexagon_A2_negp; break;
3471
3472  case Hexagon::BI__builtin_HEXAGON_A2_absp:
3473    ID = Intrinsic::hexagon_A2_absp; break;
3474
3475  case Hexagon::BI__builtin_HEXAGON_A2_max:
3476    ID = Intrinsic::hexagon_A2_max; break;
3477
3478  case Hexagon::BI__builtin_HEXAGON_A2_maxu:
3479    ID = Intrinsic::hexagon_A2_maxu; break;
3480
3481  case Hexagon::BI__builtin_HEXAGON_A2_min:
3482    ID = Intrinsic::hexagon_A2_min; break;
3483
3484  case Hexagon::BI__builtin_HEXAGON_A2_minu:
3485    ID = Intrinsic::hexagon_A2_minu; break;
3486
3487  case Hexagon::BI__builtin_HEXAGON_A2_maxp:
3488    ID = Intrinsic::hexagon_A2_maxp; break;
3489
3490  case Hexagon::BI__builtin_HEXAGON_A2_maxup:
3491    ID = Intrinsic::hexagon_A2_maxup; break;
3492
3493  case Hexagon::BI__builtin_HEXAGON_A2_minp:
3494    ID = Intrinsic::hexagon_A2_minp; break;
3495
3496  case Hexagon::BI__builtin_HEXAGON_A2_minup:
3497    ID = Intrinsic::hexagon_A2_minup; break;
3498
3499  case Hexagon::BI__builtin_HEXAGON_A2_tfr:
3500    ID = Intrinsic::hexagon_A2_tfr; break;
3501
3502  case Hexagon::BI__builtin_HEXAGON_A2_tfrsi:
3503    ID = Intrinsic::hexagon_A2_tfrsi; break;
3504
3505  case Hexagon::BI__builtin_HEXAGON_A2_tfrp:
3506    ID = Intrinsic::hexagon_A2_tfrp; break;
3507
3508  case Hexagon::BI__builtin_HEXAGON_A2_tfrpi:
3509    ID = Intrinsic::hexagon_A2_tfrpi; break;
3510
3511  case Hexagon::BI__builtin_HEXAGON_A2_zxtb:
3512    ID = Intrinsic::hexagon_A2_zxtb; break;
3513
3514  case Hexagon::BI__builtin_HEXAGON_A2_sxtb:
3515    ID = Intrinsic::hexagon_A2_sxtb; break;
3516
3517  case Hexagon::BI__builtin_HEXAGON_A2_zxth:
3518    ID = Intrinsic::hexagon_A2_zxth; break;
3519
3520  case Hexagon::BI__builtin_HEXAGON_A2_sxth:
3521    ID = Intrinsic::hexagon_A2_sxth; break;
3522
3523  case Hexagon::BI__builtin_HEXAGON_A2_combinew:
3524    ID = Intrinsic::hexagon_A2_combinew; break;
3525
3526  case Hexagon::BI__builtin_HEXAGON_A2_combineii:
3527    ID = Intrinsic::hexagon_A2_combineii; break;
3528
3529  case Hexagon::BI__builtin_HEXAGON_A2_combine_hh:
3530    ID = Intrinsic::hexagon_A2_combine_hh; break;
3531
3532  case Hexagon::BI__builtin_HEXAGON_A2_combine_hl:
3533    ID = Intrinsic::hexagon_A2_combine_hl; break;
3534
3535  case Hexagon::BI__builtin_HEXAGON_A2_combine_lh:
3536    ID = Intrinsic::hexagon_A2_combine_lh; break;
3537
3538  case Hexagon::BI__builtin_HEXAGON_A2_combine_ll:
3539    ID = Intrinsic::hexagon_A2_combine_ll; break;
3540
3541  case Hexagon::BI__builtin_HEXAGON_A2_tfril:
3542    ID = Intrinsic::hexagon_A2_tfril; break;
3543
3544  case Hexagon::BI__builtin_HEXAGON_A2_tfrih:
3545    ID = Intrinsic::hexagon_A2_tfrih; break;
3546
3547  case Hexagon::BI__builtin_HEXAGON_A2_and:
3548    ID = Intrinsic::hexagon_A2_and; break;
3549
3550  case Hexagon::BI__builtin_HEXAGON_A2_or:
3551    ID = Intrinsic::hexagon_A2_or; break;
3552
3553  case Hexagon::BI__builtin_HEXAGON_A2_xor:
3554    ID = Intrinsic::hexagon_A2_xor; break;
3555
3556  case Hexagon::BI__builtin_HEXAGON_A2_not:
3557    ID = Intrinsic::hexagon_A2_not; break;
3558
3559  case Hexagon::BI__builtin_HEXAGON_M2_xor_xacc:
3560    ID = Intrinsic::hexagon_M2_xor_xacc; break;
3561
3562  case Hexagon::BI__builtin_HEXAGON_A2_subri:
3563    ID = Intrinsic::hexagon_A2_subri; break;
3564
3565  case Hexagon::BI__builtin_HEXAGON_A2_andir:
3566    ID = Intrinsic::hexagon_A2_andir; break;
3567
3568  case Hexagon::BI__builtin_HEXAGON_A2_orir:
3569    ID = Intrinsic::hexagon_A2_orir; break;
3570
3571  case Hexagon::BI__builtin_HEXAGON_A2_andp:
3572    ID = Intrinsic::hexagon_A2_andp; break;
3573
3574  case Hexagon::BI__builtin_HEXAGON_A2_orp:
3575    ID = Intrinsic::hexagon_A2_orp; break;
3576
3577  case Hexagon::BI__builtin_HEXAGON_A2_xorp:
3578    ID = Intrinsic::hexagon_A2_xorp; break;
3579
3580  case Hexagon::BI__builtin_HEXAGON_A2_notp:
3581    ID = Intrinsic::hexagon_A2_notp; break;
3582
3583  case Hexagon::BI__builtin_HEXAGON_A2_sxtw:
3584    ID = Intrinsic::hexagon_A2_sxtw; break;
3585
3586  case Hexagon::BI__builtin_HEXAGON_A2_sat:
3587    ID = Intrinsic::hexagon_A2_sat; break;
3588
3589  case Hexagon::BI__builtin_HEXAGON_A2_sath:
3590    ID = Intrinsic::hexagon_A2_sath; break;
3591
3592  case Hexagon::BI__builtin_HEXAGON_A2_satuh:
3593    ID = Intrinsic::hexagon_A2_satuh; break;
3594
3595  case Hexagon::BI__builtin_HEXAGON_A2_satub:
3596    ID = Intrinsic::hexagon_A2_satub; break;
3597
3598  case Hexagon::BI__builtin_HEXAGON_A2_satb:
3599    ID = Intrinsic::hexagon_A2_satb; break;
3600
3601  case Hexagon::BI__builtin_HEXAGON_A2_vaddub:
3602    ID = Intrinsic::hexagon_A2_vaddub; break;
3603
3604  case Hexagon::BI__builtin_HEXAGON_A2_vaddubs:
3605    ID = Intrinsic::hexagon_A2_vaddubs; break;
3606
3607  case Hexagon::BI__builtin_HEXAGON_A2_vaddh:
3608    ID = Intrinsic::hexagon_A2_vaddh; break;
3609
3610  case Hexagon::BI__builtin_HEXAGON_A2_vaddhs:
3611    ID = Intrinsic::hexagon_A2_vaddhs; break;
3612
3613  case Hexagon::BI__builtin_HEXAGON_A2_vadduhs:
3614    ID = Intrinsic::hexagon_A2_vadduhs; break;
3615
3616  case Hexagon::BI__builtin_HEXAGON_A2_vaddw:
3617    ID = Intrinsic::hexagon_A2_vaddw; break;
3618
3619  case Hexagon::BI__builtin_HEXAGON_A2_vaddws:
3620    ID = Intrinsic::hexagon_A2_vaddws; break;
3621
3622  case Hexagon::BI__builtin_HEXAGON_A2_svavgh:
3623    ID = Intrinsic::hexagon_A2_svavgh; break;
3624
3625  case Hexagon::BI__builtin_HEXAGON_A2_svavghs:
3626    ID = Intrinsic::hexagon_A2_svavghs; break;
3627
3628  case Hexagon::BI__builtin_HEXAGON_A2_svnavgh:
3629    ID = Intrinsic::hexagon_A2_svnavgh; break;
3630
3631  case Hexagon::BI__builtin_HEXAGON_A2_svaddh:
3632    ID = Intrinsic::hexagon_A2_svaddh; break;
3633
3634  case Hexagon::BI__builtin_HEXAGON_A2_svaddhs:
3635    ID = Intrinsic::hexagon_A2_svaddhs; break;
3636
3637  case Hexagon::BI__builtin_HEXAGON_A2_svadduhs:
3638    ID = Intrinsic::hexagon_A2_svadduhs; break;
3639
3640  case Hexagon::BI__builtin_HEXAGON_A2_svsubh:
3641    ID = Intrinsic::hexagon_A2_svsubh; break;
3642
3643  case Hexagon::BI__builtin_HEXAGON_A2_svsubhs:
3644    ID = Intrinsic::hexagon_A2_svsubhs; break;
3645
3646  case Hexagon::BI__builtin_HEXAGON_A2_svsubuhs:
3647    ID = Intrinsic::hexagon_A2_svsubuhs; break;
3648
3649  case Hexagon::BI__builtin_HEXAGON_A2_vraddub:
3650    ID = Intrinsic::hexagon_A2_vraddub; break;
3651
3652  case Hexagon::BI__builtin_HEXAGON_A2_vraddub_acc:
3653    ID = Intrinsic::hexagon_A2_vraddub_acc; break;
3654
3655  case Hexagon::BI__builtin_HEXAGON_M2_vradduh:
3656    ID = Intrinsic::hexagon_M2_vradduh; break;
3657
3658  case Hexagon::BI__builtin_HEXAGON_A2_vsubub:
3659    ID = Intrinsic::hexagon_A2_vsubub; break;
3660
3661  case Hexagon::BI__builtin_HEXAGON_A2_vsububs:
3662    ID = Intrinsic::hexagon_A2_vsububs; break;
3663
3664  case Hexagon::BI__builtin_HEXAGON_A2_vsubh:
3665    ID = Intrinsic::hexagon_A2_vsubh; break;
3666
3667  case Hexagon::BI__builtin_HEXAGON_A2_vsubhs:
3668    ID = Intrinsic::hexagon_A2_vsubhs; break;
3669
3670  case Hexagon::BI__builtin_HEXAGON_A2_vsubuhs:
3671    ID = Intrinsic::hexagon_A2_vsubuhs; break;
3672
3673  case Hexagon::BI__builtin_HEXAGON_A2_vsubw:
3674    ID = Intrinsic::hexagon_A2_vsubw; break;
3675
3676  case Hexagon::BI__builtin_HEXAGON_A2_vsubws:
3677    ID = Intrinsic::hexagon_A2_vsubws; break;
3678
3679  case Hexagon::BI__builtin_HEXAGON_A2_vabsh:
3680    ID = Intrinsic::hexagon_A2_vabsh; break;
3681
3682  case Hexagon::BI__builtin_HEXAGON_A2_vabshsat:
3683    ID = Intrinsic::hexagon_A2_vabshsat; break;
3684
3685  case Hexagon::BI__builtin_HEXAGON_A2_vabsw:
3686    ID = Intrinsic::hexagon_A2_vabsw; break;
3687
3688  case Hexagon::BI__builtin_HEXAGON_A2_vabswsat:
3689    ID = Intrinsic::hexagon_A2_vabswsat; break;
3690
3691  case Hexagon::BI__builtin_HEXAGON_M2_vabsdiffw:
3692    ID = Intrinsic::hexagon_M2_vabsdiffw; break;
3693
3694  case Hexagon::BI__builtin_HEXAGON_M2_vabsdiffh:
3695    ID = Intrinsic::hexagon_M2_vabsdiffh; break;
3696
3697  case Hexagon::BI__builtin_HEXAGON_A2_vrsadub:
3698    ID = Intrinsic::hexagon_A2_vrsadub; break;
3699
3700  case Hexagon::BI__builtin_HEXAGON_A2_vrsadub_acc:
3701    ID = Intrinsic::hexagon_A2_vrsadub_acc; break;
3702
3703  case Hexagon::BI__builtin_HEXAGON_A2_vavgub:
3704    ID = Intrinsic::hexagon_A2_vavgub; break;
3705
3706  case Hexagon::BI__builtin_HEXAGON_A2_vavguh:
3707    ID = Intrinsic::hexagon_A2_vavguh; break;
3708
3709  case Hexagon::BI__builtin_HEXAGON_A2_vavgh:
3710    ID = Intrinsic::hexagon_A2_vavgh; break;
3711
3712  case Hexagon::BI__builtin_HEXAGON_A2_vnavgh:
3713    ID = Intrinsic::hexagon_A2_vnavgh; break;
3714
3715  case Hexagon::BI__builtin_HEXAGON_A2_vavgw:
3716    ID = Intrinsic::hexagon_A2_vavgw; break;
3717
3718  case Hexagon::BI__builtin_HEXAGON_A2_vnavgw:
3719    ID = Intrinsic::hexagon_A2_vnavgw; break;
3720
3721  case Hexagon::BI__builtin_HEXAGON_A2_vavgwr:
3722    ID = Intrinsic::hexagon_A2_vavgwr; break;
3723
3724  case Hexagon::BI__builtin_HEXAGON_A2_vnavgwr:
3725    ID = Intrinsic::hexagon_A2_vnavgwr; break;
3726
3727  case Hexagon::BI__builtin_HEXAGON_A2_vavgwcr:
3728    ID = Intrinsic::hexagon_A2_vavgwcr; break;
3729
3730  case Hexagon::BI__builtin_HEXAGON_A2_vnavgwcr:
3731    ID = Intrinsic::hexagon_A2_vnavgwcr; break;
3732
3733  case Hexagon::BI__builtin_HEXAGON_A2_vavghcr:
3734    ID = Intrinsic::hexagon_A2_vavghcr; break;
3735
3736  case Hexagon::BI__builtin_HEXAGON_A2_vnavghcr:
3737    ID = Intrinsic::hexagon_A2_vnavghcr; break;
3738
3739  case Hexagon::BI__builtin_HEXAGON_A2_vavguw:
3740    ID = Intrinsic::hexagon_A2_vavguw; break;
3741
3742  case Hexagon::BI__builtin_HEXAGON_A2_vavguwr:
3743    ID = Intrinsic::hexagon_A2_vavguwr; break;
3744
3745  case Hexagon::BI__builtin_HEXAGON_A2_vavgubr:
3746    ID = Intrinsic::hexagon_A2_vavgubr; break;
3747
3748  case Hexagon::BI__builtin_HEXAGON_A2_vavguhr:
3749    ID = Intrinsic::hexagon_A2_vavguhr; break;
3750
3751  case Hexagon::BI__builtin_HEXAGON_A2_vavghr:
3752    ID = Intrinsic::hexagon_A2_vavghr; break;
3753
3754  case Hexagon::BI__builtin_HEXAGON_A2_vnavghr:
3755    ID = Intrinsic::hexagon_A2_vnavghr; break;
3756
3757  case Hexagon::BI__builtin_HEXAGON_A2_vminh:
3758    ID = Intrinsic::hexagon_A2_vminh; break;
3759
3760  case Hexagon::BI__builtin_HEXAGON_A2_vmaxh:
3761    ID = Intrinsic::hexagon_A2_vmaxh; break;
3762
3763  case Hexagon::BI__builtin_HEXAGON_A2_vminub:
3764    ID = Intrinsic::hexagon_A2_vminub; break;
3765
3766  case Hexagon::BI__builtin_HEXAGON_A2_vmaxub:
3767    ID = Intrinsic::hexagon_A2_vmaxub; break;
3768
3769  case Hexagon::BI__builtin_HEXAGON_A2_vminuh:
3770    ID = Intrinsic::hexagon_A2_vminuh; break;
3771
3772  case Hexagon::BI__builtin_HEXAGON_A2_vmaxuh:
3773    ID = Intrinsic::hexagon_A2_vmaxuh; break;
3774
3775  case Hexagon::BI__builtin_HEXAGON_A2_vminw:
3776    ID = Intrinsic::hexagon_A2_vminw; break;
3777
3778  case Hexagon::BI__builtin_HEXAGON_A2_vmaxw:
3779    ID = Intrinsic::hexagon_A2_vmaxw; break;
3780
3781  case Hexagon::BI__builtin_HEXAGON_A2_vminuw:
3782    ID = Intrinsic::hexagon_A2_vminuw; break;
3783
3784  case Hexagon::BI__builtin_HEXAGON_A2_vmaxuw:
3785    ID = Intrinsic::hexagon_A2_vmaxuw; break;
3786
3787  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_r:
3788    ID = Intrinsic::hexagon_S2_asr_r_r; break;
3789
3790  case Hexagon::BI__builtin_HEXAGON_S2_asl_r_r:
3791    ID = Intrinsic::hexagon_S2_asl_r_r; break;
3792
3793  case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_r:
3794    ID = Intrinsic::hexagon_S2_lsr_r_r; break;
3795
3796  case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_r:
3797    ID = Intrinsic::hexagon_S2_lsl_r_r; break;
3798
3799  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_p:
3800    ID = Intrinsic::hexagon_S2_asr_r_p; break;
3801
3802  case Hexagon::BI__builtin_HEXAGON_S2_asl_r_p:
3803    ID = Intrinsic::hexagon_S2_asl_r_p; break;
3804
3805  case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_p:
3806    ID = Intrinsic::hexagon_S2_lsr_r_p; break;
3807
3808  case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_p:
3809    ID = Intrinsic::hexagon_S2_lsl_r_p; break;
3810
3811  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_r_acc:
3812    ID = Intrinsic::hexagon_S2_asr_r_r_acc; break;
3813
3814  case Hexagon::BI__builtin_HEXAGON_S2_asl_r_r_acc:
3815    ID = Intrinsic::hexagon_S2_asl_r_r_acc; break;
3816
3817  case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_r_acc:
3818    ID = Intrinsic::hexagon_S2_lsr_r_r_acc; break;
3819
3820  case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_r_acc:
3821    ID = Intrinsic::hexagon_S2_lsl_r_r_acc; break;
3822
3823  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_p_acc:
3824    ID = Intrinsic::hexagon_S2_asr_r_p_acc; break;
3825
3826  case Hexagon::BI__builtin_HEXAGON_S2_asl_r_p_acc:
3827    ID = Intrinsic::hexagon_S2_asl_r_p_acc; break;
3828
3829  case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_p_acc:
3830    ID = Intrinsic::hexagon_S2_lsr_r_p_acc; break;
3831
3832  case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_p_acc:
3833    ID = Intrinsic::hexagon_S2_lsl_r_p_acc; break;
3834
3835  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_r_nac:
3836    ID = Intrinsic::hexagon_S2_asr_r_r_nac; break;
3837
3838  case Hexagon::BI__builtin_HEXAGON_S2_asl_r_r_nac:
3839    ID = Intrinsic::hexagon_S2_asl_r_r_nac; break;
3840
3841  case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_r_nac:
3842    ID = Intrinsic::hexagon_S2_lsr_r_r_nac; break;
3843
3844  case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_r_nac:
3845    ID = Intrinsic::hexagon_S2_lsl_r_r_nac; break;
3846
3847  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_p_nac:
3848    ID = Intrinsic::hexagon_S2_asr_r_p_nac; break;
3849
3850  case Hexagon::BI__builtin_HEXAGON_S2_asl_r_p_nac:
3851    ID = Intrinsic::hexagon_S2_asl_r_p_nac; break;
3852
3853  case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_p_nac:
3854    ID = Intrinsic::hexagon_S2_lsr_r_p_nac; break;
3855
3856  case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_p_nac:
3857    ID = Intrinsic::hexagon_S2_lsl_r_p_nac; break;
3858
3859  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_r_and:
3860    ID = Intrinsic::hexagon_S2_asr_r_r_and; break;
3861
3862  case Hexagon::BI__builtin_HEXAGON_S2_asl_r_r_and:
3863    ID = Intrinsic::hexagon_S2_asl_r_r_and; break;
3864
3865  case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_r_and:
3866    ID = Intrinsic::hexagon_S2_lsr_r_r_and; break;
3867
3868  case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_r_and:
3869    ID = Intrinsic::hexagon_S2_lsl_r_r_and; break;
3870
3871  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_r_or:
3872    ID = Intrinsic::hexagon_S2_asr_r_r_or; break;
3873
3874  case Hexagon::BI__builtin_HEXAGON_S2_asl_r_r_or:
3875    ID = Intrinsic::hexagon_S2_asl_r_r_or; break;
3876
3877  case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_r_or:
3878    ID = Intrinsic::hexagon_S2_lsr_r_r_or; break;
3879
3880  case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_r_or:
3881    ID = Intrinsic::hexagon_S2_lsl_r_r_or; break;
3882
3883  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_p_and:
3884    ID = Intrinsic::hexagon_S2_asr_r_p_and; break;
3885
3886  case Hexagon::BI__builtin_HEXAGON_S2_asl_r_p_and:
3887    ID = Intrinsic::hexagon_S2_asl_r_p_and; break;
3888
3889  case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_p_and:
3890    ID = Intrinsic::hexagon_S2_lsr_r_p_and; break;
3891
3892  case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_p_and:
3893    ID = Intrinsic::hexagon_S2_lsl_r_p_and; break;
3894
3895  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_p_or:
3896    ID = Intrinsic::hexagon_S2_asr_r_p_or; break;
3897
3898  case Hexagon::BI__builtin_HEXAGON_S2_asl_r_p_or:
3899    ID = Intrinsic::hexagon_S2_asl_r_p_or; break;
3900
3901  case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_p_or:
3902    ID = Intrinsic::hexagon_S2_lsr_r_p_or; break;
3903
3904  case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_p_or:
3905    ID = Intrinsic::hexagon_S2_lsl_r_p_or; break;
3906
3907  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_r_sat:
3908    ID = Intrinsic::hexagon_S2_asr_r_r_sat; break;
3909
3910  case Hexagon::BI__builtin_HEXAGON_S2_asl_r_r_sat:
3911    ID = Intrinsic::hexagon_S2_asl_r_r_sat; break;
3912
3913  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_r:
3914    ID = Intrinsic::hexagon_S2_asr_i_r; break;
3915
3916  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r:
3917    ID = Intrinsic::hexagon_S2_lsr_i_r; break;
3918
3919  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_r:
3920    ID = Intrinsic::hexagon_S2_asl_i_r; break;
3921
3922  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_p:
3923    ID = Intrinsic::hexagon_S2_asr_i_p; break;
3924
3925  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p:
3926    ID = Intrinsic::hexagon_S2_lsr_i_p; break;
3927
3928  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_p:
3929    ID = Intrinsic::hexagon_S2_asl_i_p; break;
3930
3931  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_acc:
3932    ID = Intrinsic::hexagon_S2_asr_i_r_acc; break;
3933
3934  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_acc:
3935    ID = Intrinsic::hexagon_S2_lsr_i_r_acc; break;
3936
3937  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_acc:
3938    ID = Intrinsic::hexagon_S2_asl_i_r_acc; break;
3939
3940  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_acc:
3941    ID = Intrinsic::hexagon_S2_asr_i_p_acc; break;
3942
3943  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_acc:
3944    ID = Intrinsic::hexagon_S2_lsr_i_p_acc; break;
3945
3946  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_acc:
3947    ID = Intrinsic::hexagon_S2_asl_i_p_acc; break;
3948
3949  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_nac:
3950    ID = Intrinsic::hexagon_S2_asr_i_r_nac; break;
3951
3952  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_nac:
3953    ID = Intrinsic::hexagon_S2_lsr_i_r_nac; break;
3954
3955  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_nac:
3956    ID = Intrinsic::hexagon_S2_asl_i_r_nac; break;
3957
3958  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_nac:
3959    ID = Intrinsic::hexagon_S2_asr_i_p_nac; break;
3960
3961  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_nac:
3962    ID = Intrinsic::hexagon_S2_lsr_i_p_nac; break;
3963
3964  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_nac:
3965    ID = Intrinsic::hexagon_S2_asl_i_p_nac; break;
3966
3967  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_xacc:
3968    ID = Intrinsic::hexagon_S2_lsr_i_r_xacc; break;
3969
3970  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_xacc:
3971    ID = Intrinsic::hexagon_S2_asl_i_r_xacc; break;
3972
3973  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_xacc:
3974    ID = Intrinsic::hexagon_S2_lsr_i_p_xacc; break;
3975
3976  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_xacc:
3977    ID = Intrinsic::hexagon_S2_asl_i_p_xacc; break;
3978
3979  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_and:
3980    ID = Intrinsic::hexagon_S2_asr_i_r_and; break;
3981
3982  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_and:
3983    ID = Intrinsic::hexagon_S2_lsr_i_r_and; break;
3984
3985  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_and:
3986    ID = Intrinsic::hexagon_S2_asl_i_r_and; break;
3987
3988  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_or:
3989    ID = Intrinsic::hexagon_S2_asr_i_r_or; break;
3990
3991  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_r_or:
3992    ID = Intrinsic::hexagon_S2_lsr_i_r_or; break;
3993
3994  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_or:
3995    ID = Intrinsic::hexagon_S2_asl_i_r_or; break;
3996
3997  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_and:
3998    ID = Intrinsic::hexagon_S2_asr_i_p_and; break;
3999
4000  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_and:
4001    ID = Intrinsic::hexagon_S2_lsr_i_p_and; break;
4002
4003  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_and:
4004    ID = Intrinsic::hexagon_S2_asl_i_p_and; break;
4005
4006  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_p_or:
4007    ID = Intrinsic::hexagon_S2_asr_i_p_or; break;
4008
4009  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_p_or:
4010    ID = Intrinsic::hexagon_S2_lsr_i_p_or; break;
4011
4012  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_p_or:
4013    ID = Intrinsic::hexagon_S2_asl_i_p_or; break;
4014
4015  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_r_sat:
4016    ID = Intrinsic::hexagon_S2_asl_i_r_sat; break;
4017
4018  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_rnd:
4019    ID = Intrinsic::hexagon_S2_asr_i_r_rnd; break;
4020
4021  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_r_rnd_goodsyntax:
4022    ID = Intrinsic::hexagon_S2_asr_i_r_rnd_goodsyntax; break;
4023
4024  case Hexagon::BI__builtin_HEXAGON_S2_addasl_rrri:
4025    ID = Intrinsic::hexagon_S2_addasl_rrri; break;
4026
4027  case Hexagon::BI__builtin_HEXAGON_S2_valignib:
4028    ID = Intrinsic::hexagon_S2_valignib; break;
4029
4030  case Hexagon::BI__builtin_HEXAGON_S2_valignrb:
4031    ID = Intrinsic::hexagon_S2_valignrb; break;
4032
4033  case Hexagon::BI__builtin_HEXAGON_S2_vspliceib:
4034    ID = Intrinsic::hexagon_S2_vspliceib; break;
4035
4036  case Hexagon::BI__builtin_HEXAGON_S2_vsplicerb:
4037    ID = Intrinsic::hexagon_S2_vsplicerb; break;
4038
4039  case Hexagon::BI__builtin_HEXAGON_S2_vsplatrh:
4040    ID = Intrinsic::hexagon_S2_vsplatrh; break;
4041
4042  case Hexagon::BI__builtin_HEXAGON_S2_vsplatrb:
4043    ID = Intrinsic::hexagon_S2_vsplatrb; break;
4044
4045  case Hexagon::BI__builtin_HEXAGON_S2_insert:
4046    ID = Intrinsic::hexagon_S2_insert; break;
4047
4048  case Hexagon::BI__builtin_HEXAGON_S2_tableidxb_goodsyntax:
4049    ID = Intrinsic::hexagon_S2_tableidxb_goodsyntax; break;
4050
4051  case Hexagon::BI__builtin_HEXAGON_S2_tableidxh_goodsyntax:
4052    ID = Intrinsic::hexagon_S2_tableidxh_goodsyntax; break;
4053
4054  case Hexagon::BI__builtin_HEXAGON_S2_tableidxw_goodsyntax:
4055    ID = Intrinsic::hexagon_S2_tableidxw_goodsyntax; break;
4056
4057  case Hexagon::BI__builtin_HEXAGON_S2_tableidxd_goodsyntax:
4058    ID = Intrinsic::hexagon_S2_tableidxd_goodsyntax; break;
4059
4060  case Hexagon::BI__builtin_HEXAGON_S2_extractu:
4061    ID = Intrinsic::hexagon_S2_extractu; break;
4062
4063  case Hexagon::BI__builtin_HEXAGON_S2_insertp:
4064    ID = Intrinsic::hexagon_S2_insertp; break;
4065
4066  case Hexagon::BI__builtin_HEXAGON_S2_extractup:
4067    ID = Intrinsic::hexagon_S2_extractup; break;
4068
4069  case Hexagon::BI__builtin_HEXAGON_S2_insert_rp:
4070    ID = Intrinsic::hexagon_S2_insert_rp; break;
4071
4072  case Hexagon::BI__builtin_HEXAGON_S2_extractu_rp:
4073    ID = Intrinsic::hexagon_S2_extractu_rp; break;
4074
4075  case Hexagon::BI__builtin_HEXAGON_S2_insertp_rp:
4076    ID = Intrinsic::hexagon_S2_insertp_rp; break;
4077
4078  case Hexagon::BI__builtin_HEXAGON_S2_extractup_rp:
4079    ID = Intrinsic::hexagon_S2_extractup_rp; break;
4080
4081  case Hexagon::BI__builtin_HEXAGON_S2_tstbit_i:
4082    ID = Intrinsic::hexagon_S2_tstbit_i; break;
4083
4084  case Hexagon::BI__builtin_HEXAGON_S2_setbit_i:
4085    ID = Intrinsic::hexagon_S2_setbit_i; break;
4086
4087  case Hexagon::BI__builtin_HEXAGON_S2_togglebit_i:
4088    ID = Intrinsic::hexagon_S2_togglebit_i; break;
4089
4090  case Hexagon::BI__builtin_HEXAGON_S2_clrbit_i:
4091    ID = Intrinsic::hexagon_S2_clrbit_i; break;
4092
4093  case Hexagon::BI__builtin_HEXAGON_S2_tstbit_r:
4094    ID = Intrinsic::hexagon_S2_tstbit_r; break;
4095
4096  case Hexagon::BI__builtin_HEXAGON_S2_setbit_r:
4097    ID = Intrinsic::hexagon_S2_setbit_r; break;
4098
4099  case Hexagon::BI__builtin_HEXAGON_S2_togglebit_r:
4100    ID = Intrinsic::hexagon_S2_togglebit_r; break;
4101
4102  case Hexagon::BI__builtin_HEXAGON_S2_clrbit_r:
4103    ID = Intrinsic::hexagon_S2_clrbit_r; break;
4104
4105  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_vh:
4106    ID = Intrinsic::hexagon_S2_asr_i_vh; break;
4107
4108  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_vh:
4109    ID = Intrinsic::hexagon_S2_lsr_i_vh; break;
4110
4111  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_vh:
4112    ID = Intrinsic::hexagon_S2_asl_i_vh; break;
4113
4114  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_vh:
4115    ID = Intrinsic::hexagon_S2_asr_r_vh; break;
4116
4117  case Hexagon::BI__builtin_HEXAGON_S2_asl_r_vh:
4118    ID = Intrinsic::hexagon_S2_asl_r_vh; break;
4119
4120  case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_vh:
4121    ID = Intrinsic::hexagon_S2_lsr_r_vh; break;
4122
4123  case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_vh:
4124    ID = Intrinsic::hexagon_S2_lsl_r_vh; break;
4125
4126  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_vw:
4127    ID = Intrinsic::hexagon_S2_asr_i_vw; break;
4128
4129  case Hexagon::BI__builtin_HEXAGON_S2_asr_i_svw_trun:
4130    ID = Intrinsic::hexagon_S2_asr_i_svw_trun; break;
4131
4132  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_svw_trun:
4133    ID = Intrinsic::hexagon_S2_asr_r_svw_trun; break;
4134
4135  case Hexagon::BI__builtin_HEXAGON_S2_lsr_i_vw:
4136    ID = Intrinsic::hexagon_S2_lsr_i_vw; break;
4137
4138  case Hexagon::BI__builtin_HEXAGON_S2_asl_i_vw:
4139    ID = Intrinsic::hexagon_S2_asl_i_vw; break;
4140
4141  case Hexagon::BI__builtin_HEXAGON_S2_asr_r_vw:
4142    ID = Intrinsic::hexagon_S2_asr_r_vw; break;
4143
4144  case Hexagon::BI__builtin_HEXAGON_S2_asl_r_vw:
4145    ID = Intrinsic::hexagon_S2_asl_r_vw; break;
4146
4147  case Hexagon::BI__builtin_HEXAGON_S2_lsr_r_vw:
4148    ID = Intrinsic::hexagon_S2_lsr_r_vw; break;
4149
4150  case Hexagon::BI__builtin_HEXAGON_S2_lsl_r_vw:
4151    ID = Intrinsic::hexagon_S2_lsl_r_vw; break;
4152
4153  case Hexagon::BI__builtin_HEXAGON_S2_vrndpackwh:
4154    ID = Intrinsic::hexagon_S2_vrndpackwh; break;
4155
4156  case Hexagon::BI__builtin_HEXAGON_S2_vrndpackwhs:
4157    ID = Intrinsic::hexagon_S2_vrndpackwhs; break;
4158
4159  case Hexagon::BI__builtin_HEXAGON_S2_vsxtbh:
4160    ID = Intrinsic::hexagon_S2_vsxtbh; break;
4161
4162  case Hexagon::BI__builtin_HEXAGON_S2_vzxtbh:
4163    ID = Intrinsic::hexagon_S2_vzxtbh; break;
4164
4165  case Hexagon::BI__builtin_HEXAGON_S2_vsathub:
4166    ID = Intrinsic::hexagon_S2_vsathub; break;
4167
4168  case Hexagon::BI__builtin_HEXAGON_S2_svsathub:
4169    ID = Intrinsic::hexagon_S2_svsathub; break;
4170
4171  case Hexagon::BI__builtin_HEXAGON_S2_svsathb:
4172    ID = Intrinsic::hexagon_S2_svsathb; break;
4173
4174  case Hexagon::BI__builtin_HEXAGON_S2_vsathb:
4175    ID = Intrinsic::hexagon_S2_vsathb; break;
4176
4177  case Hexagon::BI__builtin_HEXAGON_S2_vtrunohb:
4178    ID = Intrinsic::hexagon_S2_vtrunohb; break;
4179
4180  case Hexagon::BI__builtin_HEXAGON_S2_vtrunewh:
4181    ID = Intrinsic::hexagon_S2_vtrunewh; break;
4182
4183  case Hexagon::BI__builtin_HEXAGON_S2_vtrunowh:
4184    ID = Intrinsic::hexagon_S2_vtrunowh; break;
4185
4186  case Hexagon::BI__builtin_HEXAGON_S2_vtrunehb:
4187    ID = Intrinsic::hexagon_S2_vtrunehb; break;
4188
4189  case Hexagon::BI__builtin_HEXAGON_S2_vsxthw:
4190    ID = Intrinsic::hexagon_S2_vsxthw; break;
4191
4192  case Hexagon::BI__builtin_HEXAGON_S2_vzxthw:
4193    ID = Intrinsic::hexagon_S2_vzxthw; break;
4194
4195  case Hexagon::BI__builtin_HEXAGON_S2_vsatwh:
4196    ID = Intrinsic::hexagon_S2_vsatwh; break;
4197
4198  case Hexagon::BI__builtin_HEXAGON_S2_vsatwuh:
4199    ID = Intrinsic::hexagon_S2_vsatwuh; break;
4200
4201  case Hexagon::BI__builtin_HEXAGON_S2_packhl:
4202    ID = Intrinsic::hexagon_S2_packhl; break;
4203
4204  case Hexagon::BI__builtin_HEXAGON_A2_swiz:
4205    ID = Intrinsic::hexagon_A2_swiz; break;
4206
4207  case Hexagon::BI__builtin_HEXAGON_S2_vsathub_nopack:
4208    ID = Intrinsic::hexagon_S2_vsathub_nopack; break;
4209
4210  case Hexagon::BI__builtin_HEXAGON_S2_vsathb_nopack:
4211    ID = Intrinsic::hexagon_S2_vsathb_nopack; break;
4212
4213  case Hexagon::BI__builtin_HEXAGON_S2_vsatwh_nopack:
4214    ID = Intrinsic::hexagon_S2_vsatwh_nopack; break;
4215
4216  case Hexagon::BI__builtin_HEXAGON_S2_vsatwuh_nopack:
4217    ID = Intrinsic::hexagon_S2_vsatwuh_nopack; break;
4218
4219  case Hexagon::BI__builtin_HEXAGON_S2_shuffob:
4220    ID = Intrinsic::hexagon_S2_shuffob; break;
4221
4222  case Hexagon::BI__builtin_HEXAGON_S2_shuffeb:
4223    ID = Intrinsic::hexagon_S2_shuffeb; break;
4224
4225  case Hexagon::BI__builtin_HEXAGON_S2_shuffoh:
4226    ID = Intrinsic::hexagon_S2_shuffoh; break;
4227
4228  case Hexagon::BI__builtin_HEXAGON_S2_shuffeh:
4229    ID = Intrinsic::hexagon_S2_shuffeh; break;
4230
4231  case Hexagon::BI__builtin_HEXAGON_S2_parityp:
4232    ID = Intrinsic::hexagon_S2_parityp; break;
4233
4234  case Hexagon::BI__builtin_HEXAGON_S2_lfsp:
4235    ID = Intrinsic::hexagon_S2_lfsp; break;
4236
4237  case Hexagon::BI__builtin_HEXAGON_S2_clbnorm:
4238    ID = Intrinsic::hexagon_S2_clbnorm; break;
4239
4240  case Hexagon::BI__builtin_HEXAGON_S2_clb:
4241    ID = Intrinsic::hexagon_S2_clb; break;
4242
4243  case Hexagon::BI__builtin_HEXAGON_S2_cl0:
4244    ID = Intrinsic::hexagon_S2_cl0; break;
4245
4246  case Hexagon::BI__builtin_HEXAGON_S2_cl1:
4247    ID = Intrinsic::hexagon_S2_cl1; break;
4248
4249  case Hexagon::BI__builtin_HEXAGON_S2_clbp:
4250    ID = Intrinsic::hexagon_S2_clbp; break;
4251
4252  case Hexagon::BI__builtin_HEXAGON_S2_cl0p:
4253    ID = Intrinsic::hexagon_S2_cl0p; break;
4254
4255  case Hexagon::BI__builtin_HEXAGON_S2_cl1p:
4256    ID = Intrinsic::hexagon_S2_cl1p; break;
4257
4258  case Hexagon::BI__builtin_HEXAGON_S2_brev:
4259    ID = Intrinsic::hexagon_S2_brev; break;
4260
4261  case Hexagon::BI__builtin_HEXAGON_S2_ct0:
4262    ID = Intrinsic::hexagon_S2_ct0; break;
4263
4264  case Hexagon::BI__builtin_HEXAGON_S2_ct1:
4265    ID = Intrinsic::hexagon_S2_ct1; break;
4266
4267  case Hexagon::BI__builtin_HEXAGON_S2_interleave:
4268    ID = Intrinsic::hexagon_S2_interleave; break;
4269
4270  case Hexagon::BI__builtin_HEXAGON_S2_deinterleave:
4271    ID = Intrinsic::hexagon_S2_deinterleave; break;
4272
4273  case Hexagon::BI__builtin_SI_to_SXTHI_asrh:
4274    ID = Intrinsic::hexagon_SI_to_SXTHI_asrh; break;
4275
4276  case Hexagon::BI__builtin_HEXAGON_A4_orn:
4277    ID = Intrinsic::hexagon_A4_orn; break;
4278
4279  case Hexagon::BI__builtin_HEXAGON_A4_andn:
4280    ID = Intrinsic::hexagon_A4_andn; break;
4281
4282  case Hexagon::BI__builtin_HEXAGON_A4_ornp:
4283    ID = Intrinsic::hexagon_A4_ornp; break;
4284
4285  case Hexagon::BI__builtin_HEXAGON_A4_andnp:
4286    ID = Intrinsic::hexagon_A4_andnp; break;
4287
4288  case Hexagon::BI__builtin_HEXAGON_A4_combineir:
4289    ID = Intrinsic::hexagon_A4_combineir; break;
4290
4291  case Hexagon::BI__builtin_HEXAGON_A4_combineri:
4292    ID = Intrinsic::hexagon_A4_combineri; break;
4293
4294  case Hexagon::BI__builtin_HEXAGON_C4_cmpneqi:
4295    ID = Intrinsic::hexagon_C4_cmpneqi; break;
4296
4297  case Hexagon::BI__builtin_HEXAGON_C4_cmpneq:
4298    ID = Intrinsic::hexagon_C4_cmpneq; break;
4299
4300  case Hexagon::BI__builtin_HEXAGON_C4_cmpltei:
4301    ID = Intrinsic::hexagon_C4_cmpltei; break;
4302
4303  case Hexagon::BI__builtin_HEXAGON_C4_cmplte:
4304    ID = Intrinsic::hexagon_C4_cmplte; break;
4305
4306  case Hexagon::BI__builtin_HEXAGON_C4_cmplteui:
4307    ID = Intrinsic::hexagon_C4_cmplteui; break;
4308
4309  case Hexagon::BI__builtin_HEXAGON_C4_cmplteu:
4310    ID = Intrinsic::hexagon_C4_cmplteu; break;
4311
4312  case Hexagon::BI__builtin_HEXAGON_A4_rcmpneq:
4313    ID = Intrinsic::hexagon_A4_rcmpneq; break;
4314
4315  case Hexagon::BI__builtin_HEXAGON_A4_rcmpneqi:
4316    ID = Intrinsic::hexagon_A4_rcmpneqi; break;
4317
4318  case Hexagon::BI__builtin_HEXAGON_A4_rcmpeq:
4319    ID = Intrinsic::hexagon_A4_rcmpeq; break;
4320
4321  case Hexagon::BI__builtin_HEXAGON_A4_rcmpeqi:
4322    ID = Intrinsic::hexagon_A4_rcmpeqi; break;
4323
4324  case Hexagon::BI__builtin_HEXAGON_C4_fastcorner9:
4325    ID = Intrinsic::hexagon_C4_fastcorner9; break;
4326
4327  case Hexagon::BI__builtin_HEXAGON_C4_fastcorner9_not:
4328    ID = Intrinsic::hexagon_C4_fastcorner9_not; break;
4329
4330  case Hexagon::BI__builtin_HEXAGON_C4_and_andn:
4331    ID = Intrinsic::hexagon_C4_and_andn; break;
4332
4333  case Hexagon::BI__builtin_HEXAGON_C4_and_and:
4334    ID = Intrinsic::hexagon_C4_and_and; break;
4335
4336  case Hexagon::BI__builtin_HEXAGON_C4_and_orn:
4337    ID = Intrinsic::hexagon_C4_and_orn; break;
4338
4339  case Hexagon::BI__builtin_HEXAGON_C4_and_or:
4340    ID = Intrinsic::hexagon_C4_and_or; break;
4341
4342  case Hexagon::BI__builtin_HEXAGON_C4_or_andn:
4343    ID = Intrinsic::hexagon_C4_or_andn; break;
4344
4345  case Hexagon::BI__builtin_HEXAGON_C4_or_and:
4346    ID = Intrinsic::hexagon_C4_or_and; break;
4347
4348  case Hexagon::BI__builtin_HEXAGON_C4_or_orn:
4349    ID = Intrinsic::hexagon_C4_or_orn; break;
4350
4351  case Hexagon::BI__builtin_HEXAGON_C4_or_or:
4352    ID = Intrinsic::hexagon_C4_or_or; break;
4353
4354  case Hexagon::BI__builtin_HEXAGON_S4_addaddi:
4355    ID = Intrinsic::hexagon_S4_addaddi; break;
4356
4357  case Hexagon::BI__builtin_HEXAGON_S4_subaddi:
4358    ID = Intrinsic::hexagon_S4_subaddi; break;
4359
4360  case Hexagon::BI__builtin_HEXAGON_M4_xor_xacc:
4361    ID = Intrinsic::hexagon_M4_xor_xacc; break;
4362
4363  case Hexagon::BI__builtin_HEXAGON_M4_and_and:
4364    ID = Intrinsic::hexagon_M4_and_and; break;
4365
4366  case Hexagon::BI__builtin_HEXAGON_M4_and_or:
4367    ID = Intrinsic::hexagon_M4_and_or; break;
4368
4369  case Hexagon::BI__builtin_HEXAGON_M4_and_xor:
4370    ID = Intrinsic::hexagon_M4_and_xor; break;
4371
4372  case Hexagon::BI__builtin_HEXAGON_M4_and_andn:
4373    ID = Intrinsic::hexagon_M4_and_andn; break;
4374
4375  case Hexagon::BI__builtin_HEXAGON_M4_xor_and:
4376    ID = Intrinsic::hexagon_M4_xor_and; break;
4377
4378  case Hexagon::BI__builtin_HEXAGON_M4_xor_or:
4379    ID = Intrinsic::hexagon_M4_xor_or; break;
4380
4381  case Hexagon::BI__builtin_HEXAGON_M4_xor_andn:
4382    ID = Intrinsic::hexagon_M4_xor_andn; break;
4383
4384  case Hexagon::BI__builtin_HEXAGON_M4_or_and:
4385    ID = Intrinsic::hexagon_M4_or_and; break;
4386
4387  case Hexagon::BI__builtin_HEXAGON_M4_or_or:
4388    ID = Intrinsic::hexagon_M4_or_or; break;
4389
4390  case Hexagon::BI__builtin_HEXAGON_M4_or_xor:
4391    ID = Intrinsic::hexagon_M4_or_xor; break;
4392
4393  case Hexagon::BI__builtin_HEXAGON_M4_or_andn:
4394    ID = Intrinsic::hexagon_M4_or_andn; break;
4395
4396  case Hexagon::BI__builtin_HEXAGON_S4_or_andix:
4397    ID = Intrinsic::hexagon_S4_or_andix; break;
4398
4399  case Hexagon::BI__builtin_HEXAGON_S4_or_andi:
4400    ID = Intrinsic::hexagon_S4_or_andi; break;
4401
4402  case Hexagon::BI__builtin_HEXAGON_S4_or_ori:
4403    ID = Intrinsic::hexagon_S4_or_ori; break;
4404
4405  case Hexagon::BI__builtin_HEXAGON_A4_modwrapu:
4406    ID = Intrinsic::hexagon_A4_modwrapu; break;
4407
4408  case Hexagon::BI__builtin_HEXAGON_A4_cround_rr:
4409    ID = Intrinsic::hexagon_A4_cround_rr; break;
4410
4411  case Hexagon::BI__builtin_HEXAGON_A4_round_ri:
4412    ID = Intrinsic::hexagon_A4_round_ri; break;
4413
4414  case Hexagon::BI__builtin_HEXAGON_A4_round_rr:
4415    ID = Intrinsic::hexagon_A4_round_rr; break;
4416
4417  case Hexagon::BI__builtin_HEXAGON_A4_round_ri_sat:
4418    ID = Intrinsic::hexagon_A4_round_ri_sat; break;
4419
4420  case Hexagon::BI__builtin_HEXAGON_A4_round_rr_sat:
4421    ID = Intrinsic::hexagon_A4_round_rr_sat; break;
4422
4423  }
4424
4425  llvm::Function *F = CGM.getIntrinsic(ID);
4426  return Builder.CreateCall(F, Ops, "");
4427}
4428
4429Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID,
4430                                           const CallExpr *E) {
4431  SmallVector<Value*, 4> Ops;
4432
4433  for (unsigned i = 0, e = E->getNumArgs(); i != e; i++)
4434    Ops.push_back(EmitScalarExpr(E->getArg(i)));
4435
4436  Intrinsic::ID ID = Intrinsic::not_intrinsic;
4437
4438  switch (BuiltinID) {
4439  default: return 0;
4440
4441  // vec_ld, vec_lvsl, vec_lvsr
4442  case PPC::BI__builtin_altivec_lvx:
4443  case PPC::BI__builtin_altivec_lvxl:
4444  case PPC::BI__builtin_altivec_lvebx:
4445  case PPC::BI__builtin_altivec_lvehx:
4446  case PPC::BI__builtin_altivec_lvewx:
4447  case PPC::BI__builtin_altivec_lvsl:
4448  case PPC::BI__builtin_altivec_lvsr:
4449  {
4450    Ops[1] = Builder.CreateBitCast(Ops[1], Int8PtrTy);
4451
4452    Ops[0] = Builder.CreateGEP(Ops[1], Ops[0]);
4453    Ops.pop_back();
4454
4455    switch (BuiltinID) {
4456    default: llvm_unreachable("Unsupported ld/lvsl/lvsr intrinsic!");
4457    case PPC::BI__builtin_altivec_lvx:
4458      ID = Intrinsic::ppc_altivec_lvx;
4459      break;
4460    case PPC::BI__builtin_altivec_lvxl:
4461      ID = Intrinsic::ppc_altivec_lvxl;
4462      break;
4463    case PPC::BI__builtin_altivec_lvebx:
4464      ID = Intrinsic::ppc_altivec_lvebx;
4465      break;
4466    case PPC::BI__builtin_altivec_lvehx:
4467      ID = Intrinsic::ppc_altivec_lvehx;
4468      break;
4469    case PPC::BI__builtin_altivec_lvewx:
4470      ID = Intrinsic::ppc_altivec_lvewx;
4471      break;
4472    case PPC::BI__builtin_altivec_lvsl:
4473      ID = Intrinsic::ppc_altivec_lvsl;
4474      break;
4475    case PPC::BI__builtin_altivec_lvsr:
4476      ID = Intrinsic::ppc_altivec_lvsr;
4477      break;
4478    }
4479    llvm::Function *F = CGM.getIntrinsic(ID);
4480    return Builder.CreateCall(F, Ops, "");
4481  }
4482
4483  // vec_st
4484  case PPC::BI__builtin_altivec_stvx:
4485  case PPC::BI__builtin_altivec_stvxl:
4486  case PPC::BI__builtin_altivec_stvebx:
4487  case PPC::BI__builtin_altivec_stvehx:
4488  case PPC::BI__builtin_altivec_stvewx:
4489  {
4490    Ops[2] = Builder.CreateBitCast(Ops[2], Int8PtrTy);
4491    Ops[1] = Builder.CreateGEP(Ops[2], Ops[1]);
4492    Ops.pop_back();
4493
4494    switch (BuiltinID) {
4495    default: llvm_unreachable("Unsupported st intrinsic!");
4496    case PPC::BI__builtin_altivec_stvx:
4497      ID = Intrinsic::ppc_altivec_stvx;
4498      break;
4499    case PPC::BI__builtin_altivec_stvxl:
4500      ID = Intrinsic::ppc_altivec_stvxl;
4501      break;
4502    case PPC::BI__builtin_altivec_stvebx:
4503      ID = Intrinsic::ppc_altivec_stvebx;
4504      break;
4505    case PPC::BI__builtin_altivec_stvehx:
4506      ID = Intrinsic::ppc_altivec_stvehx;
4507      break;
4508    case PPC::BI__builtin_altivec_stvewx:
4509      ID = Intrinsic::ppc_altivec_stvewx;
4510      break;
4511    }
4512    llvm::Function *F = CGM.getIntrinsic(ID);
4513    return Builder.CreateCall(F, Ops, "");
4514  }
4515  }
4516  return 0;
4517}
4518