1d1c09396e629a9fef1939f7ab7dfb69455d82fb8Ben Cheng/* 2d1c09396e629a9fef1939f7ab7dfb69455d82fb8Ben Cheng * arch/arm/include/asm/byteorder.h 3d1c09396e629a9fef1939f7ab7dfb69455d82fb8Ben Cheng * 4d1c09396e629a9fef1939f7ab7dfb69455d82fb8Ben Cheng * ARM Endian-ness. In little endian mode, the data bus is connected such 5d1c09396e629a9fef1939f7ab7dfb69455d82fb8Ben Cheng * that byte accesses appear as: 6d1c09396e629a9fef1939f7ab7dfb69455d82fb8Ben Cheng * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31 7d1c09396e629a9fef1939f7ab7dfb69455d82fb8Ben Cheng * and word accesses (data or instruction) appear as: 8d1c09396e629a9fef1939f7ab7dfb69455d82fb8Ben Cheng * d0...d31 9d1c09396e629a9fef1939f7ab7dfb69455d82fb8Ben Cheng * 10d1c09396e629a9fef1939f7ab7dfb69455d82fb8Ben Cheng * When in big endian mode, byte accesses appear as: 11d1c09396e629a9fef1939f7ab7dfb69455d82fb8Ben Cheng * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7 12d1c09396e629a9fef1939f7ab7dfb69455d82fb8Ben Cheng * and word accesses (data or instruction) appear as: 13d1c09396e629a9fef1939f7ab7dfb69455d82fb8Ben Cheng * d0...d31 14d1c09396e629a9fef1939f7ab7dfb69455d82fb8Ben Cheng */ 15d1c09396e629a9fef1939f7ab7dfb69455d82fb8Ben Cheng#ifndef __ASM_ARM_BYTEORDER_H 16d1c09396e629a9fef1939f7ab7dfb69455d82fb8Ben Cheng#define __ASM_ARM_BYTEORDER_H 17d1c09396e629a9fef1939f7ab7dfb69455d82fb8Ben Cheng 18d1c09396e629a9fef1939f7ab7dfb69455d82fb8Ben Cheng#ifdef __ARMEB__ 19d1c09396e629a9fef1939f7ab7dfb69455d82fb8Ben Cheng#include <linux/byteorder/big_endian.h> 20d1c09396e629a9fef1939f7ab7dfb69455d82fb8Ben Cheng#else 21d1c09396e629a9fef1939f7ab7dfb69455d82fb8Ben Cheng#include <linux/byteorder/little_endian.h> 22d1c09396e629a9fef1939f7ab7dfb69455d82fb8Ben Cheng#endif 23d1c09396e629a9fef1939f7ab7dfb69455d82fb8Ben Cheng 24d1c09396e629a9fef1939f7ab7dfb69455d82fb8Ben Cheng#endif 25d1c09396e629a9fef1939f7ab7dfb69455d82fb8Ben Cheng 26