1/****************************************************************************** 2 * 3 * Copyright (C) 2015 The Android Open Source Project 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at: 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 ***************************************************************************** 18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore 19*/ 20 21/*****************************************************************************/ 22/* */ 23/* File Name : ih264d_api.c */ 24/* */ 25/* Description : Has all API related functions */ 26/* */ 27/* */ 28/* List of Functions : api_check_struct_sanity */ 29/* ih264d_set_processor */ 30/* ih264d_create */ 31/* ih264d_delete */ 32/* ih264d_init */ 33/* ih264d_map_error */ 34/* ih264d_video_decode */ 35/* ih264d_get_version */ 36/* ih264d_get_display_frame */ 37/* ih264d_set_display_frame */ 38/* ih264d_set_flush_mode */ 39/* ih264d_get_status */ 40/* ih264d_get_buf_info */ 41/* ih264d_set_params */ 42/* ih264d_set_default_params */ 43/* ih264d_reset */ 44/* ih264d_ctl */ 45/* ih264d_rel_display_frame */ 46/* ih264d_set_degrade */ 47/* ih264d_get_frame_dimensions */ 48/* ih264d_set_num_cores */ 49/* ih264d_fill_output_struct_from_context */ 50/* ih264d_api_function */ 51/* */ 52/* Issues / Problems : None */ 53/* */ 54/* Revision History : */ 55/* */ 56/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 57/* 14 10 2008 100356(SKV) Draft */ 58/* */ 59/*****************************************************************************/ 60#include "ih264_typedefs.h" 61#include "ih264_macros.h" 62#include "ih264_platform_macros.h" 63#include "ih264d_tables.h" 64#include "iv.h" 65#include "ivd.h" 66#include "ih264d.h" 67#include "ih264d_defs.h" 68 69#include <string.h> 70#include <limits.h> 71#include <stddef.h> 72 73#include "ih264d_inter_pred.h" 74 75#include "ih264d_structs.h" 76#include "ih264d_nal.h" 77#include "ih264d_error_handler.h" 78 79#include "ih264d_defs.h" 80 81#include "ithread.h" 82#include "ih264d_parse_slice.h" 83#include "ih264d_function_selector.h" 84#include "ih264_error.h" 85#include "ih264_disp_mgr.h" 86#include "ih264_buf_mgr.h" 87#include "ih264d_deblocking.h" 88#include "ih264d_parse_cavlc.h" 89#include "ih264d_parse_cabac.h" 90#include "ih264d_utils.h" 91#include "ih264d_format_conv.h" 92#include "ih264d_parse_headers.h" 93#include "ih264d_thread_compute_bs.h" 94#include <assert.h> 95 96 97/*********************/ 98/* Codec Versioning */ 99/*********************/ 100//Move this to where it is used 101#define CODEC_NAME "H264VDEC" 102#define CODEC_RELEASE_TYPE "production" 103#define CODEC_RELEASE_VER "05.00" 104#define CODEC_VENDOR "ITTIAM" 105#define MAXVERSION_STRLEN 511 106#ifdef __ANDROID__ 107#define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \ 108 snprintf(version_string, MAXVERSION_STRLEN, \ 109 "@(#)Id:%s_%s Ver:%s Released by %s", \ 110 codec_name, codec_release_type, codec_release_ver, codec_vendor) 111#else 112#define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \ 113 snprintf(version_string, MAXVERSION_STRLEN, \ 114 "@(#)Id:%s_%s Ver:%s Released by %s Build: %s @ %s", \ 115 codec_name, codec_release_type, codec_release_ver, codec_vendor, __DATE__, __TIME__) 116#endif 117 118 119#define MIN_IN_BUFS 1 120#define MIN_OUT_BUFS_420 3 121#define MIN_OUT_BUFS_422ILE 1 122#define MIN_OUT_BUFS_RGB565 1 123#define MIN_OUT_BUFS_420SP 2 124 125#define NUM_FRAMES_LIMIT_ENABLED 0 126 127#if NUM_FRAMES_LIMIT_ENABLED 128#define NUM_FRAMES_LIMIT 10000 129#else 130#define NUM_FRAMES_LIMIT 0x7FFFFFFF 131#endif 132 133 134UWORD32 ih264d_get_extra_mem_external(UWORD32 width, UWORD32 height); 135WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl, 136 void *pv_api_ip, 137 void *pv_api_op); 138WORD32 ih264d_get_vui_params(iv_obj_t *dec_hdl, 139 void *pv_api_ip, 140 void *pv_api_op); 141 142WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op); 143 144WORD32 ih264d_deblock_display(dec_struct_t *ps_dec); 145 146void ih264d_signal_decode_thread(dec_struct_t *ps_dec); 147 148void ih264d_signal_bs_deblk_thread(dec_struct_t *ps_dec); 149void ih264d_decode_picture_thread(dec_struct_t *ps_dec); 150 151WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj, 152 void *pv_api_ip, 153 void *pv_api_op); 154 155void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec, 156 ivd_video_decode_op_t *ps_dec_op); 157 158static IV_API_CALL_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle, 159 void *pv_api_ip, 160 void *pv_api_op) 161{ 162 IVD_API_COMMAND_TYPE_T e_cmd; 163 UWORD32 *pu4_api_ip; 164 UWORD32 *pu4_api_op; 165 UWORD32 i, j; 166 167 if(NULL == pv_api_op) 168 return (IV_FAIL); 169 170 if(NULL == pv_api_ip) 171 return (IV_FAIL); 172 173 pu4_api_ip = (UWORD32 *)pv_api_ip; 174 pu4_api_op = (UWORD32 *)pv_api_op; 175 e_cmd = *(pu4_api_ip + 1); 176 177 /* error checks on handle */ 178 switch((WORD32)e_cmd) 179 { 180 case IVD_CMD_CREATE: 181 break; 182 183 case IVD_CMD_REL_DISPLAY_FRAME: 184 case IVD_CMD_SET_DISPLAY_FRAME: 185 case IVD_CMD_GET_DISPLAY_FRAME: 186 case IVD_CMD_VIDEO_DECODE: 187 case IVD_CMD_DELETE: 188 case IVD_CMD_VIDEO_CTL: 189 if(ps_handle == NULL) 190 { 191 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 192 *(pu4_api_op + 1) |= IVD_HANDLE_NULL; 193 return IV_FAIL; 194 } 195 196 if(ps_handle->u4_size != sizeof(iv_obj_t)) 197 { 198 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 199 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT; 200 return IV_FAIL; 201 } 202 203 if(ps_handle->pv_fxns != ih264d_api_function) 204 { 205 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 206 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL; 207 return IV_FAIL; 208 } 209 210 if(ps_handle->pv_codec_handle == NULL) 211 { 212 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 213 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL; 214 return IV_FAIL; 215 } 216 break; 217 default: 218 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 219 *(pu4_api_op + 1) |= IVD_INVALID_API_CMD; 220 return IV_FAIL; 221 } 222 223 switch((WORD32)e_cmd) 224 { 225 case IVD_CMD_CREATE: 226 { 227 ih264d_create_ip_t *ps_ip = (ih264d_create_ip_t *)pv_api_ip; 228 ih264d_create_op_t *ps_op = (ih264d_create_op_t *)pv_api_op; 229 230 231 ps_op->s_ivd_create_op_t.u4_error_code = 0; 232 233 if((ps_ip->s_ivd_create_ip_t.u4_size > sizeof(ih264d_create_ip_t)) 234 || (ps_ip->s_ivd_create_ip_t.u4_size 235 < sizeof(ivd_create_ip_t))) 236 { 237 ps_op->s_ivd_create_op_t.u4_error_code |= 1 238 << IVD_UNSUPPORTEDPARAM; 239 ps_op->s_ivd_create_op_t.u4_error_code |= 240 IVD_IP_API_STRUCT_SIZE_INCORRECT; 241 H264_DEC_DEBUG_PRINT("\n"); 242 return (IV_FAIL); 243 } 244 245 if((ps_op->s_ivd_create_op_t.u4_size != sizeof(ih264d_create_op_t)) 246 && (ps_op->s_ivd_create_op_t.u4_size 247 != sizeof(ivd_create_op_t))) 248 { 249 ps_op->s_ivd_create_op_t.u4_error_code |= 1 250 << IVD_UNSUPPORTEDPARAM; 251 ps_op->s_ivd_create_op_t.u4_error_code |= 252 IVD_OP_API_STRUCT_SIZE_INCORRECT; 253 H264_DEC_DEBUG_PRINT("\n"); 254 return (IV_FAIL); 255 } 256 257 258 if((ps_ip->s_ivd_create_ip_t.e_output_format != IV_YUV_420P) 259 && (ps_ip->s_ivd_create_ip_t.e_output_format 260 != IV_YUV_422ILE) 261 && (ps_ip->s_ivd_create_ip_t.e_output_format 262 != IV_RGB_565) 263 && (ps_ip->s_ivd_create_ip_t.e_output_format 264 != IV_YUV_420SP_UV) 265 && (ps_ip->s_ivd_create_ip_t.e_output_format 266 != IV_YUV_420SP_VU)) 267 { 268 ps_op->s_ivd_create_op_t.u4_error_code |= 1 269 << IVD_UNSUPPORTEDPARAM; 270 ps_op->s_ivd_create_op_t.u4_error_code |= 271 IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED; 272 H264_DEC_DEBUG_PRINT("\n"); 273 return (IV_FAIL); 274 } 275 276 } 277 break; 278 279 case IVD_CMD_GET_DISPLAY_FRAME: 280 { 281 ih264d_get_display_frame_ip_t *ps_ip = 282 (ih264d_get_display_frame_ip_t *)pv_api_ip; 283 ih264d_get_display_frame_op_t *ps_op = 284 (ih264d_get_display_frame_op_t *)pv_api_op; 285 286 ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0; 287 288 if((ps_ip->s_ivd_get_display_frame_ip_t.u4_size 289 != sizeof(ih264d_get_display_frame_ip_t)) 290 && (ps_ip->s_ivd_get_display_frame_ip_t.u4_size 291 != sizeof(ivd_get_display_frame_ip_t))) 292 { 293 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 294 << IVD_UNSUPPORTEDPARAM; 295 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 296 IVD_IP_API_STRUCT_SIZE_INCORRECT; 297 return (IV_FAIL); 298 } 299 300 if((ps_op->s_ivd_get_display_frame_op_t.u4_size 301 != sizeof(ih264d_get_display_frame_op_t)) 302 && (ps_op->s_ivd_get_display_frame_op_t.u4_size 303 != sizeof(ivd_get_display_frame_op_t))) 304 { 305 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 306 << IVD_UNSUPPORTEDPARAM; 307 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 308 IVD_OP_API_STRUCT_SIZE_INCORRECT; 309 return (IV_FAIL); 310 } 311 } 312 break; 313 314 case IVD_CMD_REL_DISPLAY_FRAME: 315 { 316 ih264d_rel_display_frame_ip_t *ps_ip = 317 (ih264d_rel_display_frame_ip_t *)pv_api_ip; 318 ih264d_rel_display_frame_op_t *ps_op = 319 (ih264d_rel_display_frame_op_t *)pv_api_op; 320 321 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0; 322 323 if((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size 324 != sizeof(ih264d_rel_display_frame_ip_t)) 325 && (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size 326 != sizeof(ivd_rel_display_frame_ip_t))) 327 { 328 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 329 << IVD_UNSUPPORTEDPARAM; 330 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 331 IVD_IP_API_STRUCT_SIZE_INCORRECT; 332 return (IV_FAIL); 333 } 334 335 if((ps_op->s_ivd_rel_display_frame_op_t.u4_size 336 != sizeof(ih264d_rel_display_frame_op_t)) 337 && (ps_op->s_ivd_rel_display_frame_op_t.u4_size 338 != sizeof(ivd_rel_display_frame_op_t))) 339 { 340 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 341 << IVD_UNSUPPORTEDPARAM; 342 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 343 IVD_OP_API_STRUCT_SIZE_INCORRECT; 344 return (IV_FAIL); 345 } 346 347 } 348 break; 349 350 case IVD_CMD_SET_DISPLAY_FRAME: 351 { 352 ih264d_set_display_frame_ip_t *ps_ip = 353 (ih264d_set_display_frame_ip_t *)pv_api_ip; 354 ih264d_set_display_frame_op_t *ps_op = 355 (ih264d_set_display_frame_op_t *)pv_api_op; 356 UWORD32 j; 357 358 ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0; 359 360 if((ps_ip->s_ivd_set_display_frame_ip_t.u4_size 361 != sizeof(ih264d_set_display_frame_ip_t)) 362 && (ps_ip->s_ivd_set_display_frame_ip_t.u4_size 363 != sizeof(ivd_set_display_frame_ip_t))) 364 { 365 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 366 << IVD_UNSUPPORTEDPARAM; 367 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 368 IVD_IP_API_STRUCT_SIZE_INCORRECT; 369 return (IV_FAIL); 370 } 371 372 if((ps_op->s_ivd_set_display_frame_op_t.u4_size 373 != sizeof(ih264d_set_display_frame_op_t)) 374 && (ps_op->s_ivd_set_display_frame_op_t.u4_size 375 != sizeof(ivd_set_display_frame_op_t))) 376 { 377 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 378 << IVD_UNSUPPORTEDPARAM; 379 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 380 IVD_OP_API_STRUCT_SIZE_INCORRECT; 381 return (IV_FAIL); 382 } 383 384 if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0) 385 { 386 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 387 << IVD_UNSUPPORTEDPARAM; 388 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 389 IVD_DISP_FRM_ZERO_OP_BUFS; 390 return IV_FAIL; 391 } 392 393 for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs; 394 j++) 395 { 396 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs 397 == 0) 398 { 399 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 400 << IVD_UNSUPPORTEDPARAM; 401 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 402 IVD_DISP_FRM_ZERO_OP_BUFS; 403 return IV_FAIL; 404 } 405 406 for(i = 0; 407 i 408 < ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs; 409 i++) 410 { 411 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i] 412 == NULL) 413 { 414 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 415 << IVD_UNSUPPORTEDPARAM; 416 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 417 IVD_DISP_FRM_OP_BUF_NULL; 418 return IV_FAIL; 419 } 420 421 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i] 422 == 0) 423 { 424 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 425 << IVD_UNSUPPORTEDPARAM; 426 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 427 IVD_DISP_FRM_ZERO_OP_BUF_SIZE; 428 return IV_FAIL; 429 } 430 } 431 } 432 } 433 break; 434 435 case IVD_CMD_VIDEO_DECODE: 436 { 437 ih264d_video_decode_ip_t *ps_ip = 438 (ih264d_video_decode_ip_t *)pv_api_ip; 439 ih264d_video_decode_op_t *ps_op = 440 (ih264d_video_decode_op_t *)pv_api_op; 441 442 H264_DEC_DEBUG_PRINT("The input bytes is: %d", 443 ps_ip->s_ivd_video_decode_ip_t.u4_num_Bytes); 444 ps_op->s_ivd_video_decode_op_t.u4_error_code = 0; 445 446 if(ps_ip->s_ivd_video_decode_ip_t.u4_size 447 != sizeof(ih264d_video_decode_ip_t)&& 448 ps_ip->s_ivd_video_decode_ip_t.u4_size != offsetof(ivd_video_decode_ip_t, s_out_buffer)) 449 { 450 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 451 << IVD_UNSUPPORTEDPARAM; 452 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 453 IVD_IP_API_STRUCT_SIZE_INCORRECT; 454 return (IV_FAIL); 455 } 456 457 if(ps_op->s_ivd_video_decode_op_t.u4_size 458 != sizeof(ih264d_video_decode_op_t)&& 459 ps_op->s_ivd_video_decode_op_t.u4_size != offsetof(ivd_video_decode_op_t, u4_output_present)) 460 { 461 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 462 << IVD_UNSUPPORTEDPARAM; 463 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 464 IVD_OP_API_STRUCT_SIZE_INCORRECT; 465 return (IV_FAIL); 466 } 467 468 } 469 break; 470 471 case IVD_CMD_DELETE: 472 { 473 ih264d_delete_ip_t *ps_ip = 474 (ih264d_delete_ip_t *)pv_api_ip; 475 ih264d_delete_op_t *ps_op = 476 (ih264d_delete_op_t *)pv_api_op; 477 478 ps_op->s_ivd_delete_op_t.u4_error_code = 0; 479 480 if(ps_ip->s_ivd_delete_ip_t.u4_size 481 != sizeof(ih264d_delete_ip_t)) 482 { 483 ps_op->s_ivd_delete_op_t.u4_error_code |= 1 484 << IVD_UNSUPPORTEDPARAM; 485 ps_op->s_ivd_delete_op_t.u4_error_code |= 486 IVD_IP_API_STRUCT_SIZE_INCORRECT; 487 return (IV_FAIL); 488 } 489 490 if(ps_op->s_ivd_delete_op_t.u4_size 491 != sizeof(ih264d_delete_op_t)) 492 { 493 ps_op->s_ivd_delete_op_t.u4_error_code |= 1 494 << IVD_UNSUPPORTEDPARAM; 495 ps_op->s_ivd_delete_op_t.u4_error_code |= 496 IVD_OP_API_STRUCT_SIZE_INCORRECT; 497 return (IV_FAIL); 498 } 499 500 } 501 break; 502 503 case IVD_CMD_VIDEO_CTL: 504 { 505 UWORD32 *pu4_ptr_cmd; 506 UWORD32 sub_command; 507 508 pu4_ptr_cmd = (UWORD32 *)pv_api_ip; 509 pu4_ptr_cmd += 2; 510 sub_command = *pu4_ptr_cmd; 511 512 switch(sub_command) 513 { 514 case IVD_CMD_CTL_SETPARAMS: 515 { 516 ih264d_ctl_set_config_ip_t *ps_ip; 517 ih264d_ctl_set_config_op_t *ps_op; 518 ps_ip = (ih264d_ctl_set_config_ip_t *)pv_api_ip; 519 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op; 520 521 if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size 522 != sizeof(ih264d_ctl_set_config_ip_t)) 523 { 524 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 525 << IVD_UNSUPPORTEDPARAM; 526 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 527 IVD_IP_API_STRUCT_SIZE_INCORRECT; 528 return IV_FAIL; 529 } 530 } 531 //no break; is needed here 532 case IVD_CMD_CTL_SETDEFAULT: 533 { 534 ih264d_ctl_set_config_op_t *ps_op; 535 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op; 536 if(ps_op->s_ivd_ctl_set_config_op_t.u4_size 537 != sizeof(ih264d_ctl_set_config_op_t)) 538 { 539 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 540 << IVD_UNSUPPORTEDPARAM; 541 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 542 IVD_OP_API_STRUCT_SIZE_INCORRECT; 543 return IV_FAIL; 544 } 545 } 546 break; 547 548 case IVD_CMD_CTL_GETPARAMS: 549 { 550 ih264d_ctl_getstatus_ip_t *ps_ip; 551 ih264d_ctl_getstatus_op_t *ps_op; 552 553 ps_ip = (ih264d_ctl_getstatus_ip_t *)pv_api_ip; 554 ps_op = (ih264d_ctl_getstatus_op_t *)pv_api_op; 555 if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size 556 != sizeof(ih264d_ctl_getstatus_ip_t)) 557 { 558 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 559 << IVD_UNSUPPORTEDPARAM; 560 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 561 IVD_IP_API_STRUCT_SIZE_INCORRECT; 562 return IV_FAIL; 563 } 564 if(ps_op->s_ivd_ctl_getstatus_op_t.u4_size 565 != sizeof(ih264d_ctl_getstatus_op_t)) 566 { 567 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 568 << IVD_UNSUPPORTEDPARAM; 569 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 570 IVD_OP_API_STRUCT_SIZE_INCORRECT; 571 return IV_FAIL; 572 } 573 } 574 break; 575 576 case IVD_CMD_CTL_GETBUFINFO: 577 { 578 ih264d_ctl_getbufinfo_ip_t *ps_ip; 579 ih264d_ctl_getbufinfo_op_t *ps_op; 580 ps_ip = (ih264d_ctl_getbufinfo_ip_t *)pv_api_ip; 581 ps_op = (ih264d_ctl_getbufinfo_op_t *)pv_api_op; 582 583 if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size 584 != sizeof(ih264d_ctl_getbufinfo_ip_t)) 585 { 586 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 587 << IVD_UNSUPPORTEDPARAM; 588 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 589 IVD_IP_API_STRUCT_SIZE_INCORRECT; 590 return IV_FAIL; 591 } 592 if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size 593 != sizeof(ih264d_ctl_getbufinfo_op_t)) 594 { 595 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 596 << IVD_UNSUPPORTEDPARAM; 597 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 598 IVD_OP_API_STRUCT_SIZE_INCORRECT; 599 return IV_FAIL; 600 } 601 } 602 break; 603 604 case IVD_CMD_CTL_GETVERSION: 605 { 606 ih264d_ctl_getversioninfo_ip_t *ps_ip; 607 ih264d_ctl_getversioninfo_op_t *ps_op; 608 ps_ip = (ih264d_ctl_getversioninfo_ip_t *)pv_api_ip; 609 ps_op = (ih264d_ctl_getversioninfo_op_t *)pv_api_op; 610 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size 611 != sizeof(ih264d_ctl_getversioninfo_ip_t)) 612 { 613 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 614 << IVD_UNSUPPORTEDPARAM; 615 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 616 IVD_IP_API_STRUCT_SIZE_INCORRECT; 617 return IV_FAIL; 618 } 619 if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size 620 != sizeof(ih264d_ctl_getversioninfo_op_t)) 621 { 622 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 623 << IVD_UNSUPPORTEDPARAM; 624 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 625 IVD_OP_API_STRUCT_SIZE_INCORRECT; 626 return IV_FAIL; 627 } 628 } 629 break; 630 631 case IVD_CMD_CTL_FLUSH: 632 { 633 ih264d_ctl_flush_ip_t *ps_ip; 634 ih264d_ctl_flush_op_t *ps_op; 635 ps_ip = (ih264d_ctl_flush_ip_t *)pv_api_ip; 636 ps_op = (ih264d_ctl_flush_op_t *)pv_api_op; 637 if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size 638 != sizeof(ih264d_ctl_flush_ip_t)) 639 { 640 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 641 << IVD_UNSUPPORTEDPARAM; 642 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 643 IVD_IP_API_STRUCT_SIZE_INCORRECT; 644 return IV_FAIL; 645 } 646 if(ps_op->s_ivd_ctl_flush_op_t.u4_size 647 != sizeof(ih264d_ctl_flush_op_t)) 648 { 649 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 650 << IVD_UNSUPPORTEDPARAM; 651 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 652 IVD_OP_API_STRUCT_SIZE_INCORRECT; 653 return IV_FAIL; 654 } 655 } 656 break; 657 658 case IVD_CMD_CTL_RESET: 659 { 660 ih264d_ctl_reset_ip_t *ps_ip; 661 ih264d_ctl_reset_op_t *ps_op; 662 ps_ip = (ih264d_ctl_reset_ip_t *)pv_api_ip; 663 ps_op = (ih264d_ctl_reset_op_t *)pv_api_op; 664 if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size 665 != sizeof(ih264d_ctl_reset_ip_t)) 666 { 667 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 668 << IVD_UNSUPPORTEDPARAM; 669 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 670 IVD_IP_API_STRUCT_SIZE_INCORRECT; 671 return IV_FAIL; 672 } 673 if(ps_op->s_ivd_ctl_reset_op_t.u4_size 674 != sizeof(ih264d_ctl_reset_op_t)) 675 { 676 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 677 << IVD_UNSUPPORTEDPARAM; 678 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 679 IVD_OP_API_STRUCT_SIZE_INCORRECT; 680 return IV_FAIL; 681 } 682 } 683 break; 684 685 case IH264D_CMD_CTL_DEGRADE: 686 { 687 ih264d_ctl_degrade_ip_t *ps_ip; 688 ih264d_ctl_degrade_op_t *ps_op; 689 690 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip; 691 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op; 692 693 if(ps_ip->u4_size != sizeof(ih264d_ctl_degrade_ip_t)) 694 { 695 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 696 ps_op->u4_error_code |= 697 IVD_IP_API_STRUCT_SIZE_INCORRECT; 698 return IV_FAIL; 699 } 700 701 if(ps_op->u4_size != sizeof(ih264d_ctl_degrade_op_t)) 702 { 703 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 704 ps_op->u4_error_code |= 705 IVD_OP_API_STRUCT_SIZE_INCORRECT; 706 return IV_FAIL; 707 } 708 709 if((ps_ip->i4_degrade_pics < 0) 710 || (ps_ip->i4_degrade_pics > 4) 711 || (ps_ip->i4_nondegrade_interval < 0) 712 || (ps_ip->i4_degrade_type < 0) 713 || (ps_ip->i4_degrade_type > 15)) 714 { 715 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 716 return IV_FAIL; 717 } 718 719 break; 720 } 721 722 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS: 723 { 724 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip; 725 ih264d_ctl_get_frame_dimensions_op_t *ps_op; 726 727 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip; 728 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op; 729 730 if(ps_ip->u4_size 731 != sizeof(ih264d_ctl_get_frame_dimensions_ip_t)) 732 { 733 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 734 ps_op->u4_error_code |= 735 IVD_IP_API_STRUCT_SIZE_INCORRECT; 736 return IV_FAIL; 737 } 738 739 if(ps_op->u4_size 740 != sizeof(ih264d_ctl_get_frame_dimensions_op_t)) 741 { 742 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 743 ps_op->u4_error_code |= 744 IVD_OP_API_STRUCT_SIZE_INCORRECT; 745 return IV_FAIL; 746 } 747 748 break; 749 } 750 case IH264D_CMD_CTL_GET_VUI_PARAMS: 751 { 752 ih264d_ctl_get_vui_params_ip_t *ps_ip; 753 ih264d_ctl_get_vui_params_op_t *ps_op; 754 755 ps_ip = 756 (ih264d_ctl_get_vui_params_ip_t *)pv_api_ip; 757 ps_op = 758 (ih264d_ctl_get_vui_params_op_t *)pv_api_op; 759 760 if(ps_ip->u4_size 761 != sizeof(ih264d_ctl_get_vui_params_ip_t)) 762 { 763 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 764 ps_op->u4_error_code |= 765 IVD_IP_API_STRUCT_SIZE_INCORRECT; 766 return IV_FAIL; 767 } 768 769 if(ps_op->u4_size 770 != sizeof(ih264d_ctl_get_vui_params_op_t)) 771 { 772 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 773 ps_op->u4_error_code |= 774 IVD_OP_API_STRUCT_SIZE_INCORRECT; 775 return IV_FAIL; 776 } 777 778 break; 779 } 780 case IH264D_CMD_CTL_SET_NUM_CORES: 781 { 782 ih264d_ctl_set_num_cores_ip_t *ps_ip; 783 ih264d_ctl_set_num_cores_op_t *ps_op; 784 785 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip; 786 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op; 787 788 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_num_cores_ip_t)) 789 { 790 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 791 ps_op->u4_error_code |= 792 IVD_IP_API_STRUCT_SIZE_INCORRECT; 793 return IV_FAIL; 794 } 795 796 if(ps_op->u4_size != sizeof(ih264d_ctl_set_num_cores_op_t)) 797 { 798 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 799 ps_op->u4_error_code |= 800 IVD_OP_API_STRUCT_SIZE_INCORRECT; 801 return IV_FAIL; 802 } 803 804 if((ps_ip->u4_num_cores != 1) && (ps_ip->u4_num_cores != 2) 805 && (ps_ip->u4_num_cores != 3) 806 && (ps_ip->u4_num_cores != 4)) 807 { 808 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 809 return IV_FAIL; 810 } 811 break; 812 } 813 case IH264D_CMD_CTL_SET_PROCESSOR: 814 { 815 ih264d_ctl_set_processor_ip_t *ps_ip; 816 ih264d_ctl_set_processor_op_t *ps_op; 817 818 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip; 819 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op; 820 821 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_processor_ip_t)) 822 { 823 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 824 ps_op->u4_error_code |= 825 IVD_IP_API_STRUCT_SIZE_INCORRECT; 826 return IV_FAIL; 827 } 828 829 if(ps_op->u4_size != sizeof(ih264d_ctl_set_processor_op_t)) 830 { 831 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 832 ps_op->u4_error_code |= 833 IVD_OP_API_STRUCT_SIZE_INCORRECT; 834 return IV_FAIL; 835 } 836 837 break; 838 } 839 default: 840 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 841 *(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD; 842 return IV_FAIL; 843 break; 844 } 845 } 846 break; 847 } 848 849 return IV_SUCCESS; 850} 851 852 853/** 854 ******************************************************************************* 855 * 856 * @brief 857 * Sets Processor type 858 * 859 * @par Description: 860 * Sets Processor type 861 * 862 * @param[in] ps_codec_obj 863 * Pointer to codec object at API level 864 * 865 * @param[in] pv_api_ip 866 * Pointer to input argument structure 867 * 868 * @param[out] pv_api_op 869 * Pointer to output argument structure 870 * 871 * @returns Status 872 * 873 * @remarks 874 * 875 * 876 ******************************************************************************* 877 */ 878 879WORD32 ih264d_set_processor(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 880{ 881 ih264d_ctl_set_processor_ip_t *ps_ip; 882 ih264d_ctl_set_processor_op_t *ps_op; 883 dec_struct_t *ps_codec = (dec_struct_t *)dec_hdl->pv_codec_handle; 884 885 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip; 886 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op; 887 888 ps_codec->e_processor_arch = (IVD_ARCH_T)ps_ip->u4_arch; 889 ps_codec->e_processor_soc = (IVD_SOC_T)ps_ip->u4_soc; 890 891 ih264d_init_function_ptr(ps_codec); 892 893 ps_op->u4_error_code = 0; 894 return IV_SUCCESS; 895} 896 897 898/************************************************************************** 899 * \if Function name : ih264d_init_decoder \endif 900 * 901 * 902 * \brief 903 * Initializes the decoder 904 * 905 * \param apiVersion : Version of the api being used. 906 * \param errorHandlingMechanism : Mechanism to be used for errror handling. 907 * \param postFilteringType: Type of post filtering operation to be used. 908 * \param uc_outputFormat: Format of the decoded picture [default 4:2:0]. 909 * \param uc_dispBufs: Number of Display Buffers. 910 * \param p_NALBufAPI: Pointer to NAL Buffer API. 911 * \param p_DispBufAPI: Pointer to Display Buffer API. 912 * \param ih264d_dec_mem_manager :Pointer to the function that will be called by decoder 913 * for memory allocation and freeing. 914 * 915 * \return 916 * 0 on Success and -1 on error 917 * 918 ************************************************************************** 919 */ 920void ih264d_init_decoder(void * ps_dec_params) 921{ 922 dec_struct_t * ps_dec = (dec_struct_t *)ps_dec_params; 923 dec_slice_params_t *ps_cur_slice; 924 pocstruct_t *ps_prev_poc, *ps_cur_poc; 925 WORD32 size; 926 927 size = sizeof(pred_info_t) * 2 * 32; 928 memset(ps_dec->ps_pred, 0 , size); 929 930 size = sizeof(disp_mgr_t); 931 memset(ps_dec->pv_disp_buf_mgr, 0 , size); 932 933 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size(); 934 memset(ps_dec->pv_pic_buf_mgr, 0, size); 935 936 size = sizeof(dec_err_status_t); 937 memset(ps_dec->ps_dec_err_status, 0, size); 938 939 size = sizeof(sei); 940 memset(ps_dec->ps_sei, 0, size); 941 942 size = sizeof(dpb_commands_t); 943 memset(ps_dec->ps_dpb_cmds, 0, size); 944 945 size = sizeof(dec_bit_stream_t); 946 memset(ps_dec->ps_bitstrm, 0, size); 947 948 size = sizeof(dec_slice_params_t); 949 memset(ps_dec->ps_cur_slice, 0, size); 950 951 size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t)); 952 memset(ps_dec->pv_scratch_sps_pps, 0, size); 953 954 size = sizeof(ctxt_inc_mb_info_t); 955 memset(ps_dec->ps_left_mb_ctxt_info, 0, size); 956 957 size = (sizeof(neighbouradd_t) << 2); 958 memset(ps_dec->ps_left_mvpred_addr, 0 ,size); 959 960 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size(); 961 memset(ps_dec->pv_mv_buf_mgr, 0, size); 962 963 /* Free any dynamic buffers that are allocated */ 964 ih264d_free_dynamic_bufs(ps_dec); 965 966 ps_cur_slice = ps_dec->ps_cur_slice; 967 ps_dec->init_done = 0; 968 969 ps_dec->u4_num_cores = 1; 970 971 ps_dec->u2_pic_ht = ps_dec->u2_pic_wd = 0; 972 973 ps_dec->u1_separate_parse = DEFAULT_SEPARATE_PARSE; 974 ps_dec->u4_app_disable_deblk_frm = 0; 975 ps_dec->i4_degrade_type = 0; 976 ps_dec->i4_degrade_pics = 0; 977 978 ps_dec->i4_app_skip_mode = IVD_SKIP_NONE; 979 ps_dec->i4_dec_skip_mode = IVD_SKIP_NONE; 980 981 memset(ps_dec->ps_pps, 0, 982 ((sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS)); 983 memset(ps_dec->ps_sps, 0, 984 ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS)); 985 986 /* Initialization of function pointers ih264d_deblock_picture function*/ 987 988 ps_dec->p_DeblockPicture[0] = ih264d_deblock_picture_non_mbaff; 989 ps_dec->p_DeblockPicture[1] = ih264d_deblock_picture_mbaff; 990 991 ps_dec->s_cab_dec_env.pv_codec_handle = ps_dec; 992 993 ps_dec->u4_num_fld_in_frm = 0; 994 995 ps_dec->ps_dpb_mgr->pv_codec_handle = ps_dec; 996 997 /* Initialize the sei validity u4_flag with zero indiacting sei is not valid*/ 998 ps_dec->ps_sei->u1_is_valid = 0; 999 1000 /* decParams Initializations */ 1001 ps_dec->ps_cur_pps = NULL; 1002 ps_dec->ps_cur_sps = NULL; 1003 ps_dec->u1_init_dec_flag = 0; 1004 ps_dec->u1_first_slice_in_stream = 1; 1005 ps_dec->u1_last_pic_not_decoded = 0; 1006 ps_dec->u4_app_disp_width = 0; 1007 ps_dec->i4_header_decoded = 0; 1008 ps_dec->u4_total_frames_decoded = 0; 1009 1010 ps_dec->i4_error_code = 0; 1011 ps_dec->i4_content_type = -1; 1012 ps_dec->ps_cur_slice->u1_mbaff_frame_flag = 0; 1013 1014 ps_dec->ps_dec_err_status->u1_err_flag = ACCEPT_ALL_PICS; //REJECT_PB_PICS; 1015 ps_dec->ps_dec_err_status->u1_cur_pic_type = PIC_TYPE_UNKNOWN; 1016 ps_dec->ps_dec_err_status->u4_frm_sei_sync = SYNC_FRM_DEFAULT; 1017 ps_dec->ps_dec_err_status->u4_cur_frm = INIT_FRAME; 1018 ps_dec->ps_dec_err_status->u1_pic_aud_i = PIC_TYPE_UNKNOWN; 1019 1020 ps_dec->u1_pr_sl_type = 0xFF; 1021 ps_dec->u2_mbx = 0xffff; 1022 ps_dec->u2_mby = 0; 1023 ps_dec->u2_total_mbs_coded = 0; 1024 1025 /* POC initializations */ 1026 ps_prev_poc = &ps_dec->s_prev_pic_poc; 1027 ps_cur_poc = &ps_dec->s_cur_pic_poc; 1028 ps_prev_poc->i4_pic_order_cnt_lsb = ps_cur_poc->i4_pic_order_cnt_lsb = 0; 1029 ps_prev_poc->i4_pic_order_cnt_msb = ps_cur_poc->i4_pic_order_cnt_msb = 0; 1030 ps_prev_poc->i4_delta_pic_order_cnt_bottom = 1031 ps_cur_poc->i4_delta_pic_order_cnt_bottom = 0; 1032 ps_prev_poc->i4_delta_pic_order_cnt[0] = 1033 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0; 1034 ps_prev_poc->i4_delta_pic_order_cnt[1] = 1035 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0; 1036 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0; 1037 ps_prev_poc->i4_top_field_order_count = ps_cur_poc->i4_top_field_order_count = 1038 0; 1039 ps_prev_poc->i4_bottom_field_order_count = 1040 ps_cur_poc->i4_bottom_field_order_count = 0; 1041 ps_prev_poc->u1_bot_field = ps_cur_poc->u1_bot_field = 0; 1042 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0; 1043 ps_prev_poc->i4_prev_frame_num_ofst = ps_cur_poc->i4_prev_frame_num_ofst = 0; 1044 ps_cur_slice->u1_mmco_equalto5 = 0; 1045 ps_cur_slice->u2_frame_num = 0; 1046 1047 ps_dec->i4_max_poc = 0; 1048 ps_dec->i4_prev_max_display_seq = 0; 1049 ps_dec->u1_recon_mb_grp = 4; 1050 1051 /* Field PIC initializations */ 1052 ps_dec->u1_second_field = 0; 1053 ps_dec->s_prev_seq_params.u1_eoseq_pending = 0; 1054 1055 /* Set the cropping parameters as zero */ 1056 ps_dec->u2_crop_offset_y = 0; 1057 ps_dec->u2_crop_offset_uv = 0; 1058 1059 /* The Initial Frame Rate Info is not Present */ 1060 ps_dec->i4_vui_frame_rate = -1; 1061 ps_dec->i4_pic_type = -1; 1062 ps_dec->i4_frametype = -1; 1063 ps_dec->i4_content_type = -1; 1064 1065 ps_dec->u1_res_changed = 0; 1066 1067 1068 ps_dec->u1_frame_decoded_flag = 0; 1069 1070 /* Set the default frame seek mask mode */ 1071 ps_dec->u4_skip_frm_mask = SKIP_NONE; 1072 1073 /********************************************************/ 1074 /* Initialize CAVLC residual decoding function pointers */ 1075 /********************************************************/ 1076 ps_dec->pf_cavlc_4x4res_block[0] = ih264d_cavlc_4x4res_block_totalcoeff_1; 1077 ps_dec->pf_cavlc_4x4res_block[1] = 1078 ih264d_cavlc_4x4res_block_totalcoeff_2to10; 1079 ps_dec->pf_cavlc_4x4res_block[2] = 1080 ih264d_cavlc_4x4res_block_totalcoeff_11to16; 1081 1082 ps_dec->pf_cavlc_parse4x4coeff[0] = ih264d_cavlc_parse4x4coeff_n0to7; 1083 ps_dec->pf_cavlc_parse4x4coeff[1] = ih264d_cavlc_parse4x4coeff_n8; 1084 1085 ps_dec->pf_cavlc_parse_8x8block[0] = 1086 ih264d_cavlc_parse_8x8block_none_available; 1087 ps_dec->pf_cavlc_parse_8x8block[1] = 1088 ih264d_cavlc_parse_8x8block_left_available; 1089 ps_dec->pf_cavlc_parse_8x8block[2] = 1090 ih264d_cavlc_parse_8x8block_top_available; 1091 ps_dec->pf_cavlc_parse_8x8block[3] = 1092 ih264d_cavlc_parse_8x8block_both_available; 1093 1094 /***************************************************************************/ 1095 /* Initialize Bs calculation function pointers for P and B, 16x16/non16x16 */ 1096 /***************************************************************************/ 1097 ps_dec->pf_fill_bs1[0][0] = ih264d_fill_bs1_16x16mb_pslice; 1098 ps_dec->pf_fill_bs1[0][1] = ih264d_fill_bs1_non16x16mb_pslice; 1099 1100 ps_dec->pf_fill_bs1[1][0] = ih264d_fill_bs1_16x16mb_bslice; 1101 ps_dec->pf_fill_bs1[1][1] = ih264d_fill_bs1_non16x16mb_bslice; 1102 1103 ps_dec->pf_fill_bs_xtra_left_edge[0] = 1104 ih264d_fill_bs_xtra_left_edge_cur_frm; 1105 ps_dec->pf_fill_bs_xtra_left_edge[1] = 1106 ih264d_fill_bs_xtra_left_edge_cur_fld; 1107 1108 /* Initialize Reference Pic Buffers */ 1109 ih264d_init_ref_bufs(ps_dec->ps_dpb_mgr); 1110 1111 ps_dec->u2_prv_frame_num = 0; 1112 ps_dec->u1_top_bottom_decoded = 0; 1113 ps_dec->u1_dangling_field = 0; 1114 1115 ps_dec->s_cab_dec_env.cabac_table = gau4_ih264d_cabac_table; 1116 1117 ps_dec->pu1_left_mv_ctxt_inc = ps_dec->u1_left_mv_ctxt_inc_arr[0]; 1118 ps_dec->pi1_left_ref_idx_ctxt_inc = 1119 &ps_dec->i1_left_ref_idx_ctx_inc_arr[0][0]; 1120 ps_dec->pu1_left_yuv_dc_csbp = &ps_dec->u1_yuv_dc_csbp_topmb; 1121 1122 /* ! */ 1123 /* Initializing flush frame u4_flag */ 1124 ps_dec->u1_flushfrm = 0; 1125 1126 { 1127 ps_dec->s_cab_dec_env.pv_codec_handle = (void*)ps_dec; 1128 ps_dec->ps_bitstrm->pv_codec_handle = (void*)ps_dec; 1129 ps_dec->ps_cur_slice->pv_codec_handle = (void*)ps_dec; 1130 ps_dec->ps_dpb_mgr->pv_codec_handle = (void*)ps_dec; 1131 } 1132 1133 memset(ps_dec->disp_bufs, 0, (MAX_DISP_BUFS_NEW) * sizeof(disp_buf_t)); 1134 memset(ps_dec->u4_disp_buf_mapping, 0, 1135 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32)); 1136 memset(ps_dec->u4_disp_buf_to_be_freed, 0, 1137 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32)); 1138 memset(ps_dec->ps_cur_slice, 0, sizeof(dec_slice_params_t)); 1139 1140 ih264d_init_arch(ps_dec); 1141 ih264d_init_function_ptr(ps_dec); 1142 ps_dec->e_frm_out_mode = IVD_DISPLAY_FRAME_OUT; 1143 ps_dec->init_done = 1; 1144 1145} 1146WORD32 ih264d_free_static_bufs(iv_obj_t *dec_hdl) 1147{ 1148 dec_struct_t *ps_dec; 1149 1150 void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf); 1151 void *pv_mem_ctxt; 1152 1153 ps_dec = (dec_struct_t *)dec_hdl->pv_codec_handle; 1154 pf_aligned_free = ps_dec->pf_aligned_free; 1155 pv_mem_ctxt = ps_dec->pv_mem_ctxt; 1156 1157 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_sps); 1158 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pps); 1159 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_dec_thread_handle); 1160 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_bs_deblk_thread_handle); 1161 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dpb_mgr); 1162 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pred); 1163 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_disp_buf_mgr); 1164 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_pic_buf_mgr); 1165 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pic_buf_base); 1166 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dec_err_status); 1167 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_sei); 1168 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dpb_cmds); 1169 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_bitstrm); 1170 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_cur_slice); 1171 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_scratch_sps_pps); 1172 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_bits_buf_static); 1173 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ppv_map_ref_idx_to_poc_base); 1174 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->p_cabac_ctxt_table_t); 1175 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_left_mb_ctxt_info); 1176 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_ref_buff_base); 1177 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pi2_pred1); 1178 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_temp_mc_buffer); 1179 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_init_dpb_base); 1180 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu4_mbaff_wt_mat); 1181 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu4_wts_ofsts_mat); 1182 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_left_mvpred_addr); 1183 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_mv_buf_mgr); 1184 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_col_mv_base); 1185 PS_DEC_ALIGNED_FREE(ps_dec, dec_hdl->pv_codec_handle); 1186 1187 if(dec_hdl) 1188 { 1189 pf_aligned_free(pv_mem_ctxt, dec_hdl); 1190 } 1191 return IV_SUCCESS; 1192} 1193/*****************************************************************************/ 1194/* */ 1195/* Function Name : ih264d_create */ 1196/* */ 1197/* Description : creates decoder */ 1198/* */ 1199/* Inputs :iv_obj_t decoder handle */ 1200/* :pv_api_ip pointer to input structure */ 1201/* :pv_api_op pointer to output structure */ 1202/* Outputs : */ 1203/* Returns : void */ 1204/* */ 1205/* Issues : none */ 1206/* */ 1207/* Revision History: */ 1208/* */ 1209/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1210/* 22 10 2008 100356 Draft */ 1211/* */ 1212/*****************************************************************************/ 1213WORD32 ih264d_allocate_static_bufs(iv_obj_t **dec_hdl, void *pv_api_ip, void *pv_api_op) 1214{ 1215 ih264d_create_ip_t *ps_create_ip; 1216 ih264d_create_op_t *ps_create_op; 1217 void *pv_buf; 1218 UWORD8 *pu1_buf; 1219 dec_struct_t *ps_dec; 1220 void *(*pf_aligned_alloc)(void *pv_mem_ctxt, WORD32 alignment, WORD32 size); 1221 void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf); 1222 void *pv_mem_ctxt; 1223 WORD32 size; 1224 1225 ps_create_ip = (ih264d_create_ip_t *)pv_api_ip; 1226 ps_create_op = (ih264d_create_op_t *)pv_api_op; 1227 1228 ps_create_op->s_ivd_create_op_t.u4_error_code = 0; 1229 1230 pf_aligned_alloc = ps_create_ip->s_ivd_create_ip_t.pf_aligned_alloc; 1231 pf_aligned_free = ps_create_ip->s_ivd_create_ip_t.pf_aligned_free; 1232 pv_mem_ctxt = ps_create_ip->s_ivd_create_ip_t.pv_mem_ctxt; 1233 1234 /* Initialize return handle to NULL */ 1235 ps_create_op->s_ivd_create_op_t.pv_handle = NULL; 1236 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, sizeof(iv_obj_t)); 1237 RETURN_IF((NULL == pv_buf), IV_FAIL); 1238 *dec_hdl = (iv_obj_t *)pv_buf; 1239 ps_create_op->s_ivd_create_op_t.pv_handle = *dec_hdl; 1240 1241 (*dec_hdl)->pv_codec_handle = NULL; 1242 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, sizeof(dec_struct_t)); 1243 RETURN_IF((NULL == pv_buf), IV_FAIL); 1244 (*dec_hdl)->pv_codec_handle = (dec_struct_t *)pv_buf; 1245 ps_dec = (dec_struct_t *)pv_buf; 1246 1247 memset(ps_dec, 0, sizeof(dec_struct_t)); 1248 1249#ifndef LOGO_EN 1250 ps_dec->u4_share_disp_buf = ps_create_ip->s_ivd_create_ip_t.u4_share_disp_buf; 1251#else 1252 ps_dec->u4_share_disp_buf = 0; 1253#endif 1254 1255 ps_dec->u1_chroma_format = 1256 (UWORD8)(ps_create_ip->s_ivd_create_ip_t.e_output_format); 1257 1258 if((ps_dec->u1_chroma_format != IV_YUV_420P) 1259 && (ps_dec->u1_chroma_format 1260 != IV_YUV_420SP_UV) 1261 && (ps_dec->u1_chroma_format 1262 != IV_YUV_420SP_VU)) 1263 { 1264 ps_dec->u4_share_disp_buf = 0; 1265 } 1266 1267 ps_dec->pf_aligned_alloc = pf_aligned_alloc; 1268 ps_dec->pf_aligned_free = pf_aligned_free; 1269 ps_dec->pv_mem_ctxt = pv_mem_ctxt; 1270 1271 1272 size = ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS); 1273 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1274 RETURN_IF((NULL == pv_buf), IV_FAIL); 1275 ps_dec->ps_sps = pv_buf; 1276 1277 size = (sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS; 1278 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1279 RETURN_IF((NULL == pv_buf), IV_FAIL); 1280 ps_dec->ps_pps = pv_buf; 1281 1282 size = ithread_get_handle_size(); 1283 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1284 RETURN_IF((NULL == pv_buf), IV_FAIL); 1285 ps_dec->pv_dec_thread_handle = pv_buf; 1286 1287 size = ithread_get_handle_size(); 1288 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1289 RETURN_IF((NULL == pv_buf), IV_FAIL); 1290 ps_dec->pv_bs_deblk_thread_handle = pv_buf; 1291 1292 size = sizeof(dpb_manager_t); 1293 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1294 RETURN_IF((NULL == pv_buf), IV_FAIL); 1295 ps_dec->ps_dpb_mgr = pv_buf; 1296 1297 size = sizeof(pred_info_t) * 2 * 32; 1298 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1299 RETURN_IF((NULL == pv_buf), IV_FAIL); 1300 ps_dec->ps_pred = pv_buf; 1301 1302 size = sizeof(disp_mgr_t); 1303 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1304 RETURN_IF((NULL == pv_buf), IV_FAIL); 1305 ps_dec->pv_disp_buf_mgr = pv_buf; 1306 1307 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size(); 1308 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1309 RETURN_IF((NULL == pv_buf), IV_FAIL); 1310 ps_dec->pv_pic_buf_mgr = pv_buf; 1311 1312 size = sizeof(struct pic_buffer_t) * (H264_MAX_REF_PICS * 2); 1313 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1314 RETURN_IF((NULL == pv_buf), IV_FAIL); 1315 ps_dec->ps_pic_buf_base = pv_buf; 1316 1317 size = sizeof(dec_err_status_t); 1318 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1319 RETURN_IF((NULL == pv_buf), IV_FAIL); 1320 ps_dec->ps_dec_err_status = (dec_err_status_t *)pv_buf; 1321 1322 size = sizeof(sei); 1323 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1324 RETURN_IF((NULL == pv_buf), IV_FAIL); 1325 ps_dec->ps_sei = (sei *)pv_buf; 1326 1327 size = sizeof(dpb_commands_t); 1328 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1329 RETURN_IF((NULL == pv_buf), IV_FAIL); 1330 ps_dec->ps_dpb_cmds = (dpb_commands_t *)pv_buf; 1331 1332 size = sizeof(dec_bit_stream_t); 1333 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1334 RETURN_IF((NULL == pv_buf), IV_FAIL); 1335 ps_dec->ps_bitstrm = (dec_bit_stream_t *)pv_buf; 1336 1337 size = sizeof(dec_slice_params_t); 1338 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1339 RETURN_IF((NULL == pv_buf), IV_FAIL); 1340 ps_dec->ps_cur_slice = (dec_slice_params_t *)pv_buf; 1341 1342 size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t)); 1343 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1344 RETURN_IF((NULL == pv_buf), IV_FAIL); 1345 ps_dec->pv_scratch_sps_pps = pv_buf; 1346 1347 1348 ps_dec->u4_static_bits_buf_size = 256000; 1349 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, ps_dec->u4_static_bits_buf_size); 1350 RETURN_IF((NULL == pv_buf), IV_FAIL); 1351 ps_dec->pu1_bits_buf_static = pv_buf; 1352 1353 1354 size = ((TOTAL_LIST_ENTRIES + PAD_MAP_IDX_POC) 1355 * sizeof(void *)); 1356 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1357 RETURN_IF((NULL == pv_buf), IV_FAIL); 1358 ps_dec->ppv_map_ref_idx_to_poc_base = pv_buf; 1359 memset(ps_dec->ppv_map_ref_idx_to_poc_base, 0, size); 1360 1361 ps_dec->ppv_map_ref_idx_to_poc = ps_dec->ppv_map_ref_idx_to_poc_base + OFFSET_MAP_IDX_POC; 1362 1363 1364 size = (sizeof(bin_ctxt_model_t) * NUM_CABAC_CTXTS); 1365 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1366 RETURN_IF((NULL == pv_buf), IV_FAIL); 1367 ps_dec->p_cabac_ctxt_table_t = pv_buf; 1368 1369 1370 1371 size = sizeof(ctxt_inc_mb_info_t); 1372 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1373 RETURN_IF((NULL == pv_buf), IV_FAIL); 1374 ps_dec->ps_left_mb_ctxt_info = pv_buf; 1375 1376 1377 1378 size = MAX_REF_BUF_SIZE * 2; 1379 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1380 RETURN_IF((NULL == pv_buf), IV_FAIL); 1381 ps_dec->pu1_ref_buff_base = pv_buf; 1382 ps_dec->pu1_ref_buff = ps_dec->pu1_ref_buff_base + MAX_REF_BUF_SIZE; 1383 1384 1385 size = ((sizeof(WORD16)) * PRED_BUFFER_WIDTH 1386 * PRED_BUFFER_HEIGHT * 2); 1387 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1388 RETURN_IF((NULL == pv_buf), IV_FAIL); 1389 ps_dec->pi2_pred1 = pv_buf; 1390 1391 1392 size = sizeof(UWORD8) * (MB_LUM_SIZE); 1393 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1394 RETURN_IF((NULL == pv_buf), IV_FAIL); 1395 ps_dec->pu1_temp_mc_buffer = pv_buf; 1396 1397 1398 1399 1400 size = 8 * MAX_REF_BUFS * sizeof(struct pic_buffer_t); 1401 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1402 RETURN_IF((NULL == pv_buf), IV_FAIL); 1403 1404 ps_dec->pu1_init_dpb_base = pv_buf; 1405 pu1_buf = pv_buf; 1406 ps_dec->ps_dpb_mgr->ps_init_dpb[0][0] = (struct pic_buffer_t *)pu1_buf; 1407 1408 pu1_buf += size / 2; 1409 ps_dec->ps_dpb_mgr->ps_init_dpb[1][0] = (struct pic_buffer_t *)pu1_buf; 1410 1411 size = (sizeof(UWORD32) * 2 * 3 1412 * ((MAX_FRAMES << 1) * (MAX_FRAMES << 1)) * 2); 1413 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1414 RETURN_IF((NULL == pv_buf), IV_FAIL); 1415 ps_dec->pu4_mbaff_wt_mat = pv_buf; 1416 1417 size = sizeof(UWORD32) * 2 * 3 1418 * ((MAX_FRAMES << 1) * (MAX_FRAMES << 1)); 1419 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1420 RETURN_IF((NULL == pv_buf), IV_FAIL); 1421 ps_dec->pu4_wts_ofsts_mat = pv_buf; 1422 1423 1424 size = (sizeof(neighbouradd_t) << 2); 1425 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1426 RETURN_IF((NULL == pv_buf), IV_FAIL); 1427 ps_dec->ps_left_mvpred_addr = pv_buf; 1428 1429 1430 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size(); 1431 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1432 RETURN_IF((NULL == pv_buf), IV_FAIL); 1433 ps_dec->pv_mv_buf_mgr = pv_buf; 1434 1435 1436 size = sizeof(col_mv_buf_t) * (H264_MAX_REF_PICS * 2); 1437 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1438 RETURN_IF((NULL == pv_buf), IV_FAIL); 1439 ps_dec->ps_col_mv_base = pv_buf; 1440 memset(ps_dec->ps_col_mv_base, 0, size); 1441 1442 { 1443 UWORD8 i; 1444 struct pic_buffer_t *ps_init_dpb; 1445 ps_init_dpb = ps_dec->ps_dpb_mgr->ps_init_dpb[0][0]; 1446 for(i = 0; i < 2 * MAX_REF_BUFS; i++) 1447 { 1448 ps_init_dpb->pu1_buf1 = NULL; 1449 ps_init_dpb->u1_long_term_frm_idx = MAX_REF_BUFS + 1; 1450 ps_dec->ps_dpb_mgr->ps_init_dpb[0][i] = ps_init_dpb; 1451 ps_dec->ps_dpb_mgr->ps_mod_dpb[0][i] = ps_init_dpb; 1452 ps_init_dpb++; 1453 } 1454 1455 ps_init_dpb = ps_dec->ps_dpb_mgr->ps_init_dpb[1][0]; 1456 for(i = 0; i < 2 * MAX_REF_BUFS; i++) 1457 { 1458 ps_init_dpb->pu1_buf1 = NULL; 1459 ps_init_dpb->u1_long_term_frm_idx = MAX_REF_BUFS + 1; 1460 ps_dec->ps_dpb_mgr->ps_init_dpb[1][i] = ps_init_dpb; 1461 ps_dec->ps_dpb_mgr->ps_mod_dpb[1][i] = ps_init_dpb; 1462 ps_init_dpb++; 1463 } 1464 } 1465 ih264d_init_decoder(ps_dec); 1466 1467 return IV_SUCCESS; 1468} 1469 1470 1471/*****************************************************************************/ 1472/* */ 1473/* Function Name : ih264d_create */ 1474/* */ 1475/* Description : creates decoder */ 1476/* */ 1477/* Inputs :iv_obj_t decoder handle */ 1478/* :pv_api_ip pointer to input structure */ 1479/* :pv_api_op pointer to output structure */ 1480/* Outputs : */ 1481/* Returns : void */ 1482/* */ 1483/* Issues : none */ 1484/* */ 1485/* Revision History: */ 1486/* */ 1487/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1488/* 22 10 2008 100356 Draft */ 1489/* */ 1490/*****************************************************************************/ 1491WORD32 ih264d_create(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 1492{ 1493 ih264d_create_ip_t *ps_create_ip; 1494 ih264d_create_op_t *ps_create_op; 1495 1496 WORD32 ret; 1497 1498 ps_create_ip = (ih264d_create_ip_t *)pv_api_ip; 1499 ps_create_op = (ih264d_create_op_t *)pv_api_op; 1500 1501 ps_create_op->s_ivd_create_op_t.u4_error_code = 0; 1502 dec_hdl = NULL; 1503 ret = ih264d_allocate_static_bufs(&dec_hdl, pv_api_ip, pv_api_op); 1504 1505 /* If allocation of some buffer fails, then free buffers allocated till then */ 1506 if(IV_FAIL == ret) 1507 { 1508 if(dec_hdl) 1509 { 1510 if(dec_hdl->pv_codec_handle) 1511 { 1512 ih264d_free_static_bufs(dec_hdl); 1513 } 1514 else 1515 { 1516 void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf); 1517 void *pv_mem_ctxt; 1518 1519 pf_aligned_free = ps_create_ip->s_ivd_create_ip_t.pf_aligned_free; 1520 pv_mem_ctxt = ps_create_ip->s_ivd_create_ip_t.pv_mem_ctxt; 1521 pf_aligned_free(pv_mem_ctxt, dec_hdl); 1522 } 1523 } 1524 ps_create_op->s_ivd_create_op_t.u4_error_code = IVD_MEM_ALLOC_FAILED; 1525 ps_create_op->s_ivd_create_op_t.u4_error_code = 1 << IVD_FATALERROR; 1526 1527 return IV_FAIL; 1528 } 1529 1530 return IV_SUCCESS; 1531} 1532 1533/*****************************************************************************/ 1534/* */ 1535/* Function Name : ih264d_map_error */ 1536/* */ 1537/* Description : Maps error codes to IVD error groups */ 1538/* */ 1539/* Inputs : */ 1540/* Globals : <Does it use any global variables?> */ 1541/* Outputs : */ 1542/* Returns : void */ 1543/* */ 1544/* Issues : none */ 1545/* */ 1546/* Revision History: */ 1547/* */ 1548/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1549/* 22 10 2008 100356 Draft */ 1550/* */ 1551/*****************************************************************************/ 1552UWORD32 ih264d_map_error(UWORD32 i4_err_status) 1553{ 1554 UWORD32 temp = 0; 1555 1556 switch(i4_err_status) 1557 { 1558 case ERROR_MEM_ALLOC_ISRAM_T: 1559 case ERROR_MEM_ALLOC_SDRAM_T: 1560 case ERROR_BUF_MGR: 1561 case ERROR_MB_GROUP_ASSGN_T: 1562 case ERROR_FRAME_LIMIT_OVER: 1563 case ERROR_ACTUAL_RESOLUTION_GREATER_THAN_INIT: 1564 case ERROR_PROFILE_NOT_SUPPORTED: 1565 case ERROR_INIT_NOT_DONE: 1566 case IVD_MEM_ALLOC_FAILED: 1567 temp = 1 << IVD_FATALERROR; 1568 H264_DEC_DEBUG_PRINT("\nFatal Error\n"); 1569 break; 1570 1571 case ERROR_DBP_MANAGER_T: 1572 case ERROR_GAPS_IN_FRM_NUM: 1573 case ERROR_UNKNOWN_NAL: 1574 case ERROR_INV_MB_SLC_GRP_T: 1575 case ERROR_MULTIPLE_SLC_GRP_T: 1576 case ERROR_UNKNOWN_LEVEL: 1577 case ERROR_UNAVAIL_PICBUF_T: 1578 case ERROR_UNAVAIL_MVBUF_T: 1579 case ERROR_UNAVAIL_DISPBUF_T: 1580 case ERROR_NUM_REF: 1581 case ERROR_REFIDX_ORDER_T: 1582 case ERROR_PIC0_NOT_FOUND_T: 1583 case ERROR_MB_TYPE: 1584 case ERROR_SUB_MB_TYPE: 1585 case ERROR_CBP: 1586 case ERROR_REF_IDX: 1587 case ERROR_NUM_MV: 1588 case ERROR_CHROMA_PRED_MODE: 1589 case ERROR_INTRAPRED: 1590 case ERROR_NEXT_MB_ADDRESS_T: 1591 case ERROR_MB_ADDRESS_T: 1592 case ERROR_PIC1_NOT_FOUND_T: 1593 case ERROR_CAVLC_NUM_COEFF_T: 1594 case ERROR_CAVLC_SCAN_POS_T: 1595 case ERROR_PRED_WEIGHT_TABLE_T: 1596 case ERROR_CORRUPTED_SLICE: 1597 temp = 1 << IVD_CORRUPTEDDATA; 1598 break; 1599 1600 case ERROR_NOT_SUPP_RESOLUTION: 1601 case ERROR_FEATURE_UNAVAIL: 1602 case ERROR_ACTUAL_LEVEL_GREATER_THAN_INIT: 1603 temp = 1 << IVD_UNSUPPORTEDINPUT; 1604 break; 1605 1606 case ERROR_INVALID_PIC_PARAM: 1607 case ERROR_INVALID_SEQ_PARAM: 1608 case ERROR_EGC_EXCEED_32_1_T: 1609 case ERROR_EGC_EXCEED_32_2_T: 1610 case ERROR_INV_RANGE_TEV_T: 1611 case ERROR_INV_SLC_TYPE_T: 1612 case ERROR_INV_POC_TYPE_T: 1613 case ERROR_INV_RANGE_QP_T: 1614 case ERROR_INV_SPS_PPS_T: 1615 case ERROR_INV_SLICE_HDR_T: 1616 temp = 1 << IVD_CORRUPTEDHEADER; 1617 break; 1618 1619 case ERROR_EOB_FLUSHBITS_T: 1620 case ERROR_EOB_GETBITS_T: 1621 case ERROR_EOB_GETBIT_T: 1622 case ERROR_EOB_BYPASS_T: 1623 case ERROR_EOB_DECISION_T: 1624 case ERROR_EOB_TERMINATE_T: 1625 case ERROR_EOB_READCOEFF4X4CAB_T: 1626 temp = 1 << IVD_INSUFFICIENTDATA; 1627 break; 1628 case ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED: 1629 case ERROR_DISP_WIDTH_RESET_TO_PIC_WIDTH: 1630 temp = 1 << IVD_UNSUPPORTEDPARAM | 1 << IVD_FATALERROR; 1631 break; 1632 1633 case ERROR_DANGLING_FIELD_IN_PIC: 1634 temp = 1 << IVD_APPLIEDCONCEALMENT; 1635 break; 1636 1637 } 1638 1639 return temp; 1640 1641} 1642 1643UWORD32 ih264d_get_outbuf_size(WORD32 pic_wd, 1644 UWORD32 pic_ht, 1645 UWORD8 u1_chroma_format, 1646 UWORD32 *p_buf_size) 1647{ 1648 UWORD32 u4_min_num_out_bufs = 0; 1649 1650 if(u1_chroma_format == IV_YUV_420P) 1651 u4_min_num_out_bufs = MIN_OUT_BUFS_420; 1652 else if(u1_chroma_format == IV_YUV_422ILE) 1653 u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE; 1654 else if(u1_chroma_format == IV_RGB_565) 1655 u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565; 1656 else if((u1_chroma_format == IV_YUV_420SP_UV) 1657 || (u1_chroma_format == IV_YUV_420SP_VU)) 1658 u4_min_num_out_bufs = MIN_OUT_BUFS_420SP; 1659 1660 if(u1_chroma_format == IV_YUV_420P) 1661 { 1662 p_buf_size[0] = (pic_wd * pic_ht); 1663 p_buf_size[1] = (pic_wd * pic_ht) >> 2; 1664 p_buf_size[2] = (pic_wd * pic_ht) >> 2; 1665 } 1666 else if(u1_chroma_format == IV_YUV_422ILE) 1667 { 1668 p_buf_size[0] = (pic_wd * pic_ht) * 2; 1669 p_buf_size[1] = p_buf_size[2] = 0; 1670 } 1671 else if(u1_chroma_format == IV_RGB_565) 1672 { 1673 p_buf_size[0] = (pic_wd * pic_ht) * 2; 1674 p_buf_size[1] = p_buf_size[2] = 0; 1675 } 1676 else if((u1_chroma_format == IV_YUV_420SP_UV) 1677 || (u1_chroma_format == IV_YUV_420SP_VU)) 1678 { 1679 p_buf_size[0] = (pic_wd * pic_ht); 1680 p_buf_size[1] = (pic_wd * pic_ht) >> 1; 1681 p_buf_size[2] = 0; 1682 } 1683 1684 return u4_min_num_out_bufs; 1685} 1686 1687WORD32 check_app_out_buf_size(dec_struct_t *ps_dec) 1688{ 1689 UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS]; 1690 UWORD32 u4_min_num_out_bufs, i; 1691 UWORD32 pic_wd, pic_ht; 1692 1693 if(0 == ps_dec->u4_share_disp_buf) 1694 { 1695 pic_wd = ps_dec->u2_disp_width; 1696 pic_ht = ps_dec->u2_disp_height; 1697 1698 } 1699 else 1700 { 1701 pic_wd = ps_dec->u2_frm_wd_y; 1702 pic_ht = ps_dec->u2_frm_ht_y; 1703 } 1704 1705 if(ps_dec->u4_app_disp_width > pic_wd) 1706 pic_wd = ps_dec->u4_app_disp_width; 1707 1708 u4_min_num_out_bufs = ih264d_get_outbuf_size(pic_wd, pic_ht, 1709 ps_dec->u1_chroma_format, 1710 &au4_min_out_buf_size[0]); 1711 1712 1713 if(0 == ps_dec->u4_share_disp_buf) 1714 { 1715 if(ps_dec->ps_out_buffer->u4_num_bufs < u4_min_num_out_bufs) 1716 return IV_FAIL; 1717 1718 for(i = 0; i < u4_min_num_out_bufs; i++) 1719 { 1720 if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i] 1721 < au4_min_out_buf_size[i]) 1722 return (IV_FAIL); 1723 } 1724 } 1725 else 1726 { 1727 if(ps_dec->disp_bufs[0].u4_num_bufs < u4_min_num_out_bufs) 1728 return IV_FAIL; 1729 1730 for(i = 0; i < u4_min_num_out_bufs; i++) 1731 { 1732 /* We need to check only with the disp_buffer[0], because we have 1733 * already ensured that all the buffers are of the same size in 1734 * ih264d_set_display_frame. 1735 */ 1736 if(ps_dec->disp_bufs[0].u4_bufsize[i] < au4_min_out_buf_size[i]) 1737 return (IV_FAIL); 1738 } 1739 1740 } 1741 1742 return (IV_SUCCESS); 1743} 1744 1745 1746/*****************************************************************************/ 1747/* */ 1748/* Function Name : ih264d_video_decode */ 1749/* */ 1750/* Description : handle video decode API command */ 1751/* */ 1752/* Inputs :iv_obj_t decoder handle */ 1753/* :pv_api_ip pointer to input structure */ 1754/* :pv_api_op pointer to output structure */ 1755/* Outputs : */ 1756/* Returns : void */ 1757/* */ 1758/* Issues : none */ 1759/* */ 1760/* Revision History: */ 1761/* */ 1762/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1763/* 22 10 2008 100356 Draft */ 1764/* */ 1765/*****************************************************************************/ 1766 1767WORD32 ih264d_video_decode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 1768{ 1769 /* ! */ 1770 1771 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 1772 1773 WORD32 i4_err_status = 0; 1774 UWORD8 *pu1_buf = NULL; 1775 WORD32 buflen; 1776 UWORD32 u4_max_ofst, u4_length_of_start_code = 0; 1777 1778 UWORD32 bytes_consumed = 0; 1779 UWORD32 cur_slice_is_nonref = 0; 1780 UWORD32 u4_next_is_aud; 1781 UWORD32 u4_first_start_code_found = 0; 1782 WORD32 ret = 0,api_ret_value = IV_SUCCESS; 1783 WORD32 header_data_left = 0,frame_data_left = 0; 1784 UWORD8 *pu1_bitstrm_buf; 1785 ivd_video_decode_ip_t *ps_dec_ip; 1786 ivd_video_decode_op_t *ps_dec_op; 1787 1788 ithread_set_name((void*)"Parse_thread"); 1789 1790 ps_dec_ip = (ivd_video_decode_ip_t *)pv_api_ip; 1791 ps_dec_op = (ivd_video_decode_op_t *)pv_api_op; 1792 1793 { 1794 UWORD32 u4_size; 1795 u4_size = ps_dec_op->u4_size; 1796 memset(ps_dec_op, 0, sizeof(ivd_video_decode_op_t)); 1797 ps_dec_op->u4_size = u4_size; 1798 } 1799 1800 ps_dec->pv_dec_out = ps_dec_op; 1801 if(ps_dec->init_done != 1) 1802 { 1803 return IV_FAIL; 1804 } 1805 1806 /*Data memory barries instruction,so that bitstream write by the application is complete*/ 1807 DATA_SYNC(); 1808 1809 if(0 == ps_dec->u1_flushfrm) 1810 { 1811 if(ps_dec_ip->pv_stream_buffer == NULL) 1812 { 1813 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1814 ps_dec_op->u4_error_code |= IVD_DEC_FRM_BS_BUF_NULL; 1815 return IV_FAIL; 1816 } 1817 if(ps_dec_ip->u4_num_Bytes <= 0) 1818 { 1819 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1820 ps_dec_op->u4_error_code |= IVD_DEC_NUMBYTES_INV; 1821 return IV_FAIL; 1822 1823 } 1824 } 1825 ps_dec->u1_pic_decode_done = 0; 1826 1827 ps_dec_op->u4_num_bytes_consumed = 0; 1828 1829 ps_dec->ps_out_buffer = NULL; 1830 1831 if(ps_dec_ip->u4_size 1832 >= offsetof(ivd_video_decode_ip_t, s_out_buffer)) 1833 ps_dec->ps_out_buffer = &ps_dec_ip->s_out_buffer; 1834 1835 ps_dec->u4_fmt_conv_cur_row = 0; 1836 1837 ps_dec->u4_output_present = 0; 1838 ps_dec->s_disp_op.u4_error_code = 1; 1839 ps_dec->u4_fmt_conv_num_rows = FMT_CONV_NUM_ROWS; 1840 if(0 == ps_dec->u4_share_disp_buf 1841 && ps_dec->i4_decode_header == 0) 1842 { 1843 UWORD32 i; 1844 if((ps_dec->ps_out_buffer->u4_num_bufs == 0) || 1845 (ps_dec->ps_out_buffer->u4_num_bufs > IVD_VIDDEC_MAX_IO_BUFFERS)) 1846 { 1847 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1848 ps_dec_op->u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS; 1849 return IV_FAIL; 1850 } 1851 1852 for(i = 0; i < ps_dec->ps_out_buffer->u4_num_bufs; i++) 1853 { 1854 if(ps_dec->ps_out_buffer->pu1_bufs[i] == NULL) 1855 { 1856 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1857 ps_dec_op->u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL; 1858 return IV_FAIL; 1859 } 1860 1861 if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i] == 0) 1862 { 1863 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1864 ps_dec_op->u4_error_code |= 1865 IVD_DISP_FRM_ZERO_OP_BUF_SIZE; 1866 return IV_FAIL; 1867 } 1868 } 1869 } 1870 1871 if(ps_dec->u4_total_frames_decoded >= NUM_FRAMES_LIMIT) 1872 { 1873 ps_dec_op->u4_error_code = ERROR_FRAME_LIMIT_OVER; 1874 return IV_FAIL; 1875 } 1876 1877 /* ! */ 1878 ps_dec->u4_ts = ps_dec_ip->u4_ts; 1879 1880 ps_dec_op->u4_error_code = 0; 1881 ps_dec_op->e_pic_type = -1; 1882 ps_dec_op->u4_output_present = 0; 1883 ps_dec_op->u4_frame_decoded_flag = 0; 1884 1885 ps_dec->i4_frametype = -1; 1886 ps_dec->i4_content_type = -1; 1887 1888 ps_dec->u4_slice_start_code_found = 0; 1889 1890 /* In case the deocder is not in flush mode(in shared mode), 1891 then decoder has to pick up a buffer to write current frame. 1892 Check if a frame is available in such cases */ 1893 1894 if(ps_dec->u1_init_dec_flag == 1 && ps_dec->u4_share_disp_buf == 1 1895 && ps_dec->u1_flushfrm == 0) 1896 { 1897 UWORD32 i; 1898 1899 WORD32 disp_avail = 0, free_id; 1900 1901 /* Check if at least one buffer is available with the codec */ 1902 /* If not then return to application with error */ 1903 for(i = 0; i < ps_dec->u1_pic_bufs; i++) 1904 { 1905 if(0 == ps_dec->u4_disp_buf_mapping[i] 1906 || 1 == ps_dec->u4_disp_buf_to_be_freed[i]) 1907 { 1908 disp_avail = 1; 1909 break; 1910 } 1911 1912 } 1913 1914 if(0 == disp_avail) 1915 { 1916 /* If something is queued for display wait for that buffer to be returned */ 1917 1918 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL; 1919 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 1920 return (IV_FAIL); 1921 } 1922 1923 while(1) 1924 { 1925 pic_buffer_t *ps_pic_buf; 1926 ps_pic_buf = (pic_buffer_t *)ih264_buf_mgr_get_next_free( 1927 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, &free_id); 1928 1929 if(ps_pic_buf == NULL) 1930 { 1931 UWORD32 i, display_queued = 0; 1932 1933 /* check if any buffer was given for display which is not returned yet */ 1934 for(i = 0; i < (MAX_DISP_BUFS_NEW); i++) 1935 { 1936 if(0 != ps_dec->u4_disp_buf_mapping[i]) 1937 { 1938 display_queued = 1; 1939 break; 1940 } 1941 } 1942 /* If some buffer is queued for display, then codec has to singal an error and wait 1943 for that buffer to be returned. 1944 If nothing is queued for display then codec has ownership of all display buffers 1945 and it can reuse any of the existing buffers and continue decoding */ 1946 1947 if(1 == display_queued) 1948 { 1949 /* If something is queued for display wait for that buffer to be returned */ 1950 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL; 1951 ps_dec_op->u4_error_code |= (1 1952 << IVD_UNSUPPORTEDPARAM); 1953 return (IV_FAIL); 1954 } 1955 } 1956 else 1957 { 1958 /* If the buffer is with display, then mark it as in use and then look for a buffer again */ 1959 if(1 == ps_dec->u4_disp_buf_mapping[free_id]) 1960 { 1961 ih264_buf_mgr_set_status( 1962 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 1963 free_id, 1964 BUF_MGR_IO); 1965 } 1966 else 1967 { 1968 /** 1969 * Found a free buffer for present call. Release it now. 1970 * Will be again obtained later. 1971 */ 1972 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 1973 free_id, 1974 BUF_MGR_IO); 1975 break; 1976 } 1977 } 1978 } 1979 1980 } 1981 1982 if(ps_dec->u1_flushfrm) 1983 { 1984 if(ps_dec->u1_init_dec_flag == 0) 1985 { 1986 /*Come out of flush mode and return*/ 1987 ps_dec->u1_flushfrm = 0; 1988 return (IV_FAIL); 1989 } 1990 1991 1992 1993 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer, 1994 &(ps_dec->s_disp_op)); 1995 if(0 == ps_dec->s_disp_op.u4_error_code) 1996 { 1997 /* check output buffer size given by the application */ 1998 if(check_app_out_buf_size(ps_dec) != IV_SUCCESS) 1999 { 2000 ps_dec_op->u4_error_code= IVD_DISP_FRM_ZERO_OP_BUF_SIZE; 2001 return (IV_FAIL); 2002 } 2003 2004 ps_dec->u4_fmt_conv_cur_row = 0; 2005 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht; 2006 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op), 2007 ps_dec->u4_fmt_conv_cur_row, 2008 ps_dec->u4_fmt_conv_num_rows); 2009 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows; 2010 ps_dec->u4_output_present = 1; 2011 2012 } 2013 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op)); 2014 2015 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width; 2016 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height; 2017 2018 ps_dec_op->u4_new_seq = 0; 2019 2020 ps_dec_op->u4_output_present = ps_dec->u4_output_present; 2021 ps_dec_op->u4_progressive_frame_flag = 2022 ps_dec->s_disp_op.u4_progressive_frame_flag; 2023 ps_dec_op->e_output_format = 2024 ps_dec->s_disp_op.e_output_format; 2025 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf; 2026 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type; 2027 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts; 2028 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id; 2029 2030 /*In the case of flush ,since no frame is decoded set pic type as invalid*/ 2031 ps_dec_op->u4_is_ref_flag = -1; 2032 ps_dec_op->e_pic_type = IV_NA_FRAME; 2033 ps_dec_op->u4_frame_decoded_flag = 0; 2034 2035 if(0 == ps_dec->s_disp_op.u4_error_code) 2036 { 2037 return (IV_SUCCESS); 2038 } 2039 else 2040 return (IV_FAIL); 2041 2042 } 2043 if(ps_dec->u1_res_changed == 1) 2044 { 2045 /*if resolution has changed and all buffers have been flushed, reset decoder*/ 2046 ih264d_init_decoder(ps_dec); 2047 } 2048 2049 ps_dec->u4_prev_nal_skipped = 0; 2050 2051 ps_dec->u2_cur_mb_addr = 0; 2052 ps_dec->u2_total_mbs_coded = 0; 2053 ps_dec->u2_cur_slice_num = 0; 2054 ps_dec->cur_dec_mb_num = 0; 2055 ps_dec->cur_recon_mb_num = 0; 2056 ps_dec->u4_first_slice_in_pic = 1; 2057 ps_dec->u1_slice_header_done = 0; 2058 ps_dec->u1_dangling_field = 0; 2059 2060 ps_dec->u4_dec_thread_created = 0; 2061 ps_dec->u4_bs_deblk_thread_created = 0; 2062 ps_dec->u4_cur_bs_mb_num = 0; 2063 ps_dec->u4_start_recon_deblk = 0; 2064 ps_dec->u4_sps_cnt_in_process = 0; 2065 2066 DEBUG_THREADS_PRINTF(" Starting process call\n"); 2067 2068 2069 ps_dec->u4_pic_buf_got = 0; 2070 2071 do 2072 { 2073 WORD32 buf_size; 2074 2075 pu1_buf = (UWORD8*)ps_dec_ip->pv_stream_buffer 2076 + ps_dec_op->u4_num_bytes_consumed; 2077 2078 u4_max_ofst = ps_dec_ip->u4_num_Bytes 2079 - ps_dec_op->u4_num_bytes_consumed; 2080 2081 /* If dynamic bitstream buffer is not allocated and 2082 * header decode is done, then allocate dynamic bitstream buffer 2083 */ 2084 if((NULL == ps_dec->pu1_bits_buf_dynamic) && 2085 (ps_dec->i4_header_decoded & 1)) 2086 { 2087 WORD32 size; 2088 2089 void *pv_buf; 2090 void *pv_mem_ctxt = ps_dec->pv_mem_ctxt; 2091 size = MAX(256000, ps_dec->u2_pic_wd * ps_dec->u2_pic_ht * 3 / 2); 2092 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, 2093 size + EXTRA_BS_OFFSET); 2094 RETURN_IF((NULL == pv_buf), IV_FAIL); 2095 ps_dec->pu1_bits_buf_dynamic = pv_buf; 2096 ps_dec->u4_dynamic_bits_buf_size = size; 2097 } 2098 2099 if(ps_dec->pu1_bits_buf_dynamic) 2100 { 2101 pu1_bitstrm_buf = ps_dec->pu1_bits_buf_dynamic; 2102 buf_size = ps_dec->u4_dynamic_bits_buf_size; 2103 } 2104 else 2105 { 2106 pu1_bitstrm_buf = ps_dec->pu1_bits_buf_static; 2107 buf_size = ps_dec->u4_static_bits_buf_size; 2108 } 2109 2110 u4_next_is_aud = 0; 2111 2112 buflen = ih264d_find_start_code(pu1_buf, 0, u4_max_ofst, 2113 &u4_length_of_start_code, 2114 &u4_next_is_aud); 2115 2116 if(buflen == -1) 2117 buflen = 0; 2118 /* Ignore bytes beyond the allocated size of intermediate buffer */ 2119 /* Since 8 bytes are read ahead, ensure 8 bytes are free at the 2120 end of the buffer, which will be memset to 0 after emulation prevention */ 2121 buflen = MIN(buflen, buf_size - 8); 2122 2123 bytes_consumed = buflen + u4_length_of_start_code; 2124 ps_dec_op->u4_num_bytes_consumed += bytes_consumed; 2125 2126 { 2127 UWORD8 u1_firstbyte, u1_nal_ref_idc; 2128 2129 if(ps_dec->i4_app_skip_mode == IVD_SKIP_B) 2130 { 2131 u1_firstbyte = *(pu1_buf + u4_length_of_start_code); 2132 u1_nal_ref_idc = (UWORD8)(NAL_REF_IDC(u1_firstbyte)); 2133 if(u1_nal_ref_idc == 0) 2134 { 2135 /*skip non reference frames*/ 2136 cur_slice_is_nonref = 1; 2137 continue; 2138 } 2139 else 2140 { 2141 if(1 == cur_slice_is_nonref) 2142 { 2143 /*We have encountered a referenced frame,return to app*/ 2144 ps_dec_op->u4_num_bytes_consumed -= 2145 bytes_consumed; 2146 ps_dec_op->e_pic_type = IV_B_FRAME; 2147 ps_dec_op->u4_error_code = 2148 IVD_DEC_FRM_SKIPPED; 2149 ps_dec_op->u4_error_code |= (1 2150 << IVD_UNSUPPORTEDPARAM); 2151 ps_dec_op->u4_frame_decoded_flag = 0; 2152 ps_dec_op->u4_size = 2153 sizeof(ivd_video_decode_op_t); 2154 /*signal the decode thread*/ 2155 ih264d_signal_decode_thread(ps_dec); 2156 /* close deblock thread if it is not closed yet*/ 2157 if(ps_dec->u4_num_cores == 3) 2158 { 2159 ih264d_signal_bs_deblk_thread(ps_dec); 2160 } 2161 2162 return (IV_FAIL); 2163 } 2164 } 2165 2166 } 2167 2168 } 2169 2170 2171 if(buflen) 2172 { 2173 memcpy(pu1_bitstrm_buf, pu1_buf + u4_length_of_start_code, 2174 buflen); 2175 /* Decoder may read extra 8 bytes near end of the frame */ 2176 if((buflen + 8) < buf_size) 2177 { 2178 memset(pu1_bitstrm_buf + buflen, 0, 8); 2179 } 2180 u4_first_start_code_found = 1; 2181 2182 } 2183 else 2184 { 2185 /*start code not found*/ 2186 2187 if(u4_first_start_code_found == 0) 2188 { 2189 /*no start codes found in current process call*/ 2190 2191 ps_dec->i4_error_code = ERROR_START_CODE_NOT_FOUND; 2192 ps_dec_op->u4_error_code |= 1 << IVD_INSUFFICIENTDATA; 2193 2194 if(ps_dec->u4_pic_buf_got == 0) 2195 { 2196 2197 ih264d_fill_output_struct_from_context(ps_dec, 2198 ps_dec_op); 2199 2200 ps_dec_op->u4_error_code = ps_dec->i4_error_code; 2201 ps_dec_op->u4_frame_decoded_flag = 0; 2202 2203 return (IV_FAIL); 2204 } 2205 else 2206 { 2207 ps_dec->u1_pic_decode_done = 1; 2208 continue; 2209 } 2210 } 2211 else 2212 { 2213 /* a start code has already been found earlier in the same process call*/ 2214 frame_data_left = 0; 2215 header_data_left = 0; 2216 continue; 2217 } 2218 2219 } 2220 2221 ps_dec->u4_return_to_app = 0; 2222 ret = ih264d_parse_nal_unit(dec_hdl, ps_dec_op, 2223 pu1_bitstrm_buf, buflen); 2224 if(ret != OK) 2225 { 2226 UWORD32 error = ih264d_map_error(ret); 2227 ps_dec_op->u4_error_code = error | ret; 2228 api_ret_value = IV_FAIL; 2229 2230 if((ret == IVD_RES_CHANGED) 2231 || (ret == IVD_MEM_ALLOC_FAILED) 2232 || (ret == ERROR_UNAVAIL_PICBUF_T) 2233 || (ret == ERROR_UNAVAIL_MVBUF_T) 2234 || (ret == ERROR_INV_SPS_PPS_T) 2235 || (ret == IVD_DISP_FRM_ZERO_OP_BUF_SIZE)) 2236 { 2237 ps_dec->u4_slice_start_code_found = 0; 2238 break; 2239 } 2240 2241 if((ret == ERROR_INCOMPLETE_FRAME) || (ret == ERROR_DANGLING_FIELD_IN_PIC)) 2242 { 2243 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed; 2244 api_ret_value = IV_FAIL; 2245 break; 2246 } 2247 2248 if(ret == ERROR_IN_LAST_SLICE_OF_PIC) 2249 { 2250 api_ret_value = IV_FAIL; 2251 break; 2252 } 2253 2254 } 2255 2256 if(ps_dec->u4_return_to_app) 2257 { 2258 /*We have encountered a referenced frame,return to app*/ 2259 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed; 2260 ps_dec_op->u4_error_code = IVD_DEC_FRM_SKIPPED; 2261 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 2262 ps_dec_op->u4_frame_decoded_flag = 0; 2263 ps_dec_op->u4_size = sizeof(ivd_video_decode_op_t); 2264 /*signal the decode thread*/ 2265 ih264d_signal_decode_thread(ps_dec); 2266 /* close deblock thread if it is not closed yet*/ 2267 if(ps_dec->u4_num_cores == 3) 2268 { 2269 ih264d_signal_bs_deblk_thread(ps_dec); 2270 } 2271 return (IV_FAIL); 2272 2273 } 2274 2275 2276 2277 header_data_left = ((ps_dec->i4_decode_header == 1) 2278 && (ps_dec->i4_header_decoded != 3) 2279 && (ps_dec_op->u4_num_bytes_consumed 2280 < ps_dec_ip->u4_num_Bytes)); 2281 frame_data_left = (((ps_dec->i4_decode_header == 0) 2282 && ((ps_dec->u1_pic_decode_done == 0) 2283 || (u4_next_is_aud == 1))) 2284 && (ps_dec_op->u4_num_bytes_consumed 2285 < ps_dec_ip->u4_num_Bytes)); 2286 } 2287 while(( header_data_left == 1)||(frame_data_left == 1)); 2288 2289 if((ps_dec->u4_pic_buf_got == 1) 2290 && (ret != IVD_MEM_ALLOC_FAILED) 2291 && ps_dec->u2_total_mbs_coded < ps_dec->u2_frm_ht_in_mbs * ps_dec->u2_frm_wd_in_mbs) 2292 { 2293 // last slice - missing/corruption 2294 WORD32 num_mb_skipped; 2295 WORD32 prev_slice_err; 2296 pocstruct_t temp_poc; 2297 WORD32 ret1; 2298 WORD32 ht_in_mbs; 2299 ht_in_mbs = ps_dec->u2_pic_ht >> (4 + ps_dec->ps_cur_slice->u1_field_pic_flag); 2300 num_mb_skipped = (ht_in_mbs * ps_dec->u2_frm_wd_in_mbs) 2301 - ps_dec->u2_total_mbs_coded; 2302 2303 if(ps_dec->u4_first_slice_in_pic && (ps_dec->u4_pic_buf_got == 0)) 2304 prev_slice_err = 1; 2305 else 2306 prev_slice_err = 2; 2307 2308 if(ps_dec->u4_first_slice_in_pic && (ps_dec->u2_total_mbs_coded == 0)) 2309 prev_slice_err = 1; 2310 2311 ret1 = ih264d_mark_err_slice_skip(ps_dec, num_mb_skipped, ps_dec->u1_nal_unit_type == IDR_SLICE_NAL, ps_dec->ps_cur_slice->u2_frame_num, 2312 &temp_poc, prev_slice_err); 2313 2314 if((ret1 == ERROR_UNAVAIL_PICBUF_T) || (ret1 == ERROR_UNAVAIL_MVBUF_T) || 2315 (ret1 == ERROR_INV_SPS_PPS_T)) 2316 { 2317 ret = ret1; 2318 } 2319 } 2320 2321 if((ret == IVD_RES_CHANGED) 2322 || (ret == IVD_MEM_ALLOC_FAILED) 2323 || (ret == ERROR_UNAVAIL_PICBUF_T) 2324 || (ret == ERROR_UNAVAIL_MVBUF_T) 2325 || (ret == ERROR_INV_SPS_PPS_T)) 2326 { 2327 2328 /* signal the decode thread */ 2329 ih264d_signal_decode_thread(ps_dec); 2330 /* close deblock thread if it is not closed yet */ 2331 if(ps_dec->u4_num_cores == 3) 2332 { 2333 ih264d_signal_bs_deblk_thread(ps_dec); 2334 } 2335 /* dont consume bitstream for change in resolution case */ 2336 if(ret == IVD_RES_CHANGED) 2337 { 2338 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed; 2339 } 2340 return IV_FAIL; 2341 } 2342 2343 2344 if(ps_dec->u1_separate_parse) 2345 { 2346 /* If Format conversion is not complete, 2347 complete it here */ 2348 if(ps_dec->u4_num_cores == 2) 2349 { 2350 2351 /*do deblocking of all mbs*/ 2352 if((ps_dec->u4_nmb_deblk == 0) &&(ps_dec->u4_start_recon_deblk == 1) && (ps_dec->ps_cur_sps->u1_mb_aff_flag == 0)) 2353 { 2354 UWORD32 u4_num_mbs,u4_max_addr; 2355 tfr_ctxt_t s_tfr_ctxt; 2356 tfr_ctxt_t *ps_tfr_cxt = &s_tfr_ctxt; 2357 pad_mgr_t *ps_pad_mgr = &ps_dec->s_pad_mgr; 2358 2359 /*BS is done for all mbs while parsing*/ 2360 u4_max_addr = (ps_dec->u2_frm_wd_in_mbs * ps_dec->u2_frm_ht_in_mbs) - 1; 2361 ps_dec->u4_cur_bs_mb_num = u4_max_addr + 1; 2362 2363 2364 ih264d_init_deblk_tfr_ctxt(ps_dec, ps_pad_mgr, ps_tfr_cxt, 2365 ps_dec->u2_frm_wd_in_mbs, 0); 2366 2367 2368 u4_num_mbs = u4_max_addr 2369 - ps_dec->u4_cur_deblk_mb_num + 1; 2370 2371 DEBUG_PERF_PRINTF("mbs left for deblocking= %d \n",u4_num_mbs); 2372 2373 if(u4_num_mbs != 0) 2374 ih264d_check_mb_map_deblk(ps_dec, u4_num_mbs, 2375 ps_tfr_cxt,1); 2376 2377 ps_dec->u4_start_recon_deblk = 0; 2378 2379 } 2380 2381 } 2382 2383 /*signal the decode thread*/ 2384 ih264d_signal_decode_thread(ps_dec); 2385 /* close deblock thread if it is not closed yet*/ 2386 if(ps_dec->u4_num_cores == 3) 2387 { 2388 ih264d_signal_bs_deblk_thread(ps_dec); 2389 } 2390 } 2391 2392 2393 DATA_SYNC(); 2394 2395 2396 if((ps_dec_op->u4_error_code & 0xff) 2397 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED) 2398 { 2399 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width; 2400 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height; 2401 } 2402 2403//Report if header (sps and pps) has not been decoded yet 2404 if(ps_dec->i4_header_decoded != 3) 2405 { 2406 ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA); 2407 2408 } 2409 2410 if(ps_dec->i4_decode_header == 1 && ps_dec->i4_header_decoded != 3) 2411 { 2412 ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA); 2413 2414 } 2415 if(ps_dec->u4_prev_nal_skipped) 2416 { 2417 /*We have encountered a referenced frame,return to app*/ 2418 ps_dec_op->u4_error_code = IVD_DEC_FRM_SKIPPED; 2419 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 2420 ps_dec_op->u4_frame_decoded_flag = 0; 2421 ps_dec_op->u4_size = sizeof(ivd_video_decode_op_t); 2422 /* close deblock thread if it is not closed yet*/ 2423 if(ps_dec->u4_num_cores == 3) 2424 { 2425 ih264d_signal_bs_deblk_thread(ps_dec); 2426 } 2427 return (IV_FAIL); 2428 2429 } 2430 2431 if((ps_dec->u4_pic_buf_got == 1) 2432 && (ERROR_DANGLING_FIELD_IN_PIC != i4_err_status)) 2433 { 2434 /* 2435 * For field pictures, set the bottom and top picture decoded u4_flag correctly. 2436 */ 2437 2438 if(ps_dec->ps_cur_slice->u1_field_pic_flag) 2439 { 2440 if(1 == ps_dec->ps_cur_slice->u1_bottom_field_flag) 2441 { 2442 ps_dec->u1_top_bottom_decoded |= BOT_FIELD_ONLY; 2443 } 2444 else 2445 { 2446 ps_dec->u1_top_bottom_decoded |= TOP_FIELD_ONLY; 2447 } 2448 } 2449 else 2450 { 2451 ps_dec->u1_top_bottom_decoded = TOP_FIELD_ONLY | BOT_FIELD_ONLY; 2452 } 2453 2454 /* if new frame in not found (if we are still getting slices from previous frame) 2455 * ih264d_deblock_display is not called. Such frames will not be added to reference /display 2456 */ 2457 if ((ps_dec->ps_dec_err_status->u1_err_flag & REJECT_CUR_PIC) == 0) 2458 { 2459 /* Calling Function to deblock Picture and Display */ 2460 ret = ih264d_deblock_display(ps_dec); 2461 } 2462 2463 2464 /*set to complete ,as we dont support partial frame decode*/ 2465 if(ps_dec->i4_header_decoded == 3) 2466 { 2467 ps_dec->u2_total_mbs_coded = ps_dec->ps_cur_sps->u2_max_mb_addr + 1; 2468 } 2469 2470 /*Update the i4_frametype at the end of picture*/ 2471 if(ps_dec->ps_cur_slice->u1_nal_unit_type == IDR_SLICE_NAL) 2472 { 2473 ps_dec->i4_frametype = IV_IDR_FRAME; 2474 } 2475 else if(ps_dec->i4_pic_type == B_SLICE) 2476 { 2477 ps_dec->i4_frametype = IV_B_FRAME; 2478 } 2479 else if(ps_dec->i4_pic_type == P_SLICE) 2480 { 2481 ps_dec->i4_frametype = IV_P_FRAME; 2482 } 2483 else if(ps_dec->i4_pic_type == I_SLICE) 2484 { 2485 ps_dec->i4_frametype = IV_I_FRAME; 2486 } 2487 else 2488 { 2489 H264_DEC_DEBUG_PRINT("Shouldn't come here\n"); 2490 } 2491 2492 //Update the content type 2493 ps_dec->i4_content_type = ps_dec->ps_cur_slice->u1_field_pic_flag; 2494 2495 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded + 2; 2496 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded 2497 - ps_dec->ps_cur_slice->u1_field_pic_flag; 2498 2499 } 2500 2501 /* close deblock thread if it is not closed yet*/ 2502 if(ps_dec->u4_num_cores == 3) 2503 { 2504 ih264d_signal_bs_deblk_thread(ps_dec); 2505 } 2506 2507 2508 { 2509 /* In case the decoder is configured to run in low delay mode, 2510 * then get display buffer and then format convert. 2511 * Note in this mode, format conversion does not run paralelly in a thread and adds to the codec cycles 2512 */ 2513 2514 if((IVD_DECODE_FRAME_OUT == ps_dec->e_frm_out_mode) 2515 && ps_dec->u1_init_dec_flag) 2516 { 2517 2518 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer, 2519 &(ps_dec->s_disp_op)); 2520 if(0 == ps_dec->s_disp_op.u4_error_code) 2521 { 2522 ps_dec->u4_fmt_conv_cur_row = 0; 2523 ps_dec->u4_output_present = 1; 2524 } 2525 } 2526 2527 ih264d_fill_output_struct_from_context(ps_dec, ps_dec_op); 2528 2529 /* If Format conversion is not complete, 2530 complete it here */ 2531 if(ps_dec->u4_output_present && 2532 (ps_dec->u4_fmt_conv_cur_row < ps_dec->s_disp_frame_info.u4_y_ht)) 2533 { 2534 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht 2535 - ps_dec->u4_fmt_conv_cur_row; 2536 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op), 2537 ps_dec->u4_fmt_conv_cur_row, 2538 ps_dec->u4_fmt_conv_num_rows); 2539 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows; 2540 } 2541 2542 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op)); 2543 } 2544 2545 if(ps_dec->i4_decode_header == 1 && (ps_dec->i4_header_decoded & 1) == 1) 2546 { 2547 ps_dec_op->u4_progressive_frame_flag = 1; 2548 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 2549 { 2550 if((0 == ps_dec->ps_sps->u1_frame_mbs_only_flag) 2551 && (0 == ps_dec->ps_sps->u1_mb_aff_flag)) 2552 ps_dec_op->u4_progressive_frame_flag = 0; 2553 2554 } 2555 } 2556 2557 if((TOP_FIELD_ONLY | BOT_FIELD_ONLY) == ps_dec->u1_top_bottom_decoded) 2558 { 2559 ps_dec->u1_top_bottom_decoded = 0; 2560 } 2561 /*--------------------------------------------------------------------*/ 2562 /* Do End of Pic processing. */ 2563 /* Should be called only if frame was decoded in previous process call*/ 2564 /*--------------------------------------------------------------------*/ 2565 if(ps_dec->u4_pic_buf_got == 1) 2566 { 2567 if(1 == ps_dec->u1_last_pic_not_decoded) 2568 { 2569 ret = ih264d_end_of_pic_dispbuf_mgr(ps_dec); 2570 2571 if(ret != OK) 2572 return ret; 2573 2574 ret = ih264d_end_of_pic(ps_dec); 2575 if(ret != OK) 2576 return ret; 2577 } 2578 else 2579 { 2580 ret = ih264d_end_of_pic(ps_dec); 2581 if(ret != OK) 2582 return ret; 2583 } 2584 2585 } 2586 2587 2588 /*Data memory barrier instruction,so that yuv write by the library is complete*/ 2589 DATA_SYNC(); 2590 2591 H264_DEC_DEBUG_PRINT("The num bytes consumed: %d\n", 2592 ps_dec_op->u4_num_bytes_consumed); 2593 return api_ret_value; 2594} 2595 2596WORD32 ih264d_get_version(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 2597{ 2598 char version_string[MAXVERSION_STRLEN + 1]; 2599 UWORD32 version_string_len; 2600 2601 ivd_ctl_getversioninfo_ip_t *ps_ip; 2602 ivd_ctl_getversioninfo_op_t *ps_op; 2603 2604 ps_ip = (ivd_ctl_getversioninfo_ip_t *)pv_api_ip; 2605 ps_op = (ivd_ctl_getversioninfo_op_t *)pv_api_op; 2606 UNUSED(dec_hdl); 2607 ps_op->u4_error_code = IV_SUCCESS; 2608 2609 VERSION(version_string, CODEC_NAME, CODEC_RELEASE_TYPE, CODEC_RELEASE_VER, 2610 CODEC_VENDOR); 2611 2612 if((WORD32)ps_ip->u4_version_buffer_size <= 0) 2613 { 2614 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT; 2615 return (IV_FAIL); 2616 } 2617 2618 version_string_len = strnlen(version_string, MAXVERSION_STRLEN) + 1; 2619 2620 if(ps_ip->u4_version_buffer_size >= version_string_len) //(WORD32)sizeof(sizeof(version_string))) 2621 { 2622 memcpy(ps_ip->pv_version_buffer, version_string, version_string_len); 2623 ps_op->u4_error_code = IV_SUCCESS; 2624 } 2625 else 2626 { 2627 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT; 2628 return IV_FAIL; 2629 } 2630 return (IV_SUCCESS); 2631} 2632 2633/*****************************************************************************/ 2634/* */ 2635/* Function Name : ih264d_get_display_frame */ 2636/* */ 2637/* Description : */ 2638/* Inputs :iv_obj_t decoder handle */ 2639/* :pv_api_ip pointer to input structure */ 2640/* :pv_api_op pointer to output structure */ 2641/* Outputs : */ 2642/* Returns : void */ 2643/* */ 2644/* Issues : none */ 2645/* */ 2646/* Revision History: */ 2647/* */ 2648/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2649/* 22 10 2008 100356 Draft */ 2650/* */ 2651/*****************************************************************************/ 2652WORD32 ih264d_get_display_frame(iv_obj_t *dec_hdl, 2653 void *pv_api_ip, 2654 void *pv_api_op) 2655{ 2656 2657 UNUSED(dec_hdl); 2658 UNUSED(pv_api_ip); 2659 UNUSED(pv_api_op); 2660 // This function is no longer needed, output is returned in the process() 2661 return IV_FAIL; 2662} 2663 2664/*****************************************************************************/ 2665/* */ 2666/* Function Name : ih264d_set_display_frame */ 2667/* */ 2668/* Description : */ 2669/* */ 2670/* Inputs :iv_obj_t decoder handle */ 2671/* :pv_api_ip pointer to input structure */ 2672/* :pv_api_op pointer to output structure */ 2673/* Outputs : */ 2674/* Returns : void */ 2675/* */ 2676/* Issues : none */ 2677/* */ 2678/* Revision History: */ 2679/* */ 2680/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2681/* 22 10 2008 100356 Draft */ 2682/* */ 2683/*****************************************************************************/ 2684WORD32 ih264d_set_display_frame(iv_obj_t *dec_hdl, 2685 void *pv_api_ip, 2686 void *pv_api_op) 2687{ 2688 2689 UWORD32 u4_disp_buf_size[3], u4_num_disp_bufs; 2690 ivd_set_display_frame_ip_t *dec_disp_ip; 2691 ivd_set_display_frame_op_t *dec_disp_op; 2692 2693 UWORD32 i; 2694 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 2695 2696 dec_disp_ip = (ivd_set_display_frame_ip_t *)pv_api_ip; 2697 dec_disp_op = (ivd_set_display_frame_op_t *)pv_api_op; 2698 dec_disp_op->u4_error_code = 0; 2699 2700 2701 ps_dec->u4_num_disp_bufs = 0; 2702 if(ps_dec->u4_share_disp_buf) 2703 { 2704 UWORD32 u4_num_bufs = dec_disp_ip->num_disp_bufs; 2705 2706 u4_num_bufs = MIN(u4_num_bufs, MAX_DISP_BUFS_NEW); 2707 2708 ps_dec->u4_num_disp_bufs = u4_num_bufs; 2709 2710 /* Get the number and sizes of the first buffer. Compare this with the 2711 * rest to make sure all the buffers are of the same size. 2712 */ 2713 u4_num_disp_bufs = dec_disp_ip->s_disp_buffer[0].u4_num_bufs; 2714 2715 u4_disp_buf_size[0] = 2716 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[0]; 2717 u4_disp_buf_size[1] = 2718 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[1]; 2719 u4_disp_buf_size[2] = 2720 dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[2]; 2721 2722 for(i = 0; i < u4_num_bufs; i++) 2723 { 2724 if(dec_disp_ip->s_disp_buffer[i].u4_num_bufs != u4_num_disp_bufs) 2725 { 2726 return IV_FAIL; 2727 } 2728 2729 if((dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0] 2730 != u4_disp_buf_size[0]) 2731 || (dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1] 2732 != u4_disp_buf_size[1]) 2733 || (dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2] 2734 != u4_disp_buf_size[2])) 2735 { 2736 return IV_FAIL; 2737 } 2738 2739 ps_dec->disp_bufs[i].u4_num_bufs = 2740 dec_disp_ip->s_disp_buffer[i].u4_num_bufs; 2741 2742 ps_dec->disp_bufs[i].buf[0] = 2743 dec_disp_ip->s_disp_buffer[i].pu1_bufs[0]; 2744 ps_dec->disp_bufs[i].buf[1] = 2745 dec_disp_ip->s_disp_buffer[i].pu1_bufs[1]; 2746 ps_dec->disp_bufs[i].buf[2] = 2747 dec_disp_ip->s_disp_buffer[i].pu1_bufs[2]; 2748 2749 ps_dec->disp_bufs[i].u4_bufsize[0] = 2750 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0]; 2751 ps_dec->disp_bufs[i].u4_bufsize[1] = 2752 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1]; 2753 ps_dec->disp_bufs[i].u4_bufsize[2] = 2754 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2]; 2755 2756 } 2757 } 2758 return IV_SUCCESS; 2759 2760} 2761 2762/*****************************************************************************/ 2763/* */ 2764/* Function Name : ih264d_set_flush_mode */ 2765/* */ 2766/* Description : */ 2767/* */ 2768/* Inputs :iv_obj_t decoder handle */ 2769/* :pv_api_ip pointer to input structure */ 2770/* :pv_api_op pointer to output structure */ 2771/* Globals : <Does it use any global variables?> */ 2772/* Outputs : */ 2773/* Returns : void */ 2774/* */ 2775/* Issues : none */ 2776/* */ 2777/* Revision History: */ 2778/* */ 2779/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2780/* 22 10 2008 100356 Draft */ 2781/* */ 2782/*****************************************************************************/ 2783WORD32 ih264d_set_flush_mode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 2784{ 2785 dec_struct_t * ps_dec; 2786 ivd_ctl_flush_op_t *ps_ctl_op = (ivd_ctl_flush_op_t*)pv_api_op; 2787 ps_ctl_op->u4_error_code = 0; 2788 2789 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 2790 UNUSED(pv_api_ip); 2791 /* ! */ 2792 /* Signal flush frame control call */ 2793 ps_dec->u1_flushfrm = 1; 2794 2795 if(ps_dec->u1_init_dec_flag == 1) 2796 { 2797 ih264d_release_pics_in_dpb((void *)ps_dec, ps_dec->u1_pic_bufs); 2798 ih264d_release_display_bufs(ps_dec); 2799 } 2800 2801 ps_ctl_op->u4_error_code = 0; 2802 2803 /* Ignore dangling fields during flush */ 2804 ps_dec->u1_top_bottom_decoded = 0; 2805 2806 return IV_SUCCESS; 2807} 2808 2809/*****************************************************************************/ 2810/* */ 2811/* Function Name : ih264d_get_status */ 2812/* */ 2813/* Description : */ 2814/* */ 2815/* Inputs :iv_obj_t decoder handle */ 2816/* :pv_api_ip pointer to input structure */ 2817/* :pv_api_op pointer to output structure */ 2818/* Globals : <Does it use any global variables?> */ 2819/* Outputs : */ 2820/* Returns : void */ 2821/* */ 2822/* Issues : none */ 2823/* */ 2824/* Revision History: */ 2825/* */ 2826/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2827/* 22 10 2008 100356 Draft */ 2828/* */ 2829/*****************************************************************************/ 2830 2831WORD32 ih264d_get_status(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 2832{ 2833 2834 UWORD32 i; 2835 dec_struct_t * ps_dec; 2836 UWORD32 pic_wd, pic_ht; 2837 ivd_ctl_getstatus_op_t *ps_ctl_op = (ivd_ctl_getstatus_op_t*)pv_api_op; 2838 UNUSED(pv_api_ip); 2839 ps_ctl_op->u4_error_code = 0; 2840 2841 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 2842 2843 2844 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 2845 { 2846 ps_ctl_op->u4_pic_ht = ps_dec->u2_disp_height; 2847 ps_ctl_op->u4_pic_wd = ps_dec->u2_disp_width; 2848 2849 if(0 == ps_dec->u4_share_disp_buf) 2850 { 2851 pic_wd = ps_dec->u2_disp_width; 2852 pic_ht = ps_dec->u2_disp_height; 2853 2854 } 2855 else 2856 { 2857 pic_wd = ps_dec->u2_frm_wd_y; 2858 pic_ht = ps_dec->u2_frm_ht_y; 2859 } 2860 } 2861 else 2862 { 2863 pic_wd = 0; 2864 pic_ht = 0; 2865 2866 ps_ctl_op->u4_pic_ht = pic_wd; 2867 ps_ctl_op->u4_pic_wd = pic_ht; 2868 2869 if(1 == ps_dec->u4_share_disp_buf) 2870 { 2871 pic_wd += (PAD_LEN_Y_H << 1); 2872 pic_ht += (PAD_LEN_Y_V << 2); 2873 2874 } 2875 2876 } 2877 2878 if(ps_dec->u4_app_disp_width > pic_wd) 2879 pic_wd = ps_dec->u4_app_disp_width; 2880 if(0 == ps_dec->u4_share_disp_buf) 2881 ps_ctl_op->u4_num_disp_bufs = 1; 2882 else 2883 { 2884 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 2885 { 2886 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) && 2887 (1 == ps_dec->ps_cur_sps->s_vui.u1_bitstream_restriction_flag)) 2888 { 2889 ps_ctl_op->u4_num_disp_bufs = 2890 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 1; 2891 } 2892 else 2893 { 2894 /*if VUI is not present assume maximum possible refrence frames for the level, 2895 * as max reorder frames*/ 2896 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size(ps_dec->ps_cur_sps); 2897 } 2898 2899 ps_ctl_op->u4_num_disp_bufs += 2900 ps_dec->ps_cur_sps->u1_num_ref_frames + 1; 2901 } 2902 else 2903 { 2904 ps_ctl_op->u4_num_disp_bufs = 32; 2905 } 2906 ps_ctl_op->u4_num_disp_bufs = MAX( 2907 ps_ctl_op->u4_num_disp_bufs, 6); 2908 ps_ctl_op->u4_num_disp_bufs = MIN( 2909 ps_ctl_op->u4_num_disp_bufs, 32); 2910 } 2911 2912 ps_ctl_op->u4_error_code = ps_dec->i4_error_code; 2913 2914 ps_ctl_op->u4_frame_rate = 0; //make it proper 2915 ps_ctl_op->u4_bit_rate = 0; //make it proper 2916 ps_ctl_op->e_content_type = ps_dec->i4_content_type; 2917 ps_ctl_op->e_output_chroma_format = ps_dec->u1_chroma_format; 2918 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS; 2919 2920 if(ps_dec->u1_chroma_format == IV_YUV_420P) 2921 { 2922 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420; 2923 } 2924 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE) 2925 { 2926 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE; 2927 } 2928 else if(ps_dec->u1_chroma_format == IV_RGB_565) 2929 { 2930 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565; 2931 } 2932 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 2933 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 2934 { 2935 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420SP; 2936 } 2937 2938 else 2939 { 2940 //Invalid chroma format; Error code may be updated, verify in testing if needed 2941 ps_ctl_op->u4_error_code = ERROR_FEATURE_UNAVAIL; 2942 return IV_FAIL; 2943 } 2944 2945 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++) 2946 { 2947 ps_ctl_op->u4_min_in_buf_size[i] = MAX(256000, pic_wd * pic_ht * 3 / 2); 2948 } 2949 2950 /*!*/ 2951 if(ps_dec->u1_chroma_format == IV_YUV_420P) 2952 { 2953 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht); 2954 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht) 2955 >> 2; 2956 ps_ctl_op->u4_min_out_buf_size[2] = (pic_wd * pic_ht) 2957 >> 2; 2958 } 2959 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE) 2960 { 2961 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht) 2962 * 2; 2963 ps_ctl_op->u4_min_out_buf_size[1] = 2964 ps_ctl_op->u4_min_out_buf_size[2] = 0; 2965 } 2966 else if(ps_dec->u1_chroma_format == IV_RGB_565) 2967 { 2968 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht) 2969 * 2; 2970 ps_ctl_op->u4_min_out_buf_size[1] = 2971 ps_ctl_op->u4_min_out_buf_size[2] = 0; 2972 } 2973 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 2974 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 2975 { 2976 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht); 2977 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht) 2978 >> 1; 2979 ps_ctl_op->u4_min_out_buf_size[2] = 0; 2980 } 2981 2982 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs; 2983 return IV_SUCCESS; 2984} 2985 2986/*****************************************************************************/ 2987/* */ 2988/* Function Name : ih264d_get_buf_info */ 2989/* */ 2990/* Description : */ 2991/* */ 2992/* Inputs :iv_obj_t decoder handle */ 2993/* :pv_api_ip pointer to input structure */ 2994/* :pv_api_op pointer to output structure */ 2995/* Globals : <Does it use any global variables?> */ 2996/* Outputs : */ 2997/* Returns : void */ 2998/* */ 2999/* Issues : none */ 3000/* */ 3001/* Revision History: */ 3002/* */ 3003/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3004/* 22 10 2008 100356 Draft */ 3005/* */ 3006/*****************************************************************************/ 3007WORD32 ih264d_get_buf_info(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3008{ 3009 3010 dec_struct_t * ps_dec; 3011 UWORD8 i = 0; // Default for 420P format 3012 UWORD16 pic_wd, pic_ht; 3013 ivd_ctl_getbufinfo_op_t *ps_ctl_op = 3014 (ivd_ctl_getbufinfo_op_t*)pv_api_op; 3015 UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS]; 3016 UNUSED(pv_api_ip); 3017 3018 ps_ctl_op->u4_error_code = 0; 3019 3020 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 3021 3022 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS; 3023 3024 3025 ps_ctl_op->u4_num_disp_bufs = 1; 3026 3027 3028 pic_wd = 0; 3029 pic_ht = 0; 3030 3031 if(ps_dec->i4_header_decoded == 3) 3032 { 3033 3034 if(0 == ps_dec->u4_share_disp_buf) 3035 { 3036 pic_wd = ps_dec->u2_disp_width; 3037 pic_ht = ps_dec->u2_disp_height; 3038 3039 } 3040 else 3041 { 3042 pic_wd = ps_dec->u2_frm_wd_y; 3043 pic_ht = ps_dec->u2_frm_ht_y; 3044 } 3045 3046 } 3047 3048 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++) 3049 { 3050 ps_ctl_op->u4_min_in_buf_size[i] = MAX(256000, pic_wd * pic_ht * 3 / 2); 3051 } 3052 if((WORD32)ps_dec->u4_app_disp_width > pic_wd) 3053 pic_wd = ps_dec->u4_app_disp_width; 3054 3055 if(0 == ps_dec->u4_share_disp_buf) 3056 ps_ctl_op->u4_num_disp_bufs = 1; 3057 else 3058 { 3059 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 3060 { 3061 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) && 3062 (1 == ps_dec->ps_cur_sps->s_vui.u1_bitstream_restriction_flag)) 3063 { 3064 ps_ctl_op->u4_num_disp_bufs = 3065 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 1; 3066 } 3067 else 3068 { 3069 /*if VUI is not present assume maximum possible refrence frames for the level, 3070 * as max reorder frames*/ 3071 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size(ps_dec->ps_cur_sps); 3072 } 3073 3074 ps_ctl_op->u4_num_disp_bufs += 3075 ps_dec->ps_cur_sps->u1_num_ref_frames + 1; 3076 3077 } 3078 else 3079 { 3080 ps_ctl_op->u4_num_disp_bufs = 32; 3081 3082 } 3083 3084 ps_ctl_op->u4_num_disp_bufs = MAX( 3085 ps_ctl_op->u4_num_disp_bufs, 6); 3086 ps_ctl_op->u4_num_disp_bufs = MIN( 3087 ps_ctl_op->u4_num_disp_bufs, 32); 3088 } 3089 3090 ps_ctl_op->u4_min_num_out_bufs = ih264d_get_outbuf_size( 3091 pic_wd, pic_ht, ps_dec->u1_chroma_format, 3092 &au4_min_out_buf_size[0]); 3093 3094 for(i = 0; i < ps_ctl_op->u4_min_num_out_bufs; i++) 3095 { 3096 ps_ctl_op->u4_min_out_buf_size[i] = au4_min_out_buf_size[i]; 3097 } 3098 3099 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs; 3100 3101 return IV_SUCCESS; 3102} 3103 3104/*****************************************************************************/ 3105/* */ 3106/* Function Name : ih264d_set_params */ 3107/* */ 3108/* Description : */ 3109/* */ 3110/* Inputs :iv_obj_t decoder handle */ 3111/* :pv_api_ip pointer to input structure */ 3112/* :pv_api_op pointer to output structure */ 3113/* Outputs : */ 3114/* Returns : void */ 3115/* */ 3116/* Issues : none */ 3117/* */ 3118/* Revision History: */ 3119/* */ 3120/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3121/* 22 10 2008 100356 Draft */ 3122/* */ 3123/*****************************************************************************/ 3124WORD32 ih264d_set_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3125{ 3126 3127 dec_struct_t * ps_dec; 3128 WORD32 ret = IV_SUCCESS; 3129 3130 ivd_ctl_set_config_ip_t *ps_ctl_ip = 3131 (ivd_ctl_set_config_ip_t *)pv_api_ip; 3132 ivd_ctl_set_config_op_t *ps_ctl_op = 3133 (ivd_ctl_set_config_op_t *)pv_api_op; 3134 3135 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 3136 3137 ps_dec->u4_skip_frm_mask = 0; 3138 3139 ps_ctl_op->u4_error_code = 0; 3140 3141 ps_dec->i4_app_skip_mode = ps_ctl_ip->e_frm_skip_mode; 3142 3143 /*Is it really supported test it when you so the corner testing using test app*/ 3144 3145 if(ps_ctl_ip->e_frm_skip_mode != IVD_SKIP_NONE) 3146 { 3147 3148 if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_P) 3149 ps_dec->u4_skip_frm_mask |= 1 << P_SLC_BIT; 3150 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_B) 3151 ps_dec->u4_skip_frm_mask |= 1 << B_SLC_BIT; 3152 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_PB) 3153 { 3154 ps_dec->u4_skip_frm_mask |= 1 << B_SLC_BIT; 3155 ps_dec->u4_skip_frm_mask |= 1 << P_SLC_BIT; 3156 } 3157 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_I) 3158 ps_dec->u4_skip_frm_mask |= 1 << I_SLC_BIT; 3159 else 3160 { 3161 //dynamic parameter not supported 3162 //Put an appropriate error code to return the error.. 3163 //when you do the error code tests and after that remove this comment 3164 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM); 3165 ret = IV_FAIL; 3166 } 3167 } 3168 3169 if(ps_ctl_ip->u4_disp_wd >= ps_dec->u2_pic_wd) 3170 { 3171 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd; 3172 } 3173 else if(0 == ps_dec->i4_header_decoded) 3174 { 3175 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd; 3176 } 3177 else if(ps_ctl_ip->u4_disp_wd == 0) 3178 { 3179 ps_dec->u4_app_disp_width = 0; 3180 } 3181 else 3182 { 3183 /* 3184 * Set the display width to zero. This will ensure that the wrong value we had stored (0xFFFFFFFF) 3185 * does not propogate. 3186 */ 3187 ps_dec->u4_app_disp_width = 0; 3188 ps_ctl_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 3189 ps_ctl_op->u4_error_code |= ERROR_DISP_WIDTH_INVALID; 3190 ret = IV_FAIL; 3191 } 3192 3193 if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_FRAME) 3194 ps_dec->i4_decode_header = 0; 3195 else if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_HEADER) 3196 ps_dec->i4_decode_header = 1; 3197 else 3198 { 3199 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM); 3200 ps_dec->i4_decode_header = 1; 3201 ret = IV_FAIL; 3202 } 3203 ps_dec->e_frm_out_mode = IVD_DISPLAY_FRAME_OUT; 3204 3205 if((ps_ctl_ip->e_frm_out_mode != IVD_DECODE_FRAME_OUT) && 3206 (ps_ctl_ip->e_frm_out_mode != IVD_DISPLAY_FRAME_OUT)) 3207 { 3208 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM); 3209 ret = IV_FAIL; 3210 } 3211 ps_dec->e_frm_out_mode = ps_ctl_ip->e_frm_out_mode; 3212 return ret; 3213 3214} 3215 3216/*****************************************************************************/ 3217/* */ 3218/* Function Name : ih264d_set_default_params */ 3219/* */ 3220/* Description : */ 3221/* */ 3222/* Inputs :iv_obj_t decoder handle */ 3223/* :pv_api_ip pointer to input structure */ 3224/* :pv_api_op pointer to output structure */ 3225/* Outputs : */ 3226/* Returns : void */ 3227/* */ 3228/* Issues : none */ 3229/* */ 3230/* Revision History: */ 3231/* */ 3232/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3233/* 08 08 2011 100421 Copied from set_params */ 3234/* */ 3235/*****************************************************************************/ 3236WORD32 ih264d_set_default_params(iv_obj_t *dec_hdl, 3237 void *pv_api_ip, 3238 void *pv_api_op) 3239{ 3240 3241 dec_struct_t * ps_dec; 3242 WORD32 ret = IV_SUCCESS; 3243 3244 ivd_ctl_set_config_op_t *ps_ctl_op = 3245 (ivd_ctl_set_config_op_t *)pv_api_op; 3246 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 3247 UNUSED(pv_api_ip); 3248 3249 3250 { 3251 ps_dec->u4_app_disp_width = 0; 3252 ps_dec->u4_skip_frm_mask = 0; 3253 ps_dec->i4_decode_header = 1; 3254 3255 ps_ctl_op->u4_error_code = 0; 3256 } 3257 3258 3259 return ret; 3260} 3261/*****************************************************************************/ 3262/* */ 3263/* Function Name : ih264d_reset */ 3264/* */ 3265/* Description : */ 3266/* */ 3267/* Inputs :iv_obj_t decoder handle */ 3268/* :pv_api_ip pointer to input structure */ 3269/* :pv_api_op pointer to output structure */ 3270/* Globals : <Does it use any global variables?> */ 3271/* Outputs : */ 3272/* Returns : void */ 3273/* */ 3274/* Issues : none */ 3275/* */ 3276/* Revision History: */ 3277/* */ 3278/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3279/* 22 10 2008 100356 Draft */ 3280/* */ 3281/*****************************************************************************/ 3282WORD32 ih264d_delete(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3283{ 3284 dec_struct_t *ps_dec; 3285 ih264d_delete_ip_t *ps_ip = (ih264d_delete_ip_t *)pv_api_ip; 3286 ih264d_delete_op_t *ps_op = (ih264d_delete_op_t *)pv_api_op; 3287 3288 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 3289 UNUSED(ps_ip); 3290 ps_op->s_ivd_delete_op_t.u4_error_code = 0; 3291 ih264d_free_dynamic_bufs(ps_dec); 3292 ih264d_free_static_bufs(dec_hdl); 3293 return IV_SUCCESS; 3294} 3295/*****************************************************************************/ 3296/* */ 3297/* Function Name : ih264d_reset */ 3298/* */ 3299/* Description : */ 3300/* */ 3301/* Inputs :iv_obj_t decoder handle */ 3302/* :pv_api_ip pointer to input structure */ 3303/* :pv_api_op pointer to output structure */ 3304/* Globals : <Does it use any global variables?> */ 3305/* Outputs : */ 3306/* Returns : void */ 3307/* */ 3308/* Issues : none */ 3309/* */ 3310/* Revision History: */ 3311/* */ 3312/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3313/* 22 10 2008 100356 Draft */ 3314/* */ 3315/*****************************************************************************/ 3316WORD32 ih264d_reset(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3317{ 3318 dec_struct_t * ps_dec; 3319 ivd_ctl_reset_op_t *ps_ctl_op = (ivd_ctl_reset_op_t *)pv_api_op; 3320 UNUSED(pv_api_ip); 3321 ps_ctl_op->u4_error_code = 0; 3322 3323 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 3324 3325 if(ps_dec != NULL) 3326 { 3327 ih264d_init_decoder(ps_dec); 3328 } 3329 else 3330 { 3331 H264_DEC_DEBUG_PRINT( 3332 "\nReset called without Initializing the decoder\n"); 3333 ps_ctl_op->u4_error_code = ERROR_INIT_NOT_DONE; 3334 } 3335 3336 return IV_SUCCESS; 3337} 3338 3339/*****************************************************************************/ 3340/* */ 3341/* Function Name : ih264d_ctl */ 3342/* */ 3343/* Description : */ 3344/* */ 3345/* Inputs :iv_obj_t decoder handle */ 3346/* :pv_api_ip pointer to input structure */ 3347/* :pv_api_op pointer to output structure */ 3348/* Outputs : */ 3349/* Returns : void */ 3350/* */ 3351/* Issues : none */ 3352/* */ 3353/* Revision History: */ 3354/* */ 3355/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3356/* 22 10 2008 100356 Draft */ 3357/* */ 3358/*****************************************************************************/ 3359WORD32 ih264d_ctl(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3360{ 3361 ivd_ctl_set_config_ip_t *ps_ctl_ip; 3362 ivd_ctl_set_config_op_t *ps_ctl_op; 3363 WORD32 ret = IV_SUCCESS; 3364 UWORD32 subcommand; 3365 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 3366 3367 if(ps_dec->init_done != 1) 3368 { 3369 //Return proper Error Code 3370 return IV_FAIL; 3371 } 3372 ps_ctl_ip = (ivd_ctl_set_config_ip_t*)pv_api_ip; 3373 ps_ctl_op = (ivd_ctl_set_config_op_t*)pv_api_op; 3374 ps_ctl_op->u4_error_code = 0; 3375 subcommand = ps_ctl_ip->e_sub_cmd; 3376 3377 switch(subcommand) 3378 { 3379 case IVD_CMD_CTL_GETPARAMS: 3380 ret = ih264d_get_status(dec_hdl, (void *)pv_api_ip, 3381 (void *)pv_api_op); 3382 break; 3383 case IVD_CMD_CTL_SETPARAMS: 3384 ret = ih264d_set_params(dec_hdl, (void *)pv_api_ip, 3385 (void *)pv_api_op); 3386 break; 3387 case IVD_CMD_CTL_RESET: 3388 ret = ih264d_reset(dec_hdl, (void *)pv_api_ip, (void *)pv_api_op); 3389 break; 3390 case IVD_CMD_CTL_SETDEFAULT: 3391 ret = ih264d_set_default_params(dec_hdl, (void *)pv_api_ip, 3392 (void *)pv_api_op); 3393 break; 3394 case IVD_CMD_CTL_FLUSH: 3395 ret = ih264d_set_flush_mode(dec_hdl, (void *)pv_api_ip, 3396 (void *)pv_api_op); 3397 break; 3398 case IVD_CMD_CTL_GETBUFINFO: 3399 ret = ih264d_get_buf_info(dec_hdl, (void *)pv_api_ip, 3400 (void *)pv_api_op); 3401 break; 3402 case IVD_CMD_CTL_GETVERSION: 3403 ret = ih264d_get_version(dec_hdl, (void *)pv_api_ip, 3404 (void *)pv_api_op); 3405 break; 3406 case IH264D_CMD_CTL_DEGRADE: 3407 ret = ih264d_set_degrade(dec_hdl, (void *)pv_api_ip, 3408 (void *)pv_api_op); 3409 break; 3410 3411 case IH264D_CMD_CTL_SET_NUM_CORES: 3412 ret = ih264d_set_num_cores(dec_hdl, (void *)pv_api_ip, 3413 (void *)pv_api_op); 3414 break; 3415 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS: 3416 ret = ih264d_get_frame_dimensions(dec_hdl, (void *)pv_api_ip, 3417 (void *)pv_api_op); 3418 break; 3419 case IH264D_CMD_CTL_GET_VUI_PARAMS: 3420 ret = ih264d_get_vui_params(dec_hdl, (void *)pv_api_ip, 3421 (void *)pv_api_op); 3422 break; 3423 3424 case IH264D_CMD_CTL_SET_PROCESSOR: 3425 ret = ih264d_set_processor(dec_hdl, (void *)pv_api_ip, 3426 (void *)pv_api_op); 3427 break; 3428 default: 3429 H264_DEC_DEBUG_PRINT("\ndo nothing\n") 3430 ; 3431 break; 3432 } 3433 3434 return ret; 3435} 3436/*****************************************************************************/ 3437/* */ 3438/* Function Name : ih264d_rel_display_frame */ 3439/* */ 3440/* Description : */ 3441/* */ 3442/* Inputs :iv_obj_t decoder handle */ 3443/* :pv_api_ip pointer to input structure */ 3444/* :pv_api_op pointer to output structure */ 3445/* Outputs : */ 3446/* Returns : void */ 3447/* */ 3448/* Issues : none */ 3449/* */ 3450/* Revision History: */ 3451/* */ 3452/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3453/* 22 10 2008 100356 Draft */ 3454/* */ 3455/*****************************************************************************/ 3456WORD32 ih264d_rel_display_frame(iv_obj_t *dec_hdl, 3457 void *pv_api_ip, 3458 void *pv_api_op) 3459{ 3460 3461 ivd_rel_display_frame_ip_t *ps_rel_ip; 3462 ivd_rel_display_frame_op_t *ps_rel_op; 3463 UWORD32 buf_released = 0; 3464 3465 UWORD32 u4_ts = -1; 3466 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 3467 3468 ps_rel_ip = (ivd_rel_display_frame_ip_t *)pv_api_ip; 3469 ps_rel_op = (ivd_rel_display_frame_op_t *)pv_api_op; 3470 ps_rel_op->u4_error_code = 0; 3471 u4_ts = ps_rel_ip->u4_disp_buf_id; 3472 3473 if(0 == ps_dec->u4_share_disp_buf) 3474 { 3475 ps_dec->u4_disp_buf_mapping[u4_ts] = 0; 3476 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 0; 3477 return IV_SUCCESS; 3478 } 3479 3480 if(ps_dec->pv_pic_buf_mgr != NULL) 3481 { 3482 if(1 == ps_dec->u4_disp_buf_mapping[u4_ts]) 3483 { 3484 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 3485 ps_rel_ip->u4_disp_buf_id, 3486 BUF_MGR_IO); 3487 ps_dec->u4_disp_buf_mapping[u4_ts] = 0; 3488 buf_released = 1; 3489 } 3490 } 3491 3492 if((1 == ps_dec->u4_share_disp_buf) && (0 == buf_released)) 3493 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 1; 3494 3495 return IV_SUCCESS; 3496} 3497 3498/** 3499 ******************************************************************************* 3500 * 3501 * @brief 3502 * Sets degrade params 3503 * 3504 * @par Description: 3505 * Sets degrade params. 3506 * Refer to ih264d_ctl_degrade_ip_t definition for details 3507 * 3508 * @param[in] ps_codec_obj 3509 * Pointer to codec object at API level 3510 * 3511 * @param[in] pv_api_ip 3512 * Pointer to input argument structure 3513 * 3514 * @param[out] pv_api_op 3515 * Pointer to output argument structure 3516 * 3517 * @returns Status 3518 * 3519 * @remarks 3520 * 3521 * 3522 ******************************************************************************* 3523 */ 3524 3525WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj, 3526 void *pv_api_ip, 3527 void *pv_api_op) 3528{ 3529 ih264d_ctl_degrade_ip_t *ps_ip; 3530 ih264d_ctl_degrade_op_t *ps_op; 3531 dec_struct_t *ps_codec = (dec_struct_t *)ps_codec_obj->pv_codec_handle; 3532 3533 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip; 3534 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op; 3535 3536 ps_codec->i4_degrade_type = ps_ip->i4_degrade_type; 3537 ps_codec->i4_nondegrade_interval = ps_ip->i4_nondegrade_interval; 3538 ps_codec->i4_degrade_pics = ps_ip->i4_degrade_pics; 3539 3540 ps_op->u4_error_code = 0; 3541 ps_codec->i4_degrade_pic_cnt = 0; 3542 3543 return IV_SUCCESS; 3544} 3545 3546WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl, 3547 void *pv_api_ip, 3548 void *pv_api_op) 3549{ 3550 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip; 3551 ih264d_ctl_get_frame_dimensions_op_t *ps_op; 3552 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 3553 UWORD32 disp_wd, disp_ht, buffer_wd, buffer_ht, x_offset, y_offset; 3554 3555 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip; 3556 3557 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op; 3558 UNUSED(ps_ip); 3559 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 3560 { 3561 disp_wd = ps_dec->u2_disp_width; 3562 disp_ht = ps_dec->u2_disp_height; 3563 3564 if(0 == ps_dec->u4_share_disp_buf) 3565 { 3566 buffer_wd = disp_wd; 3567 buffer_ht = disp_ht; 3568 } 3569 else 3570 { 3571 buffer_wd = ps_dec->u2_frm_wd_y; 3572 buffer_ht = ps_dec->u2_frm_ht_y; 3573 } 3574 } 3575 else 3576 { 3577 disp_wd = 0; 3578 disp_ht = 0; 3579 3580 if(0 == ps_dec->u4_share_disp_buf) 3581 { 3582 buffer_wd = disp_wd; 3583 buffer_ht = disp_ht; 3584 } 3585 else 3586 { 3587 buffer_wd = ALIGN16(disp_wd) + (PAD_LEN_Y_H << 1); 3588 buffer_ht = ALIGN16(disp_ht) + (PAD_LEN_Y_V << 2); 3589 } 3590 } 3591 if(ps_dec->u4_app_disp_width > buffer_wd) 3592 buffer_wd = ps_dec->u4_app_disp_width; 3593 3594 if(0 == ps_dec->u4_share_disp_buf) 3595 { 3596 x_offset = 0; 3597 y_offset = 0; 3598 } 3599 else 3600 { 3601 y_offset = (PAD_LEN_Y_V << 1); 3602 x_offset = PAD_LEN_Y_H; 3603 3604 if((NULL != ps_dec->ps_sps) && (1 == (ps_dec->ps_sps->u1_is_valid)) 3605 && (0 != ps_dec->u2_crop_offset_y)) 3606 { 3607 y_offset += ps_dec->u2_crop_offset_y / ps_dec->u2_frm_wd_y; 3608 x_offset += ps_dec->u2_crop_offset_y % ps_dec->u2_frm_wd_y; 3609 } 3610 } 3611 3612 ps_op->u4_disp_wd[0] = disp_wd; 3613 ps_op->u4_disp_ht[0] = disp_ht; 3614 ps_op->u4_buffer_wd[0] = buffer_wd; 3615 ps_op->u4_buffer_ht[0] = buffer_ht; 3616 ps_op->u4_x_offset[0] = x_offset; 3617 ps_op->u4_y_offset[0] = y_offset; 3618 3619 ps_op->u4_disp_wd[1] = ps_op->u4_disp_wd[2] = ((ps_op->u4_disp_wd[0] + 1) 3620 >> 1); 3621 ps_op->u4_disp_ht[1] = ps_op->u4_disp_ht[2] = ((ps_op->u4_disp_ht[0] + 1) 3622 >> 1); 3623 ps_op->u4_buffer_wd[1] = ps_op->u4_buffer_wd[2] = (ps_op->u4_buffer_wd[0] 3624 >> 1); 3625 ps_op->u4_buffer_ht[1] = ps_op->u4_buffer_ht[2] = (ps_op->u4_buffer_ht[0] 3626 >> 1); 3627 ps_op->u4_x_offset[1] = ps_op->u4_x_offset[2] = 3628 (ps_op->u4_x_offset[0] >> 1); 3629 ps_op->u4_y_offset[1] = ps_op->u4_y_offset[2] = 3630 (ps_op->u4_y_offset[0] >> 1); 3631 3632 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 3633 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 3634 { 3635 ps_op->u4_disp_wd[2] = 0; 3636 ps_op->u4_disp_ht[2] = 0; 3637 ps_op->u4_buffer_wd[2] = 0; 3638 ps_op->u4_buffer_ht[2] = 0; 3639 ps_op->u4_x_offset[2] = 0; 3640 ps_op->u4_y_offset[2] = 0; 3641 3642 ps_op->u4_disp_wd[1] <<= 1; 3643 ps_op->u4_buffer_wd[1] <<= 1; 3644 ps_op->u4_x_offset[1] <<= 1; 3645 } 3646 3647 return IV_SUCCESS; 3648 3649} 3650 3651WORD32 ih264d_get_vui_params(iv_obj_t *dec_hdl, 3652 void *pv_api_ip, 3653 void *pv_api_op) 3654{ 3655 ih264d_ctl_get_vui_params_ip_t *ps_ip; 3656 ih264d_ctl_get_vui_params_op_t *ps_op; 3657 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 3658 dec_seq_params_t *ps_sps; 3659 vui_t *ps_vui; 3660 WORD32 i; 3661 UWORD32 u4_size; 3662 3663 ps_ip = (ih264d_ctl_get_vui_params_ip_t *)pv_api_ip; 3664 ps_op = (ih264d_ctl_get_vui_params_op_t *)pv_api_op; 3665 UNUSED(ps_ip); 3666 3667 u4_size = ps_op->u4_size; 3668 memset(ps_op, 0, sizeof(ih264d_ctl_get_vui_params_op_t)); 3669 ps_op->u4_size = u4_size; 3670 3671 if(NULL == ps_dec->ps_cur_sps) 3672 { 3673 ps_op->u4_error_code = ERROR_VUI_PARAMS_NOT_FOUND; 3674 return IV_FAIL; 3675 } 3676 3677 ps_sps = ps_dec->ps_cur_sps; 3678 if((0 == ps_sps->u1_is_valid) 3679 || (0 == ps_sps->u1_vui_parameters_present_flag)) 3680 { 3681 ps_op->u4_error_code = ERROR_VUI_PARAMS_NOT_FOUND; 3682 return IV_FAIL; 3683 } 3684 3685 ps_vui = &ps_sps->s_vui; 3686 3687 ps_op->u1_aspect_ratio_idc = ps_vui->u1_aspect_ratio_idc; 3688 ps_op->u2_sar_width = ps_vui->u2_sar_width; 3689 ps_op->u2_sar_height = ps_vui->u2_sar_height; 3690 ps_op->u1_overscan_appropriate_flag = ps_vui->u1_overscan_appropriate_flag; 3691 ps_op->u1_video_format = ps_vui->u1_video_format; 3692 ps_op->u1_video_full_range_flag = ps_vui->u1_video_full_range_flag; 3693 ps_op->u1_colour_primaries = ps_vui->u1_colour_primaries; 3694 ps_op->u1_tfr_chars = ps_vui->u1_tfr_chars; 3695 ps_op->u1_matrix_coeffs = ps_vui->u1_matrix_coeffs; 3696 ps_op->u1_cr_top_field = ps_vui->u1_cr_top_field; 3697 ps_op->u1_cr_bottom_field = ps_vui->u1_cr_bottom_field; 3698 ps_op->u4_num_units_in_tick = ps_vui->u4_num_units_in_tick; 3699 ps_op->u4_time_scale = ps_vui->u4_time_scale; 3700 ps_op->u1_fixed_frame_rate_flag = ps_vui->u1_fixed_frame_rate_flag; 3701 ps_op->u1_nal_hrd_params_present = ps_vui->u1_nal_hrd_params_present; 3702 ps_op->u1_vcl_hrd_params_present = ps_vui->u1_vcl_hrd_params_present; 3703 ps_op->u1_low_delay_hrd_flag = ps_vui->u1_low_delay_hrd_flag; 3704 ps_op->u1_pic_struct_present_flag = ps_vui->u1_pic_struct_present_flag; 3705 ps_op->u1_bitstream_restriction_flag = ps_vui->u1_bitstream_restriction_flag; 3706 ps_op->u1_mv_over_pic_boundaries_flag = ps_vui->u1_mv_over_pic_boundaries_flag; 3707 ps_op->u4_max_bytes_per_pic_denom = ps_vui->u4_max_bytes_per_pic_denom; 3708 ps_op->u4_max_bits_per_mb_denom = ps_vui->u4_max_bits_per_mb_denom; 3709 ps_op->u4_log2_max_mv_length_horz = ps_vui->u4_log2_max_mv_length_horz; 3710 ps_op->u4_log2_max_mv_length_vert = ps_vui->u4_log2_max_mv_length_vert; 3711 ps_op->u4_num_reorder_frames = ps_vui->u4_num_reorder_frames; 3712 ps_op->u4_max_dec_frame_buffering = ps_vui->u4_max_dec_frame_buffering; 3713 3714 return IV_SUCCESS; 3715} 3716 3717WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3718{ 3719 ih264d_ctl_set_num_cores_ip_t *ps_ip; 3720 ih264d_ctl_set_num_cores_op_t *ps_op; 3721 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 3722 3723 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip; 3724 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op; 3725 ps_op->u4_error_code = 0; 3726 ps_dec->u4_num_cores = ps_ip->u4_num_cores; 3727 if(ps_dec->u4_num_cores == 1) 3728 { 3729 ps_dec->u1_separate_parse = 0; 3730 } 3731 else 3732 { 3733 ps_dec->u1_separate_parse = 1; 3734 } 3735 3736 /*using only upto three threads currently*/ 3737 if(ps_dec->u4_num_cores > 3) 3738 ps_dec->u4_num_cores = 3; 3739 3740 return IV_SUCCESS; 3741} 3742 3743void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec, 3744 ivd_video_decode_op_t *ps_dec_op) 3745{ 3746 if((ps_dec_op->u4_error_code & 0xff) 3747 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED) 3748 { 3749 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width; 3750 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height; 3751 } 3752 ps_dec_op->e_pic_type = ps_dec->i4_frametype; 3753 3754 ps_dec_op->u4_new_seq = 0; 3755 ps_dec_op->u4_output_present = ps_dec->u4_output_present; 3756 ps_dec_op->u4_progressive_frame_flag = 3757 ps_dec->s_disp_op.u4_progressive_frame_flag; 3758 3759 ps_dec_op->u4_is_ref_flag = 1; 3760 if(ps_dec_op->u4_frame_decoded_flag) 3761 { 3762 if(ps_dec->ps_cur_slice->u1_nal_ref_idc == 0) 3763 ps_dec_op->u4_is_ref_flag = 0; 3764 } 3765 3766 ps_dec_op->e_output_format = ps_dec->s_disp_op.e_output_format; 3767 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf; 3768 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type; 3769 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts; 3770 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id; 3771} 3772 3773/*****************************************************************************/ 3774/* */ 3775/* Function Name : ih264d_api_function */ 3776/* */ 3777/* Description : */ 3778/* */ 3779/* Inputs :iv_obj_t decoder handle */ 3780/* :pv_api_ip pointer to input structure */ 3781/* :pv_api_op pointer to output structure */ 3782/* Outputs : */ 3783/* Returns : void */ 3784/* */ 3785/* Issues : none */ 3786/* */ 3787/* Revision History: */ 3788/* */ 3789/* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3790/* 22 10 2008 100356 Draft */ 3791/* */ 3792/*****************************************************************************/ 3793IV_API_CALL_STATUS_T ih264d_api_function(iv_obj_t *dec_hdl, 3794 void *pv_api_ip, 3795 void *pv_api_op) 3796{ 3797 UWORD32 command; 3798 UWORD32 *pu2_ptr_cmd; 3799 UWORD32 u4_api_ret; 3800 IV_API_CALL_STATUS_T e_status; 3801 e_status = api_check_struct_sanity(dec_hdl, pv_api_ip, pv_api_op); 3802 3803 if(e_status != IV_SUCCESS) 3804 { 3805 UWORD32 *ptr_err; 3806 3807 ptr_err = (UWORD32 *)pv_api_op; 3808 UNUSED(ptr_err); 3809 H264_DEC_DEBUG_PRINT("error code = %d\n", *(ptr_err + 1)); 3810 return IV_FAIL; 3811 } 3812 3813 pu2_ptr_cmd = (UWORD32 *)pv_api_ip; 3814 pu2_ptr_cmd++; 3815 3816 command = *pu2_ptr_cmd; 3817// H264_DEC_DEBUG_PRINT("inside lib = %d\n",command); 3818 switch(command) 3819 { 3820 3821 case IVD_CMD_CREATE: 3822 u4_api_ret = ih264d_create(dec_hdl, (void *)pv_api_ip, 3823 (void *)pv_api_op); 3824 break; 3825 case IVD_CMD_DELETE: 3826 u4_api_ret = ih264d_delete(dec_hdl, (void *)pv_api_ip, 3827 (void *)pv_api_op); 3828 break; 3829 3830 case IVD_CMD_VIDEO_DECODE: 3831 u4_api_ret = ih264d_video_decode(dec_hdl, (void *)pv_api_ip, 3832 (void *)pv_api_op); 3833 break; 3834 3835 case IVD_CMD_GET_DISPLAY_FRAME: 3836 u4_api_ret = ih264d_get_display_frame(dec_hdl, (void *)pv_api_ip, 3837 (void *)pv_api_op); 3838 3839 break; 3840 3841 case IVD_CMD_SET_DISPLAY_FRAME: 3842 u4_api_ret = ih264d_set_display_frame(dec_hdl, (void *)pv_api_ip, 3843 (void *)pv_api_op); 3844 3845 break; 3846 3847 case IVD_CMD_REL_DISPLAY_FRAME: 3848 u4_api_ret = ih264d_rel_display_frame(dec_hdl, (void *)pv_api_ip, 3849 (void *)pv_api_op); 3850 break; 3851 3852 case IVD_CMD_VIDEO_CTL: 3853 u4_api_ret = ih264d_ctl(dec_hdl, (void *)pv_api_ip, 3854 (void *)pv_api_op); 3855 break; 3856 default: 3857 u4_api_ret = IV_FAIL; 3858 break; 3859 } 3860 3861 return u4_api_ret; 3862} 3863