1b08e2e23eec181e9951df33cd704ac294c5407b6Vignesh Venkatasubramanian#!/usr/bin/env perl 2ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang## 3ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang## Copyright (c) 2013 The WebM project authors. All Rights Reserved. 4ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang## 5ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang## Use of this source code is governed by a BSD-style license 6ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang## that can be found in the LICENSE file in the root of the source 7ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang## tree. An additional intellectual property rights grant can be found 8ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang## in the file PATENTS. All contributing project authors may 9ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang## be found in the AUTHORS file in the root of the source tree. 10ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang## 11ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang 12ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuangpackage thumb; 13ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang 14ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuangsub FixThumbInstructions($$) 15ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang{ 16ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang my $short_branches = $_[1]; 17ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang my $branch_shift_offset = $short_branches ? 1 : 0; 18ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang 19ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # Write additions with shifts, such as "add r10, r11, lsl #8", 20ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # in three operand form, "add r10, r10, r11, lsl #8". 21ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang s/(add\s+)(r\d+),\s*(r\d+),\s*(lsl #\d+)/$1$2, $2, $3, $4/g; 22ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang 23ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # Convert additions with a non-constant shift into a sequence 24ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # with left shift, addition and a right shift (to restore the 25ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # register to the original value). Currently the right shift 26ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # isn't necessary in the code base since the values in these 27b08e2e23eec181e9951df33cd704ac294c5407b6Vignesh Venkatasubramanian # registers aren't used, but doing the shift for consistency. 28ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # This converts instructions such as "add r12, r12, r5, lsl r4" 29ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # into the sequence "lsl r5, r4", "add r12, r12, r5", "lsr r5, r4". 30ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang s/^(\s*)(add)(\s+)(r\d+),\s*(r\d+),\s*(r\d+),\s*lsl (r\d+)/$1lsl$3$6, $7\n$1$2$3$4, $5, $6\n$1lsr$3$6, $7/g; 31ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang 32ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # Convert loads with right shifts in the indexing into a 33ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # sequence of an add, load and sub. This converts 34ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # "ldrb r4, [r9, lr, asr #1]" into "add r9, r9, lr, asr #1", 35ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # "ldrb r9, [r9]", "sub r9, r9, lr, asr #1". 36ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang s/^(\s*)(ldrb)(\s+)(r\d+),\s*\[(\w+),\s*(\w+),\s*(asr #\d+)\]/$1add $3$5, $5, $6, $7\n$1$2$3$4, [$5]\n$1sub $3$5, $5, $6, $7/g; 37ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang 38ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # Convert register indexing with writeback into a separate add 39ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # instruction. This converts "ldrb r12, [r1, r2]!" into 40ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # "ldrb r12, [r1, r2]", "add r1, r1, r2". 41ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang s/^(\s*)(ldrb)(\s+)(r\d+),\s*\[(\w+),\s*(\w+)\]!/$1$2$3$4, [$5, $6]\n$1add $3$5, $6/g; 42ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang 43ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # Convert negative register indexing into separate sub/add instructions. 44ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # This converts "ldrne r4, [src, -pstep, lsl #1]" into 45ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # "subne src, src, pstep, lsl #1", "ldrne r4, [src]", 46ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # "addne src, src, pstep, lsl #1". In a couple of cases where 47ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # this is used, it's used for two subsequent load instructions, 48ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # where a hand-written version of it could merge two subsequent 49ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # add and sub instructions. 505ae7ac49f08a179e4f054d99fcfc9dce78d26e58hkuang s/^(\s*)((ldr|str|pld)(ne)?)(\s+)(r\d+,\s*)?\[(\w+), -([^\]]+)\]/$1sub$4$5$7, $7, $8\n$1$2$5$6\[$7\]\n$1add$4$5$7, $7, $8/g; 51ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang 52ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # Convert register post indexing to a separate add instruction. 53ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # This converts "ldrneb r9, [r0], r2" into "ldrneb r9, [r0]", 54a72801d7d92ababb50eecf27a36bd222d031d2feVignesh Venkatasubramanian # "addne r0, r0, r2". 55ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang s/^(\s*)((ldr|str)(ne)?[bhd]?)(\s+)(\w+),(\s*\w+,)?\s*\[(\w+)\],\s*(\w+)/$1$2$5$6,$7 [$8]\n$1add$4$5$8, $8, $9/g; 56ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang 57ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # Convert a conditional addition to the pc register into a series of 58ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # instructions. This converts "addlt pc, pc, r3, lsl #2" into 59ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # "itttt lt", "movlt.n r12, pc", "addlt.w r12, #12", 60ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # "addlt.w r12, r12, r3, lsl #2", "movlt.n pc, r12". 61ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # This assumes that r12 is free at this point. 62ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang s/^(\s*)addlt(\s+)pc,\s*pc,\s*(\w+),\s*lsl\s*#(\d+)/$1itttt$2lt\n$1movlt.n$2r12, pc\n$1addlt.w$2r12, #12\n$1addlt.w$2r12, r12, $3, lsl #($4-$branch_shift_offset)\n$1movlt.n$2pc, r12/g; 63ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang 64ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # Convert "mov pc, lr" into "bx lr", since the former only works 65ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # for switching from arm to thumb (and only in armv7), but not 66ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang # from thumb to arm. 67ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang s/mov(\s*)pc\s*,\s*lr/bx$1lr/g; 68ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang} 69ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang 70ba164dffc5a6795bce97fae02b51ccf3330e15e4hkuang1; 71