ScheduleDAG.h revision 6f0d024a534af18d9e60b3ea757376cd8a3a980e
1//===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the ScheduleDAG class, which is used as the common 11// base class for SelectionDAG-based instruction scheduler. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_CODEGEN_SCHEDULEDAG_H 16#define LLVM_CODEGEN_SCHEDULEDAG_H 17 18#include "llvm/CodeGen/SelectionDAG.h" 19#include "llvm/ADT/DenseMap.h" 20#include "llvm/ADT/GraphTraits.h" 21#include "llvm/ADT/SmallSet.h" 22 23namespace llvm { 24 struct InstrStage; 25 struct SUnit; 26 class MachineConstantPool; 27 class MachineFunction; 28 class MachineModuleInfo; 29 class MachineRegisterInfo; 30 class MachineInstr; 31 class TargetRegisterInfo; 32 class SelectionDAG; 33 class SelectionDAGISel; 34 class TargetInstrInfo; 35 class TargetInstrDesc; 36 class TargetMachine; 37 class TargetRegisterClass; 38 39 /// HazardRecognizer - This determines whether or not an instruction can be 40 /// issued this cycle, and whether or not a noop needs to be inserted to handle 41 /// the hazard. 42 class HazardRecognizer { 43 public: 44 virtual ~HazardRecognizer(); 45 46 enum HazardType { 47 NoHazard, // This instruction can be emitted at this cycle. 48 Hazard, // This instruction can't be emitted at this cycle. 49 NoopHazard // This instruction can't be emitted, and needs noops. 50 }; 51 52 /// getHazardType - Return the hazard type of emitting this node. There are 53 /// three possible results. Either: 54 /// * NoHazard: it is legal to issue this instruction on this cycle. 55 /// * Hazard: issuing this instruction would stall the machine. If some 56 /// other instruction is available, issue it first. 57 /// * NoopHazard: issuing this instruction would break the program. If 58 /// some other instruction can be issued, do so, otherwise issue a noop. 59 virtual HazardType getHazardType(SDNode *Node) { 60 return NoHazard; 61 } 62 63 /// EmitInstruction - This callback is invoked when an instruction is 64 /// emitted, to advance the hazard state. 65 virtual void EmitInstruction(SDNode *Node) { 66 } 67 68 /// AdvanceCycle - This callback is invoked when no instructions can be 69 /// issued on this cycle without a hazard. This should increment the 70 /// internal state of the hazard recognizer so that previously "Hazard" 71 /// instructions will now not be hazards. 72 virtual void AdvanceCycle() { 73 } 74 75 /// EmitNoop - This callback is invoked when a noop was added to the 76 /// instruction stream. 77 virtual void EmitNoop() { 78 } 79 }; 80 81 /// SDep - Scheduling dependency. It keeps track of dependent nodes, 82 /// cost of the depdenency, etc. 83 struct SDep { 84 SUnit *Dep; // Dependent - either a predecessor or a successor. 85 unsigned Reg; // If non-zero, this dep is a phy register dependency. 86 int Cost; // Cost of the dependency. 87 bool isCtrl : 1; // True iff it's a control dependency. 88 bool isSpecial : 1; // True iff it's a special ctrl dep added during sched. 89 SDep(SUnit *d, unsigned r, int t, bool c, bool s) 90 : Dep(d), Reg(r), Cost(t), isCtrl(c), isSpecial(s) {} 91 }; 92 93 /// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or 94 /// a group of nodes flagged together. 95 struct SUnit { 96 SDNode *Node; // Representative node. 97 SmallVector<SDNode*,4> FlaggedNodes;// All nodes flagged to Node. 98 unsigned InstanceNo; // Instance#. One SDNode can be multiple 99 // SUnit due to cloning. 100 101 // Preds/Succs - The SUnits before/after us in the graph. The boolean value 102 // is true if the edge is a token chain edge, false if it is a value edge. 103 SmallVector<SDep, 4> Preds; // All sunit predecessors. 104 SmallVector<SDep, 4> Succs; // All sunit successors. 105 106 typedef SmallVector<SDep, 4>::iterator pred_iterator; 107 typedef SmallVector<SDep, 4>::iterator succ_iterator; 108 typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator; 109 typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator; 110 111 unsigned NodeNum; // Entry # of node in the node vector. 112 unsigned short Latency; // Node latency. 113 short NumPreds; // # of preds. 114 short NumSuccs; // # of sucss. 115 short NumPredsLeft; // # of preds not scheduled. 116 short NumSuccsLeft; // # of succs not scheduled. 117 bool isTwoAddress : 1; // Is a two-address instruction. 118 bool isCommutable : 1; // Is a commutable instruction. 119 bool hasPhysRegDefs : 1; // Has physreg defs that are being used. 120 bool isPending : 1; // True once pending. 121 bool isAvailable : 1; // True once available. 122 bool isScheduled : 1; // True once scheduled. 123 unsigned CycleBound; // Upper/lower cycle to be scheduled at. 124 unsigned Cycle; // Once scheduled, the cycle of the op. 125 unsigned Depth; // Node depth; 126 unsigned Height; // Node height; 127 const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null. 128 const TargetRegisterClass *CopySrcRC; 129 130 SUnit(SDNode *node, unsigned nodenum) 131 : Node(node), InstanceNo(0), NodeNum(nodenum), Latency(0), 132 NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0), 133 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false), 134 isPending(false), isAvailable(false), isScheduled(false), 135 CycleBound(0), Cycle(0), Depth(0), Height(0), 136 CopyDstRC(NULL), CopySrcRC(NULL) {} 137 138 /// addPred - This adds the specified node as a pred of the current node if 139 /// not already. This returns true if this is a new pred. 140 bool addPred(SUnit *N, bool isCtrl, bool isSpecial, 141 unsigned PhyReg = 0, int Cost = 1) { 142 for (unsigned i = 0, e = Preds.size(); i != e; ++i) 143 if (Preds[i].Dep == N && 144 Preds[i].isCtrl == isCtrl && Preds[i].isSpecial == isSpecial) 145 return false; 146 Preds.push_back(SDep(N, PhyReg, Cost, isCtrl, isSpecial)); 147 N->Succs.push_back(SDep(this, PhyReg, Cost, isCtrl, isSpecial)); 148 if (!isCtrl) { 149 ++NumPreds; 150 ++N->NumSuccs; 151 } 152 if (!N->isScheduled) 153 ++NumPredsLeft; 154 if (!isScheduled) 155 ++N->NumSuccsLeft; 156 return true; 157 } 158 159 bool removePred(SUnit *N, bool isCtrl, bool isSpecial) { 160 for (SmallVector<SDep, 4>::iterator I = Preds.begin(), E = Preds.end(); 161 I != E; ++I) 162 if (I->Dep == N && I->isCtrl == isCtrl && I->isSpecial == isSpecial) { 163 bool FoundSucc = false; 164 for (SmallVector<SDep, 4>::iterator II = N->Succs.begin(), 165 EE = N->Succs.end(); II != EE; ++II) 166 if (II->Dep == this && 167 II->isCtrl == isCtrl && II->isSpecial == isSpecial) { 168 FoundSucc = true; 169 N->Succs.erase(II); 170 break; 171 } 172 assert(FoundSucc && "Mismatching preds / succs lists!"); 173 Preds.erase(I); 174 if (!isCtrl) { 175 --NumPreds; 176 --N->NumSuccs; 177 } 178 if (!N->isScheduled) 179 --NumPredsLeft; 180 if (!isScheduled) 181 --N->NumSuccsLeft; 182 return true; 183 } 184 return false; 185 } 186 187 bool isPred(SUnit *N) { 188 for (unsigned i = 0, e = Preds.size(); i != e; ++i) 189 if (Preds[i].Dep == N) 190 return true; 191 return false; 192 } 193 194 bool isSucc(SUnit *N) { 195 for (unsigned i = 0, e = Succs.size(); i != e; ++i) 196 if (Succs[i].Dep == N) 197 return true; 198 return false; 199 } 200 201 void dump(const SelectionDAG *G) const; 202 void dumpAll(const SelectionDAG *G) const; 203 }; 204 205 //===--------------------------------------------------------------------===// 206 /// SchedulingPriorityQueue - This interface is used to plug different 207 /// priorities computation algorithms into the list scheduler. It implements 208 /// the interface of a standard priority queue, where nodes are inserted in 209 /// arbitrary order and returned in priority order. The computation of the 210 /// priority and the representation of the queue are totally up to the 211 /// implementation to decide. 212 /// 213 class SchedulingPriorityQueue { 214 public: 215 virtual ~SchedulingPriorityQueue() {} 216 217 virtual void initNodes(DenseMap<SDNode*, std::vector<SUnit*> > &SUMap, 218 std::vector<SUnit> &SUnits) = 0; 219 virtual void addNode(const SUnit *SU) = 0; 220 virtual void updateNode(const SUnit *SU) = 0; 221 virtual void releaseState() = 0; 222 223 virtual unsigned size() const = 0; 224 virtual bool empty() const = 0; 225 virtual void push(SUnit *U) = 0; 226 227 virtual void push_all(const std::vector<SUnit *> &Nodes) = 0; 228 virtual SUnit *pop() = 0; 229 230 virtual void remove(SUnit *SU) = 0; 231 232 /// ScheduledNode - As each node is scheduled, this method is invoked. This 233 /// allows the priority function to adjust the priority of node that have 234 /// already been emitted. 235 virtual void ScheduledNode(SUnit *Node) {} 236 237 virtual void UnscheduledNode(SUnit *Node) {} 238 }; 239 240 class ScheduleDAG { 241 public: 242 SelectionDAG &DAG; // DAG of the current basic block 243 MachineBasicBlock *BB; // Current basic block 244 const TargetMachine &TM; // Target processor 245 const TargetInstrInfo *TII; // Target instruction information 246 const TargetRegisterInfo *TRI; // Target processor register info 247 MachineFunction *MF; // Machine function 248 MachineRegisterInfo &RegInfo; // Virtual/real register map 249 MachineConstantPool *ConstPool; // Target constant pool 250 std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s 251 // represent noop instructions. 252 DenseMap<SDNode*, std::vector<SUnit*> > SUnitMap; 253 // SDNode to SUnit mapping (n -> n). 254 std::vector<SUnit> SUnits; // The scheduling units. 255 SmallSet<SDNode*, 16> CommuteSet; // Nodes the should be commuted. 256 257 ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb, 258 const TargetMachine &tm); 259 260 virtual ~ScheduleDAG() {} 261 262 /// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered 263 /// using 'dot'. 264 /// 265 void viewGraph(); 266 267 /// Run - perform scheduling. 268 /// 269 MachineBasicBlock *Run(); 270 271 /// isPassiveNode - Return true if the node is a non-scheduled leaf. 272 /// 273 static bool isPassiveNode(SDNode *Node) { 274 if (isa<ConstantSDNode>(Node)) return true; 275 if (isa<RegisterSDNode>(Node)) return true; 276 if (isa<GlobalAddressSDNode>(Node)) return true; 277 if (isa<BasicBlockSDNode>(Node)) return true; 278 if (isa<FrameIndexSDNode>(Node)) return true; 279 if (isa<ConstantPoolSDNode>(Node)) return true; 280 if (isa<JumpTableSDNode>(Node)) return true; 281 if (isa<ExternalSymbolSDNode>(Node)) return true; 282 if (isa<MemOperandSDNode>(Node)) return true; 283 return false; 284 } 285 286 /// NewSUnit - Creates a new SUnit and return a ptr to it. 287 /// 288 SUnit *NewSUnit(SDNode *N) { 289 SUnits.push_back(SUnit(N, SUnits.size())); 290 return &SUnits.back(); 291 } 292 293 /// Clone - Creates a clone of the specified SUnit. It does not copy the 294 /// predecessors / successors info nor the temporary scheduling states. 295 SUnit *Clone(SUnit *N); 296 297 /// BuildSchedUnits - Build SUnits from the selection dag that we are input. 298 /// This SUnit graph is similar to the SelectionDAG, but represents flagged 299 /// together nodes with a single SUnit. 300 void BuildSchedUnits(); 301 302 /// ComputeLatency - Compute node latency. 303 /// 304 void ComputeLatency(SUnit *SU); 305 306 /// CalculateDepths, CalculateHeights - Calculate node depth / height. 307 /// 308 void CalculateDepths(); 309 void CalculateHeights(); 310 311 /// CountResults - The results of target nodes have register or immediate 312 /// operands first, then an optional chain, and optional flag operands 313 /// (which do not go into the machine instrs.) 314 static unsigned CountResults(SDNode *Node); 315 316 /// CountOperands - The inputs to target nodes have any actual inputs first, 317 /// followed by optional memory operands chain operand, then flag operands. 318 /// Compute the number of actual operands that will go into the machine 319 /// instr. 320 static unsigned CountOperands(SDNode *Node); 321 322 /// CountMemOperands - Find the index of the last MemOperandSDNode 323 static unsigned CountMemOperands(SDNode *Node); 324 325 /// EmitNode - Generate machine code for an node and needed dependencies. 326 /// VRBaseMap contains, for each already emitted node, the first virtual 327 /// register number for the results of the node. 328 /// 329 void EmitNode(SDNode *Node, unsigned InstNo, 330 DenseMap<SDOperand, unsigned> &VRBaseMap); 331 332 /// EmitNoop - Emit a noop instruction. 333 /// 334 void EmitNoop(); 335 336 void EmitCrossRCCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap); 337 338 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 339 /// implicit physical register output. 340 void EmitCopyFromReg(SDNode *Node, unsigned ResNo, unsigned InstNo, 341 unsigned SrcReg, 342 DenseMap<SDOperand, unsigned> &VRBaseMap); 343 344 void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI, 345 const TargetInstrDesc &II, 346 DenseMap<SDOperand, unsigned> &VRBaseMap); 347 348 void EmitSchedule(); 349 350 void dumpSchedule() const; 351 352 /// Schedule - Order nodes according to selected style. 353 /// 354 virtual void Schedule() {} 355 356 private: 357 /// EmitSubregNode - Generate machine code for subreg nodes. 358 /// 359 void EmitSubregNode(SDNode *Node, 360 DenseMap<SDOperand, unsigned> &VRBaseMap); 361 362 void AddOperand(MachineInstr *MI, SDOperand Op, unsigned IIOpNum, 363 const TargetInstrDesc *II, 364 DenseMap<SDOperand, unsigned> &VRBaseMap); 365 366 void AddMemOperand(MachineInstr *MI, const MemOperand &MO); 367 }; 368 369 /// createBURRListDAGScheduler - This creates a bottom up register usage 370 /// reduction list scheduler. 371 ScheduleDAG* createBURRListDAGScheduler(SelectionDAGISel *IS, 372 SelectionDAG *DAG, 373 MachineBasicBlock *BB); 374 375 /// createTDRRListDAGScheduler - This creates a top down register usage 376 /// reduction list scheduler. 377 ScheduleDAG* createTDRRListDAGScheduler(SelectionDAGISel *IS, 378 SelectionDAG *DAG, 379 MachineBasicBlock *BB); 380 381 /// createTDListDAGScheduler - This creates a top-down list scheduler with 382 /// a hazard recognizer. 383 ScheduleDAG* createTDListDAGScheduler(SelectionDAGISel *IS, 384 SelectionDAG *DAG, 385 MachineBasicBlock *BB); 386 387 /// createDefaultScheduler - This creates an instruction scheduler appropriate 388 /// for the target. 389 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, 390 SelectionDAG *DAG, 391 MachineBasicBlock *BB); 392 393 class SUnitIterator : public forward_iterator<SUnit, ptrdiff_t> { 394 SUnit *Node; 395 unsigned Operand; 396 397 SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {} 398 public: 399 bool operator==(const SUnitIterator& x) const { 400 return Operand == x.Operand; 401 } 402 bool operator!=(const SUnitIterator& x) const { return !operator==(x); } 403 404 const SUnitIterator &operator=(const SUnitIterator &I) { 405 assert(I.Node == Node && "Cannot assign iterators to two different nodes!"); 406 Operand = I.Operand; 407 return *this; 408 } 409 410 pointer operator*() const { 411 return Node->Preds[Operand].Dep; 412 } 413 pointer operator->() const { return operator*(); } 414 415 SUnitIterator& operator++() { // Preincrement 416 ++Operand; 417 return *this; 418 } 419 SUnitIterator operator++(int) { // Postincrement 420 SUnitIterator tmp = *this; ++*this; return tmp; 421 } 422 423 static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); } 424 static SUnitIterator end (SUnit *N) { 425 return SUnitIterator(N, N->Preds.size()); 426 } 427 428 unsigned getOperand() const { return Operand; } 429 const SUnit *getNode() const { return Node; } 430 bool isCtrlDep() const { return Node->Preds[Operand].isCtrl; } 431 }; 432 433 template <> struct GraphTraits<SUnit*> { 434 typedef SUnit NodeType; 435 typedef SUnitIterator ChildIteratorType; 436 static inline NodeType *getEntryNode(SUnit *N) { return N; } 437 static inline ChildIteratorType child_begin(NodeType *N) { 438 return SUnitIterator::begin(N); 439 } 440 static inline ChildIteratorType child_end(NodeType *N) { 441 return SUnitIterator::end(N); 442 } 443 }; 444 445 template <> struct GraphTraits<ScheduleDAG*> : public GraphTraits<SUnit*> { 446 typedef std::vector<SUnit>::iterator nodes_iterator; 447 static nodes_iterator nodes_begin(ScheduleDAG *G) { 448 return G->SUnits.begin(); 449 } 450 static nodes_iterator nodes_end(ScheduleDAG *G) { 451 return G->SUnits.end(); 452 } 453 }; 454} 455 456#endif 457