ScheduleDAG.h revision 710461688bba935f0ad5c75da7fec2ad0f225c00
1//===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the ScheduleDAG class, which is used as the common 11// base class for instruction schedulers. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_CODEGEN_SCHEDULEDAG_H 16#define LLVM_CODEGEN_SCHEDULEDAG_H 17 18#include "llvm/CodeGen/MachineBasicBlock.h" 19#include "llvm/ADT/DenseMap.h" 20#include "llvm/ADT/BitVector.h" 21#include "llvm/ADT/GraphTraits.h" 22#include "llvm/ADT/SmallVector.h" 23#include "llvm/ADT/PointerIntPair.h" 24 25namespace llvm { 26 class SUnit; 27 class MachineConstantPool; 28 class MachineFunction; 29 class MachineModuleInfo; 30 class MachineRegisterInfo; 31 class MachineInstr; 32 class TargetRegisterInfo; 33 class ScheduleDAG; 34 class SDNode; 35 class TargetInstrInfo; 36 class TargetInstrDesc; 37 class TargetLowering; 38 class TargetMachine; 39 class TargetRegisterClass; 40 template<class Graph> class GraphWriter; 41 42 /// SDep - Scheduling dependency. This represents one direction of an 43 /// edge in the scheduling DAG. 44 class SDep { 45 public: 46 /// Kind - These are the different kinds of scheduling dependencies. 47 enum Kind { 48 Data, ///< Regular data dependence (aka true-dependence). 49 Anti, ///< A register anti-dependedence (aka WAR). 50 Output, ///< A register output-dependence (aka WAW). 51 Order ///< Any other ordering dependency. 52 }; 53 54 private: 55 /// Dep - A pointer to the depending/depended-on SUnit, and an enum 56 /// indicating the kind of the dependency. 57 PointerIntPair<SUnit *, 2, Kind> Dep; 58 59 /// Contents - A union discriminated by the dependence kind. 60 union { 61 /// Reg - For Data, Anti, and Output dependencies, the associated 62 /// register. For Data dependencies that don't currently have a register 63 /// assigned, this is set to zero. 64 unsigned Reg; 65 66 /// Order - Additional information about Order dependencies. 67 struct { 68 /// isNormalMemory - True if both sides of the dependence 69 /// access memory in non-volatile and fully modeled ways. 70 bool isNormalMemory : 1; 71 72 /// isMustAlias - True if both sides of the dependence are known to 73 /// access the same memory. 74 bool isMustAlias : 1; 75 76 /// isArtificial - True if this is an artificial dependency, meaning 77 /// it is not necessary for program correctness, and may be safely 78 /// deleted if necessary. 79 bool isArtificial : 1; 80 } Order; 81 } Contents; 82 83 /// Latency - The time associated with this edge. Often this is just 84 /// the value of the Latency field of the predecessor, however advanced 85 /// models may provide additional information about specific edges. 86 unsigned Latency; 87 88 public: 89 /// SDep - Construct a null SDep. This is only for use by container 90 /// classes which require default constructors. SUnits may not 91 /// have null SDep edges. 92 SDep() : Dep(0, Data) {} 93 94 /// SDep - Construct an SDep with the specified values. 95 SDep(SUnit *S, Kind kind, unsigned latency = 1, unsigned Reg = 0, 96 bool isNormalMemory = false, bool isMustAlias = false, 97 bool isArtificial = false) 98 : Dep(S, kind), Contents(), Latency(latency) { 99 switch (kind) { 100 case Anti: 101 case Output: 102 assert(Reg != 0 && 103 "SDep::Anti and SDep::Output must use a non-zero Reg!"); 104 // fall through 105 case Data: 106 assert(!isMustAlias && "isMustAlias only applies with SDep::Order!"); 107 assert(!isArtificial && "isArtificial only applies with SDep::Order!"); 108 Contents.Reg = Reg; 109 break; 110 case Order: 111 assert(Reg == 0 && "Reg given for non-register dependence!"); 112 Contents.Order.isNormalMemory = isNormalMemory; 113 Contents.Order.isMustAlias = isMustAlias; 114 Contents.Order.isArtificial = isArtificial; 115 break; 116 } 117 } 118 119 bool operator==(const SDep &Other) const { 120 if (Dep != Other.Dep || Latency != Other.Latency) return false; 121 switch (Dep.getInt()) { 122 case Data: 123 case Anti: 124 case Output: 125 return Contents.Reg == Other.Contents.Reg; 126 case Order: 127 return Contents.Order.isNormalMemory == 128 Other.Contents.Order.isNormalMemory && 129 Contents.Order.isMustAlias == Other.Contents.Order.isMustAlias && 130 Contents.Order.isArtificial == Other.Contents.Order.isArtificial; 131 } 132 assert(0 && "Invalid dependency kind!"); 133 return false; 134 } 135 136 bool operator!=(const SDep &Other) const { 137 return !operator==(Other); 138 } 139 140 /// getLatency - Return the latency value for this edge, which roughly 141 /// means the minimum number of cycles that must elapse between the 142 /// predecessor and the successor, given that they have this edge 143 /// between them. 144 unsigned getLatency() const { 145 return Latency; 146 } 147 148 /// setLatency - Set the latency for this edge. 149 void setLatency(unsigned Lat) { 150 Latency = Lat; 151 } 152 153 //// getSUnit - Return the SUnit to which this edge points. 154 SUnit *getSUnit() const { 155 return Dep.getPointer(); 156 } 157 158 //// setSUnit - Assign the SUnit to which this edge points. 159 void setSUnit(SUnit *SU) { 160 Dep.setPointer(SU); 161 } 162 163 /// getKind - Return an enum value representing the kind of the dependence. 164 Kind getKind() const { 165 return Dep.getInt(); 166 } 167 168 /// isCtrl - Shorthand for getKind() != SDep::Data. 169 bool isCtrl() const { 170 return getKind() != Data; 171 } 172 173 /// isNormalMemory - Test if this is an Order dependence between two 174 /// memory accesses where both sides of the dependence access memory 175 /// in non-volatile and fully modeled ways. 176 bool isNormalMemory() const { 177 return getKind() == Order && Contents.Order.isNormalMemory; 178 } 179 180 /// isMustAlias - Test if this is an Order dependence that is marked 181 /// as "must alias", meaning that the SUnits at either end of the edge 182 /// have a memory dependence on a known memory location. 183 bool isMustAlias() const { 184 return getKind() == Order && Contents.Order.isMustAlias; 185 } 186 187 /// isArtificial - Test if this is an Order dependence that is marked 188 /// as "artificial", meaning it isn't necessary for correctness. 189 bool isArtificial() const { 190 return getKind() == Order && Contents.Order.isArtificial; 191 } 192 193 /// isAssignedRegDep - Test if this is a Data dependence that is 194 /// associated with a register. 195 bool isAssignedRegDep() const { 196 return getKind() == Data && Contents.Reg != 0; 197 } 198 199 /// getReg - Return the register associated with this edge. This is 200 /// only valid on Data, Anti, and Output edges. On Data edges, this 201 /// value may be zero, meaning there is no associated register. 202 unsigned getReg() const { 203 assert((getKind() == Data || getKind() == Anti || getKind() == Output) && 204 "getReg called on non-register dependence edge!"); 205 return Contents.Reg; 206 } 207 208 /// setReg - Assign the associated register for this edge. This is 209 /// only valid on Data, Anti, and Output edges. On Anti and Output 210 /// edges, this value must not be zero. On Data edges, the value may 211 /// be zero, which would mean that no specific register is associated 212 /// with this edge. 213 void setReg(unsigned Reg) { 214 assert((getKind() == Data || getKind() == Anti || getKind() == Output) && 215 "setReg called on non-register dependence edge!"); 216 assert((getKind() != Anti || Reg != 0) && 217 "SDep::Anti edge cannot use the zero register!"); 218 assert((getKind() != Output || Reg != 0) && 219 "SDep::Output edge cannot use the zero register!"); 220 Contents.Reg = Reg; 221 } 222 }; 223 224 /// SUnit - Scheduling unit. This is a node in the scheduling DAG. 225 class SUnit { 226 private: 227 SDNode *Node; // Representative node. 228 MachineInstr *Instr; // Alternatively, a MachineInstr. 229 public: 230 SUnit *OrigNode; // If not this, the node from which 231 // this node was cloned. 232 233 // Preds/Succs - The SUnits before/after us in the graph. The boolean value 234 // is true if the edge is a token chain edge, false if it is a value edge. 235 SmallVector<SDep, 4> Preds; // All sunit predecessors. 236 SmallVector<SDep, 4> Succs; // All sunit successors. 237 238 typedef SmallVector<SDep, 4>::iterator pred_iterator; 239 typedef SmallVector<SDep, 4>::iterator succ_iterator; 240 typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator; 241 typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator; 242 243 unsigned NodeNum; // Entry # of node in the node vector. 244 unsigned NodeQueueId; // Queue id of node. 245 unsigned short Latency; // Node latency. 246 short NumPreds; // # of SDep::Data preds. 247 short NumSuccs; // # of SDep::Data sucss. 248 short NumPredsLeft; // # of preds not scheduled. 249 short NumSuccsLeft; // # of succs not scheduled. 250 bool isTwoAddress : 1; // Is a two-address instruction. 251 bool isCommutable : 1; // Is a commutable instruction. 252 bool hasPhysRegDefs : 1; // Has physreg defs that are being used. 253 bool hasPhysRegClobbers : 1; // Has any physreg defs, used or not. 254 bool isPending : 1; // True once pending. 255 bool isAvailable : 1; // True once available. 256 bool isScheduled : 1; // True once scheduled. 257 bool isScheduleHigh : 1; // True if preferable to schedule high. 258 bool isCloned : 1; // True if this node has been cloned. 259 private: 260 bool isDepthCurrent : 1; // True if Depth is current. 261 bool isHeightCurrent : 1; // True if Height is current. 262 unsigned Depth; // Node depth. 263 unsigned Height; // Node height. 264 public: 265 const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null. 266 const TargetRegisterClass *CopySrcRC; 267 268 /// SUnit - Construct an SUnit for pre-regalloc scheduling to represent 269 /// an SDNode and any nodes flagged to it. 270 SUnit(SDNode *node, unsigned nodenum) 271 : Node(node), Instr(0), OrigNode(0), NodeNum(nodenum), NodeQueueId(0), 272 Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0), 273 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false), 274 hasPhysRegClobbers(false), 275 isPending(false), isAvailable(false), isScheduled(false), 276 isScheduleHigh(false), isCloned(false), 277 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), 278 CopyDstRC(NULL), CopySrcRC(NULL) {} 279 280 /// SUnit - Construct an SUnit for post-regalloc scheduling to represent 281 /// a MachineInstr. 282 SUnit(MachineInstr *instr, unsigned nodenum) 283 : Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum), NodeQueueId(0), 284 Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0), 285 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false), 286 hasPhysRegClobbers(false), 287 isPending(false), isAvailable(false), isScheduled(false), 288 isScheduleHigh(false), isCloned(false), 289 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), 290 CopyDstRC(NULL), CopySrcRC(NULL) {} 291 292 /// SUnit - Construct a placeholder SUnit. 293 SUnit() 294 : Node(0), Instr(0), OrigNode(0), NodeNum(~0u), NodeQueueId(0), 295 Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0), 296 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false), 297 hasPhysRegClobbers(false), 298 isPending(false), isAvailable(false), isScheduled(false), 299 isScheduleHigh(false), isCloned(false), 300 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), 301 CopyDstRC(NULL), CopySrcRC(NULL) {} 302 303 /// setNode - Assign the representative SDNode for this SUnit. 304 /// This may be used during pre-regalloc scheduling. 305 void setNode(SDNode *N) { 306 assert(!Instr && "Setting SDNode of SUnit with MachineInstr!"); 307 Node = N; 308 } 309 310 /// getNode - Return the representative SDNode for this SUnit. 311 /// This may be used during pre-regalloc scheduling. 312 SDNode *getNode() const { 313 assert(!Instr && "Reading SDNode of SUnit with MachineInstr!"); 314 return Node; 315 } 316 317 /// setInstr - Assign the instruction for the SUnit. 318 /// This may be used during post-regalloc scheduling. 319 void setInstr(MachineInstr *MI) { 320 assert(!Node && "Setting MachineInstr of SUnit with SDNode!"); 321 Instr = MI; 322 } 323 324 /// getInstr - Return the representative MachineInstr for this SUnit. 325 /// This may be used during post-regalloc scheduling. 326 MachineInstr *getInstr() const { 327 assert(!Node && "Reading MachineInstr of SUnit with SDNode!"); 328 return Instr; 329 } 330 331 /// addPred - This adds the specified edge as a pred of the current node if 332 /// not already. It also adds the current node as a successor of the 333 /// specified node. 334 void addPred(const SDep &D); 335 336 /// removePred - This removes the specified edge as a pred of the current 337 /// node if it exists. It also removes the current node as a successor of 338 /// the specified node. 339 void removePred(const SDep &D); 340 341 /// getDepth - Return the depth of this node, which is the length of the 342 /// maximum path up to any node with has no predecessors. 343 unsigned getDepth() const { 344 if (!isDepthCurrent) const_cast<SUnit *>(this)->ComputeDepth(); 345 return Depth; 346 } 347 348 /// getHeight - Return the height of this node, which is the length of the 349 /// maximum path down to any node with has no successors. 350 unsigned getHeight() const { 351 if (!isHeightCurrent) const_cast<SUnit *>(this)->ComputeHeight(); 352 return Height; 353 } 354 355 /// setDepthToAtLeast - If NewDepth is greater than this node's depth 356 /// value, set it to be the new depth value. This also recursively 357 /// marks successor nodes dirty. 358 void setDepthToAtLeast(unsigned NewDepth); 359 360 /// setDepthToAtLeast - If NewDepth is greater than this node's depth 361 /// value, set it to be the new height value. This also recursively 362 /// marks predecessor nodes dirty. 363 void setHeightToAtLeast(unsigned NewHeight); 364 365 /// setDepthDirty - Set a flag in this node to indicate that its 366 /// stored Depth value will require recomputation the next time 367 /// getDepth() is called. 368 void setDepthDirty(); 369 370 /// setHeightDirty - Set a flag in this node to indicate that its 371 /// stored Height value will require recomputation the next time 372 /// getHeight() is called. 373 void setHeightDirty(); 374 375 /// isPred - Test if node N is a predecessor of this node. 376 bool isPred(SUnit *N) { 377 for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i) 378 if (Preds[i].getSUnit() == N) 379 return true; 380 return false; 381 } 382 383 /// isSucc - Test if node N is a successor of this node. 384 bool isSucc(SUnit *N) { 385 for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i) 386 if (Succs[i].getSUnit() == N) 387 return true; 388 return false; 389 } 390 391 void dump(const ScheduleDAG *G) const; 392 void dumpAll(const ScheduleDAG *G) const; 393 void print(raw_ostream &O, const ScheduleDAG *G) const; 394 395 private: 396 void ComputeDepth(); 397 void ComputeHeight(); 398 }; 399 400 //===--------------------------------------------------------------------===// 401 /// SchedulingPriorityQueue - This interface is used to plug different 402 /// priorities computation algorithms into the list scheduler. It implements 403 /// the interface of a standard priority queue, where nodes are inserted in 404 /// arbitrary order and returned in priority order. The computation of the 405 /// priority and the representation of the queue are totally up to the 406 /// implementation to decide. 407 /// 408 class SchedulingPriorityQueue { 409 public: 410 virtual ~SchedulingPriorityQueue() {} 411 412 virtual void initNodes(std::vector<SUnit> &SUnits) = 0; 413 virtual void addNode(const SUnit *SU) = 0; 414 virtual void updateNode(const SUnit *SU) = 0; 415 virtual void releaseState() = 0; 416 417 virtual unsigned size() const = 0; 418 virtual bool empty() const = 0; 419 virtual void push(SUnit *U) = 0; 420 421 virtual void push_all(const std::vector<SUnit *> &Nodes) = 0; 422 virtual SUnit *pop() = 0; 423 424 virtual void remove(SUnit *SU) = 0; 425 426 /// ScheduledNode - As each node is scheduled, this method is invoked. This 427 /// allows the priority function to adjust the priority of related 428 /// unscheduled nodes, for example. 429 /// 430 virtual void ScheduledNode(SUnit *) {} 431 432 virtual void UnscheduledNode(SUnit *) {} 433 }; 434 435 class ScheduleDAG { 436 public: 437 MachineBasicBlock *BB; // The block in which to insert instructions. 438 MachineBasicBlock::iterator InsertPos;// The position to insert instructions. 439 const TargetMachine &TM; // Target processor 440 const TargetInstrInfo *TII; // Target instruction information 441 const TargetRegisterInfo *TRI; // Target processor register info 442 const TargetLowering *TLI; // Target lowering info 443 MachineFunction &MF; // Machine function 444 MachineRegisterInfo &MRI; // Virtual/real register map 445 MachineConstantPool *ConstPool; // Target constant pool 446 std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s 447 // represent noop instructions. 448 std::vector<SUnit> SUnits; // The scheduling units. 449 SUnit EntrySU; // Special node for the region entry. 450 SUnit ExitSU; // Special node for the region exit. 451 452 explicit ScheduleDAG(MachineFunction &mf); 453 454 virtual ~ScheduleDAG(); 455 456 /// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered 457 /// using 'dot'. 458 /// 459 void viewGraph(); 460 461 /// EmitSchedule - Insert MachineInstrs into the MachineBasicBlock 462 /// according to the order specified in Sequence. 463 /// 464 virtual MachineBasicBlock *EmitSchedule() = 0; 465 466 void dumpSchedule() const; 467 468 virtual void dumpNode(const SUnit *SU) const = 0; 469 470 /// getGraphNodeLabel - Return a label for an SUnit node in a visualization 471 /// of the ScheduleDAG. 472 virtual std::string getGraphNodeLabel(const SUnit *SU) const = 0; 473 474 /// addCustomGraphFeatures - Add custom features for a visualization of 475 /// the ScheduleDAG. 476 virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {} 477 478#ifndef NDEBUG 479 /// VerifySchedule - Verify that all SUnits were scheduled and that 480 /// their state is consistent. 481 void VerifySchedule(bool isBottomUp); 482#endif 483 484 protected: 485 /// Run - perform scheduling. 486 /// 487 void Run(MachineBasicBlock *bb, MachineBasicBlock::iterator insertPos); 488 489 /// BuildSchedGraph - Build SUnits and set up their Preds and Succs 490 /// to form the scheduling dependency graph. 491 /// 492 virtual void BuildSchedGraph() = 0; 493 494 /// ComputeLatency - Compute node latency. 495 /// 496 virtual void ComputeLatency(SUnit *SU) = 0; 497 498 /// Schedule - Order nodes according to selected style, filling 499 /// in the Sequence member. 500 /// 501 virtual void Schedule() = 0; 502 503 /// ForceUnitLatencies - Return true if all scheduling edges should be given a 504 /// latency value of one. The default is to return false; schedulers may 505 /// override this as needed. 506 virtual bool ForceUnitLatencies() const { return false; } 507 508 /// EmitNoop - Emit a noop instruction. 509 /// 510 void EmitNoop(); 511 512 void AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO); 513 514 void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap); 515 516 private: 517 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the 518 /// physical register has only a single copy use, then coalesced the copy 519 /// if possible. 520 void EmitLiveInCopy(MachineBasicBlock *MBB, 521 MachineBasicBlock::iterator &InsertPos, 522 unsigned VirtReg, unsigned PhysReg, 523 const TargetRegisterClass *RC, 524 DenseMap<MachineInstr*, unsigned> &CopyRegMap); 525 526 /// EmitLiveInCopies - If this is the first basic block in the function, 527 /// and if it has live ins that need to be copied into vregs, emit the 528 /// copies into the top of the block. 529 void EmitLiveInCopies(MachineBasicBlock *MBB); 530 }; 531 532 class SUnitIterator : public forward_iterator<SUnit, ptrdiff_t> { 533 SUnit *Node; 534 unsigned Operand; 535 536 SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {} 537 public: 538 bool operator==(const SUnitIterator& x) const { 539 return Operand == x.Operand; 540 } 541 bool operator!=(const SUnitIterator& x) const { return !operator==(x); } 542 543 const SUnitIterator &operator=(const SUnitIterator &I) { 544 assert(I.Node == Node && "Cannot assign iterators to two different nodes!"); 545 Operand = I.Operand; 546 return *this; 547 } 548 549 pointer operator*() const { 550 return Node->Preds[Operand].getSUnit(); 551 } 552 pointer operator->() const { return operator*(); } 553 554 SUnitIterator& operator++() { // Preincrement 555 ++Operand; 556 return *this; 557 } 558 SUnitIterator operator++(int) { // Postincrement 559 SUnitIterator tmp = *this; ++*this; return tmp; 560 } 561 562 static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); } 563 static SUnitIterator end (SUnit *N) { 564 return SUnitIterator(N, (unsigned)N->Preds.size()); 565 } 566 567 unsigned getOperand() const { return Operand; } 568 const SUnit *getNode() const { return Node; } 569 /// isCtrlDep - Test if this is not an SDep::Data dependence. 570 bool isCtrlDep() const { 571 return getSDep().isCtrl(); 572 } 573 bool isArtificialDep() const { 574 return getSDep().isArtificial(); 575 } 576 const SDep &getSDep() const { 577 return Node->Preds[Operand]; 578 } 579 }; 580 581 template <> struct GraphTraits<SUnit*> { 582 typedef SUnit NodeType; 583 typedef SUnitIterator ChildIteratorType; 584 static inline NodeType *getEntryNode(SUnit *N) { return N; } 585 static inline ChildIteratorType child_begin(NodeType *N) { 586 return SUnitIterator::begin(N); 587 } 588 static inline ChildIteratorType child_end(NodeType *N) { 589 return SUnitIterator::end(N); 590 } 591 }; 592 593 template <> struct GraphTraits<ScheduleDAG*> : public GraphTraits<SUnit*> { 594 typedef std::vector<SUnit>::iterator nodes_iterator; 595 static nodes_iterator nodes_begin(ScheduleDAG *G) { 596 return G->SUnits.begin(); 597 } 598 static nodes_iterator nodes_end(ScheduleDAG *G) { 599 return G->SUnits.end(); 600 } 601 }; 602 603 /// ScheduleDAGTopologicalSort is a class that computes a topological 604 /// ordering for SUnits and provides methods for dynamically updating 605 /// the ordering as new edges are added. 606 /// 607 /// This allows a very fast implementation of IsReachable, for example. 608 /// 609 class ScheduleDAGTopologicalSort { 610 /// SUnits - A reference to the ScheduleDAG's SUnits. 611 std::vector<SUnit> &SUnits; 612 613 /// Index2Node - Maps topological index to the node number. 614 std::vector<int> Index2Node; 615 /// Node2Index - Maps the node number to its topological index. 616 std::vector<int> Node2Index; 617 /// Visited - a set of nodes visited during a DFS traversal. 618 BitVector Visited; 619 620 /// DFS - make a DFS traversal and mark all nodes affected by the 621 /// edge insertion. These nodes will later get new topological indexes 622 /// by means of the Shift method. 623 void DFS(const SUnit *SU, int UpperBound, bool& HasLoop); 624 625 /// Shift - reassign topological indexes for the nodes in the DAG 626 /// to preserve the topological ordering. 627 void Shift(BitVector& Visited, int LowerBound, int UpperBound); 628 629 /// Allocate - assign the topological index to the node n. 630 void Allocate(int n, int index); 631 632 public: 633 explicit ScheduleDAGTopologicalSort(std::vector<SUnit> &SUnits); 634 635 /// InitDAGTopologicalSorting - create the initial topological 636 /// ordering from the DAG to be scheduled. 637 void InitDAGTopologicalSorting(); 638 639 /// IsReachable - Checks if SU is reachable from TargetSU. 640 bool IsReachable(const SUnit *SU, const SUnit *TargetSU); 641 642 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU 643 /// will create a cycle. 644 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU); 645 646 /// AddPred - Updates the topological ordering to accomodate an edge 647 /// to be added from SUnit X to SUnit Y. 648 void AddPred(SUnit *Y, SUnit *X); 649 650 /// RemovePred - Updates the topological ordering to accomodate an 651 /// an edge to be removed from the specified node N from the predecessors 652 /// of the current node M. 653 void RemovePred(SUnit *M, SUnit *N); 654 655 typedef std::vector<int>::iterator iterator; 656 typedef std::vector<int>::const_iterator const_iterator; 657 iterator begin() { return Index2Node.begin(); } 658 const_iterator begin() const { return Index2Node.begin(); } 659 iterator end() { return Index2Node.end(); } 660 const_iterator end() const { return Index2Node.end(); } 661 662 typedef std::vector<int>::reverse_iterator reverse_iterator; 663 typedef std::vector<int>::const_reverse_iterator const_reverse_iterator; 664 reverse_iterator rbegin() { return Index2Node.rbegin(); } 665 const_reverse_iterator rbegin() const { return Index2Node.rbegin(); } 666 reverse_iterator rend() { return Index2Node.rend(); } 667 const_reverse_iterator rend() const { return Index2Node.rend(); } 668 }; 669} 670 671#endif 672