ScheduleDAG.h revision 89bf4f2f5e6f54fe6382f07c515e36adc9e0c9c2
1//===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the ScheduleDAG class, which is used as the common 11// base class for instruction schedulers. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_CODEGEN_SCHEDULEDAG_H 16#define LLVM_CODEGEN_SCHEDULEDAG_H 17 18#include "llvm/CodeGen/MachineBasicBlock.h" 19#include "llvm/ADT/DenseMap.h" 20#include "llvm/ADT/BitVector.h" 21#include "llvm/ADT/GraphTraits.h" 22#include "llvm/ADT/SmallVector.h" 23#include "llvm/ADT/PointerIntPair.h" 24 25namespace llvm { 26 struct SUnit; 27 class MachineConstantPool; 28 class MachineFunction; 29 class MachineModuleInfo; 30 class MachineRegisterInfo; 31 class MachineInstr; 32 class TargetRegisterInfo; 33 class ScheduleDAG; 34 class SelectionDAG; 35 class SDNode; 36 class TargetInstrInfo; 37 class TargetInstrDesc; 38 class TargetLowering; 39 class TargetMachine; 40 class TargetRegisterClass; 41 template<class Graph> class GraphWriter; 42 43 /// SDep - Scheduling dependency. This represents one direction of an 44 /// edge in the scheduling DAG. 45 class SDep { 46 public: 47 /// Kind - These are the different kinds of scheduling dependencies. 48 enum Kind { 49 Data, ///< Regular data dependence (aka true-dependence). 50 Anti, ///< A register anti-dependedence (aka WAR). 51 Output, ///< A register output-dependence (aka WAW). 52 Order ///< Any other ordering dependency. 53 }; 54 55 private: 56 /// Dep - A pointer to the depending/depended-on SUnit, and an enum 57 /// indicating the kind of the dependency. 58 PointerIntPair<SUnit *, 2, Kind> Dep; 59 60 /// Contents - A union discriminated by the dependence kind. 61 union { 62 /// Reg - For Data, Anti, and Output dependencies, the associated 63 /// register. For Data dependencies that don't currently have a register 64 /// assigned, this is set to zero. 65 unsigned Reg; 66 67 /// Order - Additional information about Order dependencies. 68 struct { 69 /// isNormalMemory - True if both sides of the dependence 70 /// access memory in non-volatile and fully modeled ways. 71 bool isNormalMemory : 1; 72 73 /// isMustAlias - True if both sides of the dependence are known to 74 /// access the same memory. 75 bool isMustAlias : 1; 76 77 /// isArtificial - True if this is an artificial dependency, meaning 78 /// it is not necessary for program correctness, and may be safely 79 /// deleted if necessary. 80 bool isArtificial : 1; 81 } Order; 82 } Contents; 83 84 /// Latency - The time associated with this edge. Often this is just 85 /// the value of the Latency field of the predecessor, however advanced 86 /// models may provide additional information about specific edges. 87 unsigned Latency; 88 89 public: 90 /// SDep - Construct a null SDep. This is only for use by container 91 /// classes which require default constructors. SUnits may not 92 /// have null SDep edges. 93 SDep() : Dep(0, Data) {} 94 95 /// SDep - Construct an SDep with the specified values. 96 SDep(SUnit *S, Kind kind, unsigned latency = 1, unsigned Reg = 0, 97 bool isNormalMemory = false, bool isMustAlias = false, 98 bool isArtificial = false) 99 : Dep(S, kind), Contents(), Latency(latency) { 100 switch (kind) { 101 case Anti: 102 case Output: 103 assert(Reg != 0 && 104 "SDep::Anti and SDep::Output must use a non-zero Reg!"); 105 // fall through 106 case Data: 107 assert(!isMustAlias && "isMustAlias only applies with SDep::Order!"); 108 assert(!isArtificial && "isArtificial only applies with SDep::Order!"); 109 Contents.Reg = Reg; 110 break; 111 case Order: 112 assert(Reg == 0 && "Reg given for non-register dependence!"); 113 Contents.Order.isNormalMemory = isNormalMemory; 114 Contents.Order.isMustAlias = isMustAlias; 115 Contents.Order.isArtificial = isArtificial; 116 break; 117 } 118 } 119 120 bool operator==(const SDep &Other) const { 121 if (Dep != Other.Dep || Latency != Other.Latency) return false; 122 switch (Dep.getInt()) { 123 case Data: 124 case Anti: 125 case Output: 126 return Contents.Reg == Other.Contents.Reg; 127 case Order: 128 return Contents.Order.isNormalMemory == 129 Other.Contents.Order.isNormalMemory && 130 Contents.Order.isMustAlias == Other.Contents.Order.isMustAlias && 131 Contents.Order.isArtificial == Other.Contents.Order.isArtificial; 132 } 133 assert(0 && "Invalid dependency kind!"); 134 return false; 135 } 136 137 bool operator!=(const SDep &Other) const { 138 return !operator==(Other); 139 } 140 141 /// getLatency - Return the latency value for this edge, which roughly 142 /// means the minimum number of cycles that must elapse between the 143 /// predecessor and the successor, given that they have this edge 144 /// between them. 145 unsigned getLatency() const { 146 return Latency; 147 } 148 149 //// getSUnit - Return the SUnit to which this edge points. 150 SUnit *getSUnit() const { 151 return Dep.getPointer(); 152 } 153 154 //// setSUnit - Assign the SUnit to which this edge points. 155 void setSUnit(SUnit *SU) { 156 Dep.setPointer(SU); 157 } 158 159 /// getKind - Return an enum value representing the kind of the dependence. 160 Kind getKind() const { 161 return Dep.getInt(); 162 } 163 164 /// isCtrl - Shorthand for getKind() != SDep::Data. 165 bool isCtrl() const { 166 return getKind() != Data; 167 } 168 169 /// isMustAlias - Test if this is an Order dependence that is marked 170 /// as "must alias", meaning that the SUnits at either end of the edge 171 /// have a memory dependence on a known memory location. 172 bool isMustAlias() const { 173 return getKind() == Order && Contents.Order.isMustAlias; 174 } 175 176 /// isArtificial - Test if this is an Order dependence that is marked 177 /// as "artificial", meaning it isn't necessary for correctness. 178 bool isArtificial() const { 179 return getKind() == Order && Contents.Order.isArtificial; 180 } 181 182 /// isAssignedRegDep - Test if this is a Data dependence that is 183 /// associated with a register. 184 bool isAssignedRegDep() const { 185 return getKind() == Data && Contents.Reg != 0; 186 } 187 188 /// getReg - Return the register associated with this edge. This is 189 /// only valid on Data, Anti, and Output edges. On Data edges, this 190 /// value may be zero, meaning there is no associated register. 191 unsigned getReg() const { 192 assert((getKind() == Data || getKind() == Anti || getKind() == Output) && 193 "getReg called on non-register dependence edge!"); 194 return Contents.Reg; 195 } 196 197 /// setReg - Assign the associated register for this edge. This is 198 /// only valid on Data, Anti, and Output edges. On Anti and Output 199 /// edges, this value must not be zero. On Data edges, the value may 200 /// be zero, which would mean that no specific register is associated 201 /// with this edge. 202 void setReg(unsigned Reg) { 203 assert((getKind() == Data || getKind() == Anti || getKind() == Output) && 204 "setReg called on non-register dependence edge!"); 205 assert((getKind() != Anti || Reg != 0) && 206 "SDep::Anti edge cannot use the zero register!"); 207 assert((getKind() != Output || Reg != 0) && 208 "SDep::Output edge cannot use the zero register!"); 209 Contents.Reg = Reg; 210 } 211 }; 212 213 /// SUnit - Scheduling unit. This is a node in the scheduling DAG. 214 struct SUnit { 215 private: 216 SDNode *Node; // Representative node. 217 MachineInstr *Instr; // Alternatively, a MachineInstr. 218 public: 219 SUnit *OrigNode; // If not this, the node from which 220 // this node was cloned. 221 222 // Preds/Succs - The SUnits before/after us in the graph. The boolean value 223 // is true if the edge is a token chain edge, false if it is a value edge. 224 SmallVector<SDep, 4> Preds; // All sunit predecessors. 225 SmallVector<SDep, 4> Succs; // All sunit successors. 226 227 typedef SmallVector<SDep, 4>::iterator pred_iterator; 228 typedef SmallVector<SDep, 4>::iterator succ_iterator; 229 typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator; 230 typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator; 231 232 unsigned NodeNum; // Entry # of node in the node vector. 233 unsigned NodeQueueId; // Queue id of node. 234 unsigned short Latency; // Node latency. 235 short NumPreds; // # of SDep::Data preds. 236 short NumSuccs; // # of SDep::Data sucss. 237 short NumPredsLeft; // # of preds not scheduled. 238 short NumSuccsLeft; // # of succs not scheduled. 239 bool isTwoAddress : 1; // Is a two-address instruction. 240 bool isCommutable : 1; // Is a commutable instruction. 241 bool hasPhysRegDefs : 1; // Has physreg defs that are being used. 242 bool isPending : 1; // True once pending. 243 bool isAvailable : 1; // True once available. 244 bool isScheduled : 1; // True once scheduled. 245 bool isScheduleHigh : 1; // True if preferable to schedule high. 246 private: 247 bool isDepthCurrent : 1; // True if Depth is current. 248 bool isHeightCurrent : 1; // True if Height is current. 249 unsigned Depth; // Node depth. 250 unsigned Height; // Node height. 251 public: 252 const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null. 253 const TargetRegisterClass *CopySrcRC; 254 255 /// SUnit - Construct an SUnit for pre-regalloc scheduling to represent 256 /// an SDNode and any nodes flagged to it. 257 SUnit(SDNode *node, unsigned nodenum) 258 : Node(node), Instr(0), OrigNode(0), NodeNum(nodenum), NodeQueueId(0), 259 Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0), 260 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false), 261 isPending(false), isAvailable(false), isScheduled(false), 262 isScheduleHigh(false), isDepthCurrent(false), isHeightCurrent(false), 263 Depth(0), Height(0), 264 CopyDstRC(NULL), CopySrcRC(NULL) {} 265 266 /// SUnit - Construct an SUnit for post-regalloc scheduling to represent 267 /// a MachineInstr. 268 SUnit(MachineInstr *instr, unsigned nodenum) 269 : Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum), NodeQueueId(0), 270 Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0), 271 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false), 272 isPending(false), isAvailable(false), isScheduled(false), 273 isScheduleHigh(false), isDepthCurrent(false), isHeightCurrent(false), 274 Depth(0), Height(0), 275 CopyDstRC(NULL), CopySrcRC(NULL) {} 276 277 /// setNode - Assign the representative SDNode for this SUnit. 278 /// This may be used during pre-regalloc scheduling. 279 void setNode(SDNode *N) { 280 assert(!Instr && "Setting SDNode of SUnit with MachineInstr!"); 281 Node = N; 282 } 283 284 /// getNode - Return the representative SDNode for this SUnit. 285 /// This may be used during pre-regalloc scheduling. 286 SDNode *getNode() const { 287 assert(!Instr && "Reading SDNode of SUnit with MachineInstr!"); 288 return Node; 289 } 290 291 /// setInstr - Assign the instruction for the SUnit. 292 /// This may be used during post-regalloc scheduling. 293 void setInstr(MachineInstr *MI) { 294 assert(!Node && "Setting MachineInstr of SUnit with SDNode!"); 295 Instr = MI; 296 } 297 298 /// getInstr - Return the representative MachineInstr for this SUnit. 299 /// This may be used during post-regalloc scheduling. 300 MachineInstr *getInstr() const { 301 assert(!Node && "Reading MachineInstr of SUnit with SDNode!"); 302 return Instr; 303 } 304 305 /// addPred - This adds the specified edge as a pred of the current node if 306 /// not already. It also adds the current node as a successor of the 307 /// specified node. 308 void addPred(const SDep &D); 309 310 /// removePred - This removes the specified edge as a pred of the current 311 /// node if it exists. It also removes the current node as a successor of 312 /// the specified node. 313 void removePred(const SDep &D); 314 315 /// getDepth - Return the depth of this node, which is the length of the 316 /// maximum path up to any node with has no predecessors. 317 unsigned getDepth() const { 318 if (!isDepthCurrent) const_cast<SUnit *>(this)->ComputeDepth(); 319 return Depth; 320 } 321 322 /// getHeight - Return the height of this node, which is the length of the 323 /// maximum path down to any node with has no successors. 324 unsigned getHeight() const { 325 if (!isHeightCurrent) const_cast<SUnit *>(this)->ComputeHeight(); 326 return Height; 327 } 328 329 /// setDepthToAtLeast - If NewDepth is greater than this node's depth 330 /// value, set it to be the new depth value. This also recursively 331 /// marks successor nodes dirty. 332 void setDepthToAtLeast(unsigned NewDepth); 333 334 /// setDepthToAtLeast - If NewDepth is greater than this node's depth 335 /// value, set it to be the new height value. This also recursively 336 /// marks predecessor nodes dirty. 337 void setHeightToAtLeast(unsigned NewHeight); 338 339 /// setDepthDirty - Set a flag in this node to indicate that its 340 /// stored Depth value will require recomputation the next time 341 /// getDepth() is called. 342 void setDepthDirty(); 343 344 /// setHeightDirty - Set a flag in this node to indicate that its 345 /// stored Height value will require recomputation the next time 346 /// getHeight() is called. 347 void setHeightDirty(); 348 349 /// isPred - Test if node N is a predecessor of this node. 350 bool isPred(SUnit *N) { 351 for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i) 352 if (Preds[i].getSUnit() == N) 353 return true; 354 return false; 355 } 356 357 /// isSucc - Test if node N is a successor of this node. 358 bool isSucc(SUnit *N) { 359 for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i) 360 if (Succs[i].getSUnit() == N) 361 return true; 362 return false; 363 } 364 365 void dump(const ScheduleDAG *G) const; 366 void dumpAll(const ScheduleDAG *G) const; 367 void print(raw_ostream &O, const ScheduleDAG *G) const; 368 369 private: 370 void ComputeDepth(); 371 void ComputeHeight(); 372 }; 373 374 //===--------------------------------------------------------------------===// 375 /// SchedulingPriorityQueue - This interface is used to plug different 376 /// priorities computation algorithms into the list scheduler. It implements 377 /// the interface of a standard priority queue, where nodes are inserted in 378 /// arbitrary order and returned in priority order. The computation of the 379 /// priority and the representation of the queue are totally up to the 380 /// implementation to decide. 381 /// 382 class SchedulingPriorityQueue { 383 public: 384 virtual ~SchedulingPriorityQueue() {} 385 386 virtual void initNodes(std::vector<SUnit> &SUnits) = 0; 387 virtual void addNode(const SUnit *SU) = 0; 388 virtual void updateNode(const SUnit *SU) = 0; 389 virtual void releaseState() = 0; 390 391 virtual unsigned size() const = 0; 392 virtual bool empty() const = 0; 393 virtual void push(SUnit *U) = 0; 394 395 virtual void push_all(const std::vector<SUnit *> &Nodes) = 0; 396 virtual SUnit *pop() = 0; 397 398 virtual void remove(SUnit *SU) = 0; 399 400 /// ScheduledNode - As each node is scheduled, this method is invoked. This 401 /// allows the priority function to adjust the priority of related 402 /// unscheduled nodes, for example. 403 /// 404 virtual void ScheduledNode(SUnit *) {} 405 406 virtual void UnscheduledNode(SUnit *) {} 407 }; 408 409 class ScheduleDAG { 410 public: 411 SelectionDAG *DAG; // DAG of the current basic block 412 MachineBasicBlock *BB; // Current basic block 413 const TargetMachine &TM; // Target processor 414 const TargetInstrInfo *TII; // Target instruction information 415 const TargetRegisterInfo *TRI; // Target processor register info 416 TargetLowering *TLI; // Target lowering info 417 MachineFunction *MF; // Machine function 418 MachineRegisterInfo &MRI; // Virtual/real register map 419 MachineConstantPool *ConstPool; // Target constant pool 420 std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s 421 // represent noop instructions. 422 std::vector<SUnit> SUnits; // The scheduling units. 423 424 ScheduleDAG(SelectionDAG *dag, MachineBasicBlock *bb, 425 const TargetMachine &tm); 426 427 virtual ~ScheduleDAG(); 428 429 /// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered 430 /// using 'dot'. 431 /// 432 void viewGraph(); 433 434 /// Run - perform scheduling. 435 /// 436 void Run(); 437 438 /// BuildSchedUnits - Build SUnits and set up their Preds and Succs 439 /// to form the scheduling dependency graph. 440 /// 441 virtual void BuildSchedUnits() = 0; 442 443 /// ComputeLatency - Compute node latency. 444 /// 445 virtual void ComputeLatency(SUnit *SU) = 0; 446 447 protected: 448 /// EmitNoop - Emit a noop instruction. 449 /// 450 void EmitNoop(); 451 452 public: 453 virtual MachineBasicBlock *EmitSchedule() = 0; 454 455 void dumpSchedule() const; 456 457 /// Schedule - Order nodes according to selected style, filling 458 /// in the Sequence member. 459 /// 460 virtual void Schedule() = 0; 461 462 virtual void dumpNode(const SUnit *SU) const = 0; 463 464 /// getGraphNodeLabel - Return a label for an SUnit node in a visualization 465 /// of the ScheduleDAG. 466 virtual std::string getGraphNodeLabel(const SUnit *SU) const = 0; 467 468 /// addCustomGraphFeatures - Add custom features for a visualization of 469 /// the ScheduleDAG. 470 virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {} 471 472#ifndef NDEBUG 473 /// VerifySchedule - Verify that all SUnits were scheduled and that 474 /// their state is consistent. 475 void VerifySchedule(bool isBottomUp); 476#endif 477 478 protected: 479 void AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO); 480 481 void EmitCrossRCCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap); 482 483 /// ForceUnitLatencies - Return true if all scheduling edges should be given a 484 /// latency value of one. The default is to return false; schedulers may 485 /// override this as needed. 486 virtual bool ForceUnitLatencies() const { return false; } 487 488 private: 489 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the 490 /// physical register has only a single copy use, then coalesced the copy 491 /// if possible. 492 void EmitLiveInCopy(MachineBasicBlock *MBB, 493 MachineBasicBlock::iterator &InsertPos, 494 unsigned VirtReg, unsigned PhysReg, 495 const TargetRegisterClass *RC, 496 DenseMap<MachineInstr*, unsigned> &CopyRegMap); 497 498 /// EmitLiveInCopies - If this is the first basic block in the function, 499 /// and if it has live ins that need to be copied into vregs, emit the 500 /// copies into the top of the block. 501 void EmitLiveInCopies(MachineBasicBlock *MBB); 502 }; 503 504 class SUnitIterator : public forward_iterator<SUnit, ptrdiff_t> { 505 SUnit *Node; 506 unsigned Operand; 507 508 SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {} 509 public: 510 bool operator==(const SUnitIterator& x) const { 511 return Operand == x.Operand; 512 } 513 bool operator!=(const SUnitIterator& x) const { return !operator==(x); } 514 515 const SUnitIterator &operator=(const SUnitIterator &I) { 516 assert(I.Node == Node && "Cannot assign iterators to two different nodes!"); 517 Operand = I.Operand; 518 return *this; 519 } 520 521 pointer operator*() const { 522 return Node->Preds[Operand].getSUnit(); 523 } 524 pointer operator->() const { return operator*(); } 525 526 SUnitIterator& operator++() { // Preincrement 527 ++Operand; 528 return *this; 529 } 530 SUnitIterator operator++(int) { // Postincrement 531 SUnitIterator tmp = *this; ++*this; return tmp; 532 } 533 534 static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); } 535 static SUnitIterator end (SUnit *N) { 536 return SUnitIterator(N, (unsigned)N->Preds.size()); 537 } 538 539 unsigned getOperand() const { return Operand; } 540 const SUnit *getNode() const { return Node; } 541 /// isCtrlDep - Test if this is not an SDep::Data dependence. 542 bool isCtrlDep() const { 543 return getSDep().isCtrl(); 544 } 545 bool isArtificialDep() const { 546 return getSDep().isArtificial(); 547 } 548 const SDep &getSDep() const { 549 return Node->Preds[Operand]; 550 } 551 }; 552 553 template <> struct GraphTraits<SUnit*> { 554 typedef SUnit NodeType; 555 typedef SUnitIterator ChildIteratorType; 556 static inline NodeType *getEntryNode(SUnit *N) { return N; } 557 static inline ChildIteratorType child_begin(NodeType *N) { 558 return SUnitIterator::begin(N); 559 } 560 static inline ChildIteratorType child_end(NodeType *N) { 561 return SUnitIterator::end(N); 562 } 563 }; 564 565 template <> struct GraphTraits<ScheduleDAG*> : public GraphTraits<SUnit*> { 566 typedef std::vector<SUnit>::iterator nodes_iterator; 567 static nodes_iterator nodes_begin(ScheduleDAG *G) { 568 return G->SUnits.begin(); 569 } 570 static nodes_iterator nodes_end(ScheduleDAG *G) { 571 return G->SUnits.end(); 572 } 573 }; 574 575 /// ScheduleDAGTopologicalSort is a class that computes a topological 576 /// ordering for SUnits and provides methods for dynamically updating 577 /// the ordering as new edges are added. 578 /// 579 /// This allows a very fast implementation of IsReachable, for example. 580 /// 581 class ScheduleDAGTopologicalSort { 582 /// SUnits - A reference to the ScheduleDAG's SUnits. 583 std::vector<SUnit> &SUnits; 584 585 /// Index2Node - Maps topological index to the node number. 586 std::vector<int> Index2Node; 587 /// Node2Index - Maps the node number to its topological index. 588 std::vector<int> Node2Index; 589 /// Visited - a set of nodes visited during a DFS traversal. 590 BitVector Visited; 591 592 /// DFS - make a DFS traversal and mark all nodes affected by the 593 /// edge insertion. These nodes will later get new topological indexes 594 /// by means of the Shift method. 595 void DFS(const SUnit *SU, int UpperBound, bool& HasLoop); 596 597 /// Shift - reassign topological indexes for the nodes in the DAG 598 /// to preserve the topological ordering. 599 void Shift(BitVector& Visited, int LowerBound, int UpperBound); 600 601 /// Allocate - assign the topological index to the node n. 602 void Allocate(int n, int index); 603 604 public: 605 explicit ScheduleDAGTopologicalSort(std::vector<SUnit> &SUnits); 606 607 /// InitDAGTopologicalSorting - create the initial topological 608 /// ordering from the DAG to be scheduled. 609 void InitDAGTopologicalSorting(); 610 611 /// IsReachable - Checks if SU is reachable from TargetSU. 612 bool IsReachable(const SUnit *SU, const SUnit *TargetSU); 613 614 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU 615 /// will create a cycle. 616 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU); 617 618 /// AddPred - Updates the topological ordering to accomodate an edge 619 /// to be added from SUnit X to SUnit Y. 620 void AddPred(SUnit *Y, SUnit *X); 621 622 /// RemovePred - Updates the topological ordering to accomodate an 623 /// an edge to be removed from the specified node N from the predecessors 624 /// of the current node M. 625 void RemovePred(SUnit *M, SUnit *N); 626 627 typedef std::vector<int>::iterator iterator; 628 typedef std::vector<int>::const_iterator const_iterator; 629 iterator begin() { return Index2Node.begin(); } 630 const_iterator begin() const { return Index2Node.begin(); } 631 iterator end() { return Index2Node.end(); } 632 const_iterator end() const { return Index2Node.end(); } 633 634 typedef std::vector<int>::reverse_iterator reverse_iterator; 635 typedef std::vector<int>::const_reverse_iterator const_reverse_iterator; 636 reverse_iterator rbegin() { return Index2Node.rbegin(); } 637 const_reverse_iterator rbegin() const { return Index2Node.rbegin(); } 638 reverse_iterator rend() { return Index2Node.rend(); } 639 const_reverse_iterator rend() const { return Index2Node.rend(); } 640 }; 641} 642 643#endif 644