ScheduleDAG.h revision f7119393a97c2a10757084b6bc186380f8c19a73
1//===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the ScheduleDAG class, which is used as the common 11// base class for instruction schedulers. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_CODEGEN_SCHEDULEDAG_H 16#define LLVM_CODEGEN_SCHEDULEDAG_H 17 18#include "llvm/CodeGen/MachineBasicBlock.h" 19#include "llvm/ADT/DenseMap.h" 20#include "llvm/ADT/BitVector.h" 21#include "llvm/ADT/GraphTraits.h" 22#include "llvm/ADT/SmallVector.h" 23#include "llvm/ADT/PointerIntPair.h" 24 25namespace llvm { 26 struct SUnit; 27 class MachineConstantPool; 28 class MachineFunction; 29 class MachineModuleInfo; 30 class MachineRegisterInfo; 31 class MachineInstr; 32 class TargetRegisterInfo; 33 class ScheduleDAG; 34 class SelectionDAG; 35 class SDNode; 36 class TargetInstrInfo; 37 class TargetInstrDesc; 38 class TargetLowering; 39 class TargetMachine; 40 class TargetRegisterClass; 41 template<class Graph> class GraphWriter; 42 43 /// SDep - Scheduling dependency. This represents one direction of an 44 /// edge in the scheduling DAG. 45 class SDep { 46 public: 47 /// Kind - These are the different kinds of scheduling dependencies. 48 enum Kind { 49 Data, ///< Regular data dependence (aka true-dependence). 50 Anti, ///< A register anti-dependedence (aka WAR). 51 Output, ///< A register output-dependence (aka WAW). 52 Order ///< Any other ordering dependency. 53 }; 54 55 private: 56 /// Dep - A pointer to the depending/depended-on SUnit, and an enum 57 /// indicating the kind of the dependency. 58 PointerIntPair<SUnit *, 2, Kind> Dep; 59 60 /// Contents - A union discriminated by the dependence kind. 61 union { 62 /// Reg - For Data, Anti, and Output dependencies, the associated 63 /// register. For Data dependencies that don't currently have a register 64 /// assigned, this is set to zero. 65 unsigned Reg; 66 67 /// Order - Additional information about Order dependencies. 68 struct { 69 /// isNormalMemory - True if both sides of the dependence 70 /// access memory in non-volatile and fully modeled ways. 71 bool isNormalMemory : 1; 72 73 /// isMustAlias - True if both sides of the dependence are known to 74 /// access the same memory. 75 bool isMustAlias : 1; 76 77 /// isArtificial - True if this is an artificial dependency, meaning 78 /// it is not necessary for program correctness, and may be safely 79 /// deleted if necessary. 80 bool isArtificial : 1; 81 } Order; 82 } Contents; 83 84 /// Latency - The time associated with this edge. Often this is just 85 /// the value of the Latency field of the predecessor, however advanced 86 /// models may provide additional information about specific edges. 87 unsigned Latency; 88 89 public: 90 /// SDep - Construct a null SDep. This is only for use by container 91 /// classes which require default constructors. SUnits may not 92 /// have null SDep edges. 93 SDep() : Dep(0, Data) {} 94 95 /// SDep - Construct an SDep with the specified values. 96 SDep(SUnit *S, Kind kind, unsigned latency = 1, unsigned Reg = 0, 97 bool isNormalMemory = false, bool isMustAlias = false, 98 bool isArtificial = false) 99 : Dep(S, kind), Contents(), Latency(latency) { 100 switch (kind) { 101 case Anti: 102 case Output: 103 assert(Reg != 0 && 104 "SDep::Anti and SDep::Output must use a non-zero Reg!"); 105 // fall through 106 case Data: 107 assert(!isMustAlias && "isMustAlias only applies with SDep::Order!"); 108 assert(!isArtificial && "isArtificial only applies with SDep::Order!"); 109 Contents.Reg = Reg; 110 break; 111 case Order: 112 assert(Reg == 0 && "Reg given for non-register dependence!"); 113 Contents.Order.isNormalMemory = isNormalMemory; 114 Contents.Order.isMustAlias = isMustAlias; 115 Contents.Order.isArtificial = isArtificial; 116 break; 117 } 118 } 119 120 bool operator==(const SDep &Other) const { 121 if (Dep != Other.Dep || Latency != Other.Latency) return false; 122 switch (Dep.getInt()) { 123 case Data: 124 case Anti: 125 case Output: 126 return Contents.Reg == Other.Contents.Reg; 127 case Order: 128 return Contents.Order.isNormalMemory == 129 Other.Contents.Order.isNormalMemory && 130 Contents.Order.isMustAlias == Other.Contents.Order.isMustAlias && 131 Contents.Order.isArtificial == Other.Contents.Order.isArtificial; 132 } 133 assert(0 && "Invalid dependency kind!"); 134 return false; 135 } 136 137 bool operator!=(const SDep &Other) const { 138 return !operator==(Other); 139 } 140 141 /// getLatency - Return the latency value for this edge, which roughly 142 /// means the minimum number of cycles that must elapse between the 143 /// predecessor and the successor, given that they have this edge 144 /// between them. 145 unsigned getLatency() const { 146 return Latency; 147 } 148 149 //// getSUnit - Return the SUnit to which this edge points. 150 SUnit *getSUnit() const { 151 return Dep.getPointer(); 152 } 153 154 //// setSUnit - Assign the SUnit to which this edge points. 155 void setSUnit(SUnit *SU) { 156 Dep.setPointer(SU); 157 } 158 159 /// getKind - Return an enum value representing the kind of the dependence. 160 Kind getKind() const { 161 return Dep.getInt(); 162 } 163 164 /// isCtrl - Shorthand for getKind() != SDep::Data. 165 bool isCtrl() const { 166 return getKind() != Data; 167 } 168 169 /// isNormalMemory - Test if this is an Order dependence between two 170 /// memory accesses where both sides of the dependence access memory 171 /// in non-volatile and fully modeled ways. 172 bool isNormalMemory() const { 173 return getKind() == Order && Contents.Order.isNormalMemory; 174 } 175 176 /// isMustAlias - Test if this is an Order dependence that is marked 177 /// as "must alias", meaning that the SUnits at either end of the edge 178 /// have a memory dependence on a known memory location. 179 bool isMustAlias() const { 180 return getKind() == Order && Contents.Order.isMustAlias; 181 } 182 183 /// isArtificial - Test if this is an Order dependence that is marked 184 /// as "artificial", meaning it isn't necessary for correctness. 185 bool isArtificial() const { 186 return getKind() == Order && Contents.Order.isArtificial; 187 } 188 189 /// isAssignedRegDep - Test if this is a Data dependence that is 190 /// associated with a register. 191 bool isAssignedRegDep() const { 192 return getKind() == Data && Contents.Reg != 0; 193 } 194 195 /// getReg - Return the register associated with this edge. This is 196 /// only valid on Data, Anti, and Output edges. On Data edges, this 197 /// value may be zero, meaning there is no associated register. 198 unsigned getReg() const { 199 assert((getKind() == Data || getKind() == Anti || getKind() == Output) && 200 "getReg called on non-register dependence edge!"); 201 return Contents.Reg; 202 } 203 204 /// setReg - Assign the associated register for this edge. This is 205 /// only valid on Data, Anti, and Output edges. On Anti and Output 206 /// edges, this value must not be zero. On Data edges, the value may 207 /// be zero, which would mean that no specific register is associated 208 /// with this edge. 209 void setReg(unsigned Reg) { 210 assert((getKind() == Data || getKind() == Anti || getKind() == Output) && 211 "setReg called on non-register dependence edge!"); 212 assert((getKind() != Anti || Reg != 0) && 213 "SDep::Anti edge cannot use the zero register!"); 214 assert((getKind() != Output || Reg != 0) && 215 "SDep::Output edge cannot use the zero register!"); 216 Contents.Reg = Reg; 217 } 218 }; 219 220 /// SUnit - Scheduling unit. This is a node in the scheduling DAG. 221 struct SUnit { 222 private: 223 SDNode *Node; // Representative node. 224 MachineInstr *Instr; // Alternatively, a MachineInstr. 225 public: 226 SUnit *OrigNode; // If not this, the node from which 227 // this node was cloned. 228 229 // Preds/Succs - The SUnits before/after us in the graph. The boolean value 230 // is true if the edge is a token chain edge, false if it is a value edge. 231 SmallVector<SDep, 4> Preds; // All sunit predecessors. 232 SmallVector<SDep, 4> Succs; // All sunit successors. 233 234 typedef SmallVector<SDep, 4>::iterator pred_iterator; 235 typedef SmallVector<SDep, 4>::iterator succ_iterator; 236 typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator; 237 typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator; 238 239 unsigned NodeNum; // Entry # of node in the node vector. 240 unsigned NodeQueueId; // Queue id of node. 241 unsigned short Latency; // Node latency. 242 short NumPreds; // # of SDep::Data preds. 243 short NumSuccs; // # of SDep::Data sucss. 244 short NumPredsLeft; // # of preds not scheduled. 245 short NumSuccsLeft; // # of succs not scheduled. 246 bool isTwoAddress : 1; // Is a two-address instruction. 247 bool isCommutable : 1; // Is a commutable instruction. 248 bool hasPhysRegDefs : 1; // Has physreg defs that are being used. 249 bool isPending : 1; // True once pending. 250 bool isAvailable : 1; // True once available. 251 bool isScheduled : 1; // True once scheduled. 252 bool isScheduleHigh : 1; // True if preferable to schedule high. 253 bool isCloned : 1; // True if this node has been cloned. 254 private: 255 bool isDepthCurrent : 1; // True if Depth is current. 256 bool isHeightCurrent : 1; // True if Height is current. 257 unsigned Depth; // Node depth. 258 unsigned Height; // Node height. 259 public: 260 const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null. 261 const TargetRegisterClass *CopySrcRC; 262 263 /// SUnit - Construct an SUnit for pre-regalloc scheduling to represent 264 /// an SDNode and any nodes flagged to it. 265 SUnit(SDNode *node, unsigned nodenum) 266 : Node(node), Instr(0), OrigNode(0), NodeNum(nodenum), NodeQueueId(0), 267 Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0), 268 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false), 269 isPending(false), isAvailable(false), isScheduled(false), 270 isScheduleHigh(false), isCloned(false), 271 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), 272 CopyDstRC(NULL), CopySrcRC(NULL) {} 273 274 /// SUnit - Construct an SUnit for post-regalloc scheduling to represent 275 /// a MachineInstr. 276 SUnit(MachineInstr *instr, unsigned nodenum) 277 : Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum), NodeQueueId(0), 278 Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0), 279 isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false), 280 isPending(false), isAvailable(false), isScheduled(false), 281 isScheduleHigh(false), isCloned(false), 282 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), 283 CopyDstRC(NULL), CopySrcRC(NULL) {} 284 285 /// setNode - Assign the representative SDNode for this SUnit. 286 /// This may be used during pre-regalloc scheduling. 287 void setNode(SDNode *N) { 288 assert(!Instr && "Setting SDNode of SUnit with MachineInstr!"); 289 Node = N; 290 } 291 292 /// getNode - Return the representative SDNode for this SUnit. 293 /// This may be used during pre-regalloc scheduling. 294 SDNode *getNode() const { 295 assert(!Instr && "Reading SDNode of SUnit with MachineInstr!"); 296 return Node; 297 } 298 299 /// setInstr - Assign the instruction for the SUnit. 300 /// This may be used during post-regalloc scheduling. 301 void setInstr(MachineInstr *MI) { 302 assert(!Node && "Setting MachineInstr of SUnit with SDNode!"); 303 Instr = MI; 304 } 305 306 /// getInstr - Return the representative MachineInstr for this SUnit. 307 /// This may be used during post-regalloc scheduling. 308 MachineInstr *getInstr() const { 309 assert(!Node && "Reading MachineInstr of SUnit with SDNode!"); 310 return Instr; 311 } 312 313 /// addPred - This adds the specified edge as a pred of the current node if 314 /// not already. It also adds the current node as a successor of the 315 /// specified node. 316 void addPred(const SDep &D); 317 318 /// removePred - This removes the specified edge as a pred of the current 319 /// node if it exists. It also removes the current node as a successor of 320 /// the specified node. 321 void removePred(const SDep &D); 322 323 /// getDepth - Return the depth of this node, which is the length of the 324 /// maximum path up to any node with has no predecessors. 325 unsigned getDepth() const { 326 if (!isDepthCurrent) const_cast<SUnit *>(this)->ComputeDepth(); 327 return Depth; 328 } 329 330 /// getHeight - Return the height of this node, which is the length of the 331 /// maximum path down to any node with has no successors. 332 unsigned getHeight() const { 333 if (!isHeightCurrent) const_cast<SUnit *>(this)->ComputeHeight(); 334 return Height; 335 } 336 337 /// setDepthToAtLeast - If NewDepth is greater than this node's depth 338 /// value, set it to be the new depth value. This also recursively 339 /// marks successor nodes dirty. 340 void setDepthToAtLeast(unsigned NewDepth); 341 342 /// setDepthToAtLeast - If NewDepth is greater than this node's depth 343 /// value, set it to be the new height value. This also recursively 344 /// marks predecessor nodes dirty. 345 void setHeightToAtLeast(unsigned NewHeight); 346 347 /// setDepthDirty - Set a flag in this node to indicate that its 348 /// stored Depth value will require recomputation the next time 349 /// getDepth() is called. 350 void setDepthDirty(); 351 352 /// setHeightDirty - Set a flag in this node to indicate that its 353 /// stored Height value will require recomputation the next time 354 /// getHeight() is called. 355 void setHeightDirty(); 356 357 /// isPred - Test if node N is a predecessor of this node. 358 bool isPred(SUnit *N) { 359 for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i) 360 if (Preds[i].getSUnit() == N) 361 return true; 362 return false; 363 } 364 365 /// isSucc - Test if node N is a successor of this node. 366 bool isSucc(SUnit *N) { 367 for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i) 368 if (Succs[i].getSUnit() == N) 369 return true; 370 return false; 371 } 372 373 void dump(const ScheduleDAG *G) const; 374 void dumpAll(const ScheduleDAG *G) const; 375 void print(raw_ostream &O, const ScheduleDAG *G) const; 376 377 private: 378 void ComputeDepth(); 379 void ComputeHeight(); 380 }; 381 382 //===--------------------------------------------------------------------===// 383 /// SchedulingPriorityQueue - This interface is used to plug different 384 /// priorities computation algorithms into the list scheduler. It implements 385 /// the interface of a standard priority queue, where nodes are inserted in 386 /// arbitrary order and returned in priority order. The computation of the 387 /// priority and the representation of the queue are totally up to the 388 /// implementation to decide. 389 /// 390 class SchedulingPriorityQueue { 391 public: 392 virtual ~SchedulingPriorityQueue() {} 393 394 virtual void initNodes(std::vector<SUnit> &SUnits) = 0; 395 virtual void addNode(const SUnit *SU) = 0; 396 virtual void updateNode(const SUnit *SU) = 0; 397 virtual void releaseState() = 0; 398 399 virtual unsigned size() const = 0; 400 virtual bool empty() const = 0; 401 virtual void push(SUnit *U) = 0; 402 403 virtual void push_all(const std::vector<SUnit *> &Nodes) = 0; 404 virtual SUnit *pop() = 0; 405 406 virtual void remove(SUnit *SU) = 0; 407 408 /// ScheduledNode - As each node is scheduled, this method is invoked. This 409 /// allows the priority function to adjust the priority of related 410 /// unscheduled nodes, for example. 411 /// 412 virtual void ScheduledNode(SUnit *) {} 413 414 virtual void UnscheduledNode(SUnit *) {} 415 }; 416 417 class ScheduleDAG { 418 public: 419 SelectionDAG *DAG; // DAG of the current basic block 420 MachineBasicBlock *BB; // Current basic block 421 MachineBasicBlock::iterator Begin; // The beginning of the range to be scheduled. 422 MachineBasicBlock::iterator End; // The end of the range to be scheduled. 423 const TargetMachine &TM; // Target processor 424 const TargetInstrInfo *TII; // Target instruction information 425 const TargetRegisterInfo *TRI; // Target processor register info 426 TargetLowering *TLI; // Target lowering info 427 MachineFunction &MF; // Machine function 428 MachineRegisterInfo &MRI; // Virtual/real register map 429 MachineConstantPool *ConstPool; // Target constant pool 430 std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s 431 // represent noop instructions. 432 std::vector<SUnit> SUnits; // The scheduling units. 433 434 explicit ScheduleDAG(MachineFunction &mf); 435 436 virtual ~ScheduleDAG(); 437 438 /// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered 439 /// using 'dot'. 440 /// 441 void viewGraph(); 442 443 /// Run - perform scheduling. 444 /// 445 void Run(SelectionDAG *DAG, MachineBasicBlock *MBB, 446 MachineBasicBlock::iterator Begin, 447 MachineBasicBlock::iterator End); 448 449 /// BuildSchedGraph - Build SUnits and set up their Preds and Succs 450 /// to form the scheduling dependency graph. 451 /// 452 virtual void BuildSchedGraph() = 0; 453 454 /// ComputeLatency - Compute node latency. 455 /// 456 virtual void ComputeLatency(SUnit *SU) = 0; 457 458 protected: 459 /// EmitNoop - Emit a noop instruction. 460 /// 461 void EmitNoop(); 462 463 public: 464 virtual MachineBasicBlock *EmitSchedule() = 0; 465 466 void dumpSchedule() const; 467 468 /// Schedule - Order nodes according to selected style, filling 469 /// in the Sequence member. 470 /// 471 virtual void Schedule() = 0; 472 473 virtual void dumpNode(const SUnit *SU) const = 0; 474 475 /// getGraphNodeLabel - Return a label for an SUnit node in a visualization 476 /// of the ScheduleDAG. 477 virtual std::string getGraphNodeLabel(const SUnit *SU) const = 0; 478 479 /// addCustomGraphFeatures - Add custom features for a visualization of 480 /// the ScheduleDAG. 481 virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {} 482 483#ifndef NDEBUG 484 /// VerifySchedule - Verify that all SUnits were scheduled and that 485 /// their state is consistent. 486 void VerifySchedule(bool isBottomUp); 487#endif 488 489 protected: 490 void AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO); 491 492 void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap); 493 494 /// ForceUnitLatencies - Return true if all scheduling edges should be given a 495 /// latency value of one. The default is to return false; schedulers may 496 /// override this as needed. 497 virtual bool ForceUnitLatencies() const { return false; } 498 499 private: 500 /// EmitLiveInCopy - Emit a copy for a live in physical register. If the 501 /// physical register has only a single copy use, then coalesced the copy 502 /// if possible. 503 void EmitLiveInCopy(MachineBasicBlock *MBB, 504 MachineBasicBlock::iterator &InsertPos, 505 unsigned VirtReg, unsigned PhysReg, 506 const TargetRegisterClass *RC, 507 DenseMap<MachineInstr*, unsigned> &CopyRegMap); 508 509 /// EmitLiveInCopies - If this is the first basic block in the function, 510 /// and if it has live ins that need to be copied into vregs, emit the 511 /// copies into the top of the block. 512 void EmitLiveInCopies(MachineBasicBlock *MBB); 513 }; 514 515 class SUnitIterator : public forward_iterator<SUnit, ptrdiff_t> { 516 SUnit *Node; 517 unsigned Operand; 518 519 SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {} 520 public: 521 bool operator==(const SUnitIterator& x) const { 522 return Operand == x.Operand; 523 } 524 bool operator!=(const SUnitIterator& x) const { return !operator==(x); } 525 526 const SUnitIterator &operator=(const SUnitIterator &I) { 527 assert(I.Node == Node && "Cannot assign iterators to two different nodes!"); 528 Operand = I.Operand; 529 return *this; 530 } 531 532 pointer operator*() const { 533 return Node->Preds[Operand].getSUnit(); 534 } 535 pointer operator->() const { return operator*(); } 536 537 SUnitIterator& operator++() { // Preincrement 538 ++Operand; 539 return *this; 540 } 541 SUnitIterator operator++(int) { // Postincrement 542 SUnitIterator tmp = *this; ++*this; return tmp; 543 } 544 545 static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); } 546 static SUnitIterator end (SUnit *N) { 547 return SUnitIterator(N, (unsigned)N->Preds.size()); 548 } 549 550 unsigned getOperand() const { return Operand; } 551 const SUnit *getNode() const { return Node; } 552 /// isCtrlDep - Test if this is not an SDep::Data dependence. 553 bool isCtrlDep() const { 554 return getSDep().isCtrl(); 555 } 556 bool isArtificialDep() const { 557 return getSDep().isArtificial(); 558 } 559 const SDep &getSDep() const { 560 return Node->Preds[Operand]; 561 } 562 }; 563 564 template <> struct GraphTraits<SUnit*> { 565 typedef SUnit NodeType; 566 typedef SUnitIterator ChildIteratorType; 567 static inline NodeType *getEntryNode(SUnit *N) { return N; } 568 static inline ChildIteratorType child_begin(NodeType *N) { 569 return SUnitIterator::begin(N); 570 } 571 static inline ChildIteratorType child_end(NodeType *N) { 572 return SUnitIterator::end(N); 573 } 574 }; 575 576 template <> struct GraphTraits<ScheduleDAG*> : public GraphTraits<SUnit*> { 577 typedef std::vector<SUnit>::iterator nodes_iterator; 578 static nodes_iterator nodes_begin(ScheduleDAG *G) { 579 return G->SUnits.begin(); 580 } 581 static nodes_iterator nodes_end(ScheduleDAG *G) { 582 return G->SUnits.end(); 583 } 584 }; 585 586 /// ScheduleDAGTopologicalSort is a class that computes a topological 587 /// ordering for SUnits and provides methods for dynamically updating 588 /// the ordering as new edges are added. 589 /// 590 /// This allows a very fast implementation of IsReachable, for example. 591 /// 592 class ScheduleDAGTopologicalSort { 593 /// SUnits - A reference to the ScheduleDAG's SUnits. 594 std::vector<SUnit> &SUnits; 595 596 /// Index2Node - Maps topological index to the node number. 597 std::vector<int> Index2Node; 598 /// Node2Index - Maps the node number to its topological index. 599 std::vector<int> Node2Index; 600 /// Visited - a set of nodes visited during a DFS traversal. 601 BitVector Visited; 602 603 /// DFS - make a DFS traversal and mark all nodes affected by the 604 /// edge insertion. These nodes will later get new topological indexes 605 /// by means of the Shift method. 606 void DFS(const SUnit *SU, int UpperBound, bool& HasLoop); 607 608 /// Shift - reassign topological indexes for the nodes in the DAG 609 /// to preserve the topological ordering. 610 void Shift(BitVector& Visited, int LowerBound, int UpperBound); 611 612 /// Allocate - assign the topological index to the node n. 613 void Allocate(int n, int index); 614 615 public: 616 explicit ScheduleDAGTopologicalSort(std::vector<SUnit> &SUnits); 617 618 /// InitDAGTopologicalSorting - create the initial topological 619 /// ordering from the DAG to be scheduled. 620 void InitDAGTopologicalSorting(); 621 622 /// IsReachable - Checks if SU is reachable from TargetSU. 623 bool IsReachable(const SUnit *SU, const SUnit *TargetSU); 624 625 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU 626 /// will create a cycle. 627 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU); 628 629 /// AddPred - Updates the topological ordering to accomodate an edge 630 /// to be added from SUnit X to SUnit Y. 631 void AddPred(SUnit *Y, SUnit *X); 632 633 /// RemovePred - Updates the topological ordering to accomodate an 634 /// an edge to be removed from the specified node N from the predecessors 635 /// of the current node M. 636 void RemovePred(SUnit *M, SUnit *N); 637 638 typedef std::vector<int>::iterator iterator; 639 typedef std::vector<int>::const_iterator const_iterator; 640 iterator begin() { return Index2Node.begin(); } 641 const_iterator begin() const { return Index2Node.begin(); } 642 iterator end() { return Index2Node.end(); } 643 const_iterator end() const { return Index2Node.end(); } 644 645 typedef std::vector<int>::reverse_iterator reverse_iterator; 646 typedef std::vector<int>::const_reverse_iterator const_reverse_iterator; 647 reverse_iterator rbegin() { return Index2Node.rbegin(); } 648 const_reverse_iterator rbegin() const { return Index2Node.rbegin(); } 649 reverse_iterator rend() { return Index2Node.rend(); } 650 const_reverse_iterator rend() const { return Index2Node.rend(); } 651 }; 652} 653 654#endif 655