1a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng//=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===// 2a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng// 3a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng// The LLVM Compiler Infrastructure 4a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng// 5a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng// This file is distributed under the University of Illinois Open Source 6a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng// License. See LICENSE.TXT for details. 7a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng// 8a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng//===----------------------------------------------------------------------===// 9a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng// 10a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng// This file describes an abstract interface used to get information about a 11a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng// target machines register file. This information is used for a variety of 12a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng// purposed, especially register allocation. 13a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng// 14a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng//===----------------------------------------------------------------------===// 15a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng 16a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng#ifndef LLVM_MC_MCREGISTERINFO_H 17a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng#define LLVM_MC_MCREGISTERINFO_H 18a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng 190e6a052331f674dd70e28af41f654a7874405eabEvan Cheng#include "llvm/ADT/DenseMap.h" 2050bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper#include "llvm/Support/ErrorHandling.h" 21a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng#include <cassert> 22a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng 23a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Chengnamespace llvm { 24a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng 25e26e8a64ab37e98c69801ac2028b187773bc1d1fJakob Stoklund Olesen/// An unsigned integer type large enough to represent all physical registers, 26e26e8a64ab37e98c69801ac2028b187773bc1d1fJakob Stoklund Olesen/// but not necessarily virtual registers. 27e26e8a64ab37e98c69801ac2028b187773bc1d1fJakob Stoklund Olesentypedef uint16_t MCPhysReg; 28e26e8a64ab37e98c69801ac2028b187773bc1d1fJakob Stoklund Olesen 29a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer/// MCRegisterClass - Base class of TargetRegisterClass. 30a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramerclass MCRegisterClass { 31a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramerpublic: 32e26e8a64ab37e98c69801ac2028b187773bc1d1fJakob Stoklund Olesen typedef const MCPhysReg* iterator; 33e26e8a64ab37e98c69801ac2028b187773bc1d1fJakob Stoklund Olesen typedef const MCPhysReg* const_iterator; 3490a468c424f7d0a85b3dc783634106d9a46d6688Benjamin Kramer 35f3e3783012dc7875ed37be8aaaefd96f98454781Craig Topper const iterator RegsBegin; 36b6632ba380cf624e60fe16b03d6e21b05dd07724Craig Topper const uint8_t *const RegSet; 3737ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines const uint32_t NameIdx; 38aff18aee5632d8cb5ed7e299df4cb451bf12c834Craig Topper const uint16_t RegsSize; 39aff18aee5632d8cb5ed7e299df4cb451bf12c834Craig Topper const uint16_t RegSetSize; 40aff18aee5632d8cb5ed7e299df4cb451bf12c834Craig Topper const uint16_t ID; 41aff18aee5632d8cb5ed7e299df4cb451bf12c834Craig Topper const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes 4252b89dd303424582d054e18417099f3a7e343b41Craig Topper const int8_t CopyCost; 4352b89dd303424582d054e18417099f3a7e343b41Craig Topper const bool Allocatable; 44a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer 45a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer /// getID() - Return the register class ID number. 46a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer /// 47a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer unsigned getID() const { return ID; } 48a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer 49a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer /// begin/end - Return all of the registers in this class. 50a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer /// 51a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer iterator begin() const { return RegsBegin; } 52f3e3783012dc7875ed37be8aaaefd96f98454781Craig Topper iterator end() const { return RegsBegin + RegsSize; } 53a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer 54a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer /// getNumRegs - Return the number of registers in this class. 55a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer /// 56f3e3783012dc7875ed37be8aaaefd96f98454781Craig Topper unsigned getNumRegs() const { return RegsSize; } 57a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer 58a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer /// getRegister - Return the specified register in the class. 59a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer /// 60a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer unsigned getRegister(unsigned i) const { 61a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer assert(i < getNumRegs() && "Register number out of range!"); 62a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer return RegsBegin[i]; 63a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer } 64a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer 65a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer /// contains - Return true if the specified register is included in this 66a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer /// register class. This does not include virtual registers. 67a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer bool contains(unsigned Reg) const { 689df8567548e15c6cd91e8a5851784574c4f09528Benjamin Kramer unsigned InByte = Reg % 8; 699df8567548e15c6cd91e8a5851784574c4f09528Benjamin Kramer unsigned Byte = Reg / 8; 7059a4f9af0a2e94ec04840a066251eca34bf3e3f8Benjamin Kramer if (Byte >= RegSetSize) 719df8567548e15c6cd91e8a5851784574c4f09528Benjamin Kramer return false; 729df8567548e15c6cd91e8a5851784574c4f09528Benjamin Kramer return (RegSet[Byte] & (1 << InByte)) != 0; 73a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer } 74a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer 75a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer /// contains - Return true if both registers are in this class. 76a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer bool contains(unsigned Reg1, unsigned Reg2) const { 77a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer return contains(Reg1) && contains(Reg2); 78a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer } 79a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer 80a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer /// getSize - Return the size of the register in bytes, which is also the size 81a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer /// of a stack slot allocated to hold a spilled copy of this register. 82a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer unsigned getSize() const { return RegSize; } 83a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer 84a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer /// getAlignment - Return the minimum required alignment for a register of 85a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer /// this class. 86a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer unsigned getAlignment() const { return Alignment; } 87a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer 88a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer /// getCopyCost - Return the cost of copying a value between two registers in 89a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer /// this class. A negative number means the register class is very expensive 90a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer /// to copy e.g. status flag register classes. 91a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer int getCopyCost() const { return CopyCost; } 92a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer 93a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer /// isAllocatable - Return true if this register class may be used to create 94a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer /// virtual registers. 95a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer bool isAllocatable() const { return Allocatable; } 96a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer}; 97a50c175fe3c7a3034df18747cfacb3b153c493c8Benjamin Kramer 982275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier/// MCRegisterDesc - This record contains information about a particular 992275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier/// register. The SubRegs field is a zero terminated array of registers that 1002275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier/// are sub-registers of the specific register, e.g. AL, AH are sub-registers 1012275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier/// of AX. The SuperRegs field is a zero terminated array of registers that are 1022275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier/// super-registers of the specific register, e.g. RAX, EAX, are 1032275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier/// super-registers of AX. 104a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng/// 105f5fa52ed064098be7130aa4ec1236037907ce3faEvan Chengstruct MCRegisterDesc { 106d5ce3ffa67698b9d21f58011f370a210a214d301Jakob Stoklund Olesen uint32_t Name; // Printable name for the reg (for debugging) 107d5ce3ffa67698b9d21f58011f370a210a214d301Jakob Stoklund Olesen uint32_t SubRegs; // Sub-register set, described above 108d5ce3ffa67698b9d21f58011f370a210a214d301Jakob Stoklund Olesen uint32_t SuperRegs; // Super-register set, described above 109f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen 1100371cd8b1c0d2101295ca9381a0b437e1f2d8fa2Jakob Stoklund Olesen // Offset into MCRI::SubRegIndices of a list of sub-register indices for each 1110371cd8b1c0d2101295ca9381a0b437e1f2d8fa2Jakob Stoklund Olesen // sub-register in SubRegs. 1120371cd8b1c0d2101295ca9381a0b437e1f2d8fa2Jakob Stoklund Olesen uint32_t SubRegIndices; 1130371cd8b1c0d2101295ca9381a0b437e1f2d8fa2Jakob Stoklund Olesen 114f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen // RegUnits - Points to the list of register units. The low 4 bits holds the 115f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator. 116f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen uint32_t RegUnits; 117ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 118ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines /// Index into list with lane mask sequences. The sequence contains a lanemask 119ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines /// for every register unit. 120ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines uint16_t RegUnitLaneMasks; 121a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng}; 122a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng 123a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng/// MCRegisterInfo base class - We assume that the target defines a static 1245e6b4605bd620a864055276a6d454e5a18f9fee8Evan Cheng/// array of MCRegisterDesc objects that represent all of the machine 125a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng/// registers that the target has. As such, we simply have to track a pointer 126a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng/// to this array so that we can turn register number into a register 127a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng/// descriptor. 128a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng/// 129f5fa52ed064098be7130aa4ec1236037907ce3faEvan Cheng/// Note this class is designed to be a base class of TargetRegisterInfo, which 130f5fa52ed064098be7130aa4ec1236037907ce3faEvan Cheng/// is the interface used by codegen. However, specific targets *should never* 131f5fa52ed064098be7130aa4ec1236037907ce3faEvan Cheng/// specialize this class. MCRegisterInfo should only contain getters to access 132f5fa52ed064098be7130aa4ec1236037907ce3faEvan Cheng/// TableGen generated physical register data. It must not be extended with 133f5fa52ed064098be7130aa4ec1236037907ce3faEvan Cheng/// virtual methods. 134f5fa52ed064098be7130aa4ec1236037907ce3faEvan Cheng/// 135a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Chengclass MCRegisterInfo { 1368ca9a862038e8c4e9a2ca73b3b75e1be3425155fBenjamin Kramerpublic: 1378ca9a862038e8c4e9a2ca73b3b75e1be3425155fBenjamin Kramer typedef const MCRegisterClass *regclass_iterator; 138243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer 139243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be 140243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer /// performed with a binary search. 141243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer struct DwarfLLVMRegPair { 142243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer unsigned FromReg; 143243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer unsigned ToReg; 144243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer 14532d1774d45532508c9c76fa8e4dad9454ec50656Benjamin Kramer bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; } 146243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer }; 147bed23081860275c79137f65d592920e7991b8198Ahmed Bougacha 148bed23081860275c79137f65d592920e7991b8198Ahmed Bougacha /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg 149bed23081860275c79137f65d592920e7991b8198Ahmed Bougacha /// index, -1 in any being invalid. 150bed23081860275c79137f65d592920e7991b8198Ahmed Bougacha struct SubRegCoveredBits { 151bed23081860275c79137f65d592920e7991b8198Ahmed Bougacha uint16_t Offset; 152bed23081860275c79137f65d592920e7991b8198Ahmed Bougacha uint16_t Size; 153bed23081860275c79137f65d592920e7991b8198Ahmed Bougacha }; 154a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Chengprivate: 1550e6a052331f674dd70e28af41f654a7874405eabEvan Cheng const MCRegisterDesc *Desc; // Pointer to the descriptor array 1560e6a052331f674dd70e28af41f654a7874405eabEvan Cheng unsigned NumRegs; // Number of entries in the array 1570e6a052331f674dd70e28af41f654a7874405eabEvan Cheng unsigned RAReg; // Return address register 158fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach unsigned PCReg; // Program counter register 1598ca9a862038e8c4e9a2ca73b3b75e1be3425155fBenjamin Kramer const MCRegisterClass *Classes; // Pointer to the regclass array 1608ca9a862038e8c4e9a2ca73b3b75e1be3425155fBenjamin Kramer unsigned NumClasses; // Number of entries in the array 161f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen unsigned NumRegUnits; // Number of regunits. 162dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table. 163e26e8a64ab37e98c69801ac2028b187773bc1d1fJakob Stoklund Olesen const MCPhysReg *DiffLists; // Pointer to the difflists array 164ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines const unsigned *RegUnitMaskSequences; // Pointer to lane mask sequences 165ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // for register units. 166d5ce3ffa67698b9d21f58011f370a210a214d301Jakob Stoklund Olesen const char *RegStrings; // Pointer to the string table. 16737ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines const char *RegClassStrings; // Pointer to the class strings. 168b6632ba380cf624e60fe16b03d6e21b05dd07724Craig Topper const uint16_t *SubRegIndices; // Pointer to the subreg lookup 169b3acdcc00c9dfb01663780e858e586cc5f04423fJim Grosbach // array. 170bed23081860275c79137f65d592920e7991b8198Ahmed Bougacha const SubRegCoveredBits *SubRegIdxRanges; // Pointer to the subreg covered 171bed23081860275c79137f65d592920e7991b8198Ahmed Bougacha // bit ranges array. 172b3acdcc00c9dfb01663780e858e586cc5f04423fJim Grosbach unsigned NumSubRegIndices; // Number of subreg indices. 1730ee07e013095e8c298fbcc5203e0bc9f334e15e1Jim Grosbach const uint16_t *RegEncodingTable; // Pointer to array of register 1740ee07e013095e8c298fbcc5203e0bc9f334e15e1Jim Grosbach // encodings. 175243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer 176243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer unsigned L2DwarfRegsSize; 177243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer unsigned EHL2DwarfRegsSize; 178243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer unsigned Dwarf2LRegsSize; 179243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer unsigned EHDwarf2LRegsSize; 180243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping 181243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH 182243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping 183243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH 1840e6a052331f674dd70e28af41f654a7874405eabEvan Cheng DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping 185de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar DenseMap<unsigned, int> L2CVRegs; // LLVM to CV regs mapping 186a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng 187209cdc2999208e9783349e970bd96fc37557fd97Jakob Stoklund Olesenpublic: 188f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen /// DiffListIterator - Base iterator class that can traverse the 189f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen /// differentially encoded register and regunit lists in DiffLists. 190f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen /// Don't use this class directly, use one of the specialized sub-classes 191f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen /// defined below. 192f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen class DiffListIterator { 193f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen uint16_t Val; 194e26e8a64ab37e98c69801ac2028b187773bc1d1fJakob Stoklund Olesen const MCPhysReg *List; 195f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen 196f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen protected: 197f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen /// Create an invalid iterator. Call init() to point to something useful. 198dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines DiffListIterator() : Val(0), List(nullptr) {} 199f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen 200f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen /// init - Point the iterator to InitVal, decoding subsequent values from 201f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen /// DiffList. The iterator will initially point to InitVal, sub-classes are 202f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen /// responsible for skipping the seed value if it is not part of the list. 203e26e8a64ab37e98c69801ac2028b187773bc1d1fJakob Stoklund Olesen void init(MCPhysReg InitVal, const MCPhysReg *DiffList) { 204f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen Val = InitVal; 205f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen List = DiffList; 206f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen } 207f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen 208f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen /// advance - Move to the next list position, return the applied 209f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen /// differential. This function does not detect the end of the list, that 210f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen /// is the caller's responsibility (by checking for a 0 return value). 211f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen unsigned advance() { 212f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen assert(isValid() && "Cannot move off the end of the list."); 213e26e8a64ab37e98c69801ac2028b187773bc1d1fJakob Stoklund Olesen MCPhysReg D = *List++; 214f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen Val += D; 215f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen return D; 216f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen } 217f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen 218f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen public: 219f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen 220f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen /// isValid - returns true if this iterator is not yet at the end. 221f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen bool isValid() const { return List; } 222f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen 223f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen /// Dereference the iterator to get the value at the current position. 224f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen unsigned operator*() const { return Val; } 225f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen 226f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen /// Pre-increment to move to the next position. 227f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen void operator++() { 228f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen // The end of the list is encoded as a 0 differential. 229f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen if (!advance()) 230dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines List = nullptr; 231f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen } 232f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen }; 233f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen 234303c909d5bb014fbeec395090eb467d724969195Jakob Stoklund Olesen // These iterators are allowed to sub-class DiffListIterator and access 235303c909d5bb014fbeec395090eb467d724969195Jakob Stoklund Olesen // internal list pointers. 236cd00ef033cf944fc96a0d06ffcf49cd805fc4ee3Jakob Stoklund Olesen friend class MCSubRegIterator; 237ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines friend class MCSubRegIndexIterator; 238cd00ef033cf944fc96a0d06ffcf49cd805fc4ee3Jakob Stoklund Olesen friend class MCSuperRegIterator; 239f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen friend class MCRegUnitIterator; 240ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines friend class MCRegUnitMaskIterator; 241f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen friend class MCRegUnitRootIterator; 242f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen 24339758cd55d994c0899acfb365d717e9f877ca001Jim Grosbach /// \brief Initialize MCRegisterInfo, called by TableGen 244a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng /// auto-generated routines. *DO NOT USE*. 2458ca9a862038e8c4e9a2ca73b3b75e1be3425155fBenjamin Kramer void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, 246fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach unsigned PC, 247f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen const MCRegisterClass *C, unsigned NC, 248dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const MCPhysReg (*RURoots)[2], 249f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen unsigned NRU, 250e26e8a64ab37e98c69801ac2028b187773bc1d1fJakob Stoklund Olesen const MCPhysReg *DL, 251ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines const unsigned *RUMS, 252d5ce3ffa67698b9d21f58011f370a210a214d301Jakob Stoklund Olesen const char *Strings, 25337ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines const char *ClassStrings, 254b6632ba380cf624e60fe16b03d6e21b05dd07724Craig Topper const uint16_t *SubIndices, 2550ee07e013095e8c298fbcc5203e0bc9f334e15e1Jim Grosbach unsigned NumIndices, 256bed23081860275c79137f65d592920e7991b8198Ahmed Bougacha const SubRegCoveredBits *SubIdxRanges, 2570ee07e013095e8c298fbcc5203e0bc9f334e15e1Jim Grosbach const uint16_t *RET) { 258a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng Desc = D; 259a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng NumRegs = NR; 2600e6a052331f674dd70e28af41f654a7874405eabEvan Cheng RAReg = RA; 261fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach PCReg = PC; 2628ca9a862038e8c4e9a2ca73b3b75e1be3425155fBenjamin Kramer Classes = C; 263f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen DiffLists = DL; 264ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines RegUnitMaskSequences = RUMS; 265d5ce3ffa67698b9d21f58011f370a210a214d301Jakob Stoklund Olesen RegStrings = Strings; 26637ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines RegClassStrings = ClassStrings; 2678ca9a862038e8c4e9a2ca73b3b75e1be3425155fBenjamin Kramer NumClasses = NC; 268f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen RegUnitRoots = RURoots; 269f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen NumRegUnits = NRU; 270b3acdcc00c9dfb01663780e858e586cc5f04423fJim Grosbach SubRegIndices = SubIndices; 271b3acdcc00c9dfb01663780e858e586cc5f04423fJim Grosbach NumSubRegIndices = NumIndices; 272bed23081860275c79137f65d592920e7991b8198Ahmed Bougacha SubRegIdxRanges = SubIdxRanges; 2730ee07e013095e8c298fbcc5203e0bc9f334e15e1Jim Grosbach RegEncodingTable = RET; 2740e6a052331f674dd70e28af41f654a7874405eabEvan Cheng } 2750e6a052331f674dd70e28af41f654a7874405eabEvan Cheng 27639758cd55d994c0899acfb365d717e9f877ca001Jim Grosbach /// \brief Used to initialize LLVM register to Dwarf 2770e6a052331f674dd70e28af41f654a7874405eabEvan Cheng /// register number mapping. Called by TableGen auto-generated routines. 2780e6a052331f674dd70e28af41f654a7874405eabEvan Cheng /// *DO NOT USE*. 279243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size, 280243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer bool isEH) { 281243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer if (isEH) { 282243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer EHL2DwarfRegs = Map; 283243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer EHL2DwarfRegsSize = Size; 284243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer } else { 285243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer L2DwarfRegs = Map; 286243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer L2DwarfRegsSize = Size; 287243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer } 288a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng } 289492be647722fc2f372e650ce4a5d9e10171dbe0eJim Grosbach 29039758cd55d994c0899acfb365d717e9f877ca001Jim Grosbach /// \brief Used to initialize Dwarf register to LLVM 2910e6a052331f674dd70e28af41f654a7874405eabEvan Cheng /// register number mapping. Called by TableGen auto-generated routines. 2920e6a052331f674dd70e28af41f654a7874405eabEvan Cheng /// *DO NOT USE*. 293243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size, 294243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer bool isEH) { 295243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer if (isEH) { 296243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer EHDwarf2LRegs = Map; 297243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer EHDwarf2LRegsSize = Size; 298243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer } else { 299243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer Dwarf2LRegs = Map; 300243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer Dwarf2LRegsSize = Size; 301243018ffcf764e4dde2968f909f4a2e578aafe86Benjamin Kramer } 3020e6a052331f674dd70e28af41f654a7874405eabEvan Cheng } 303492be647722fc2f372e650ce4a5d9e10171dbe0eJim Grosbach 3040e6a052331f674dd70e28af41f654a7874405eabEvan Cheng /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register 3050e6a052331f674dd70e28af41f654a7874405eabEvan Cheng /// number mapping. By default the SEH register number is just the same 3060e6a052331f674dd70e28af41f654a7874405eabEvan Cheng /// as the LLVM register number. 3070e6a052331f674dd70e28af41f654a7874405eabEvan Cheng /// FIXME: TableGen these numbers. Currently this requires target specific 3080e6a052331f674dd70e28af41f654a7874405eabEvan Cheng /// initialization code. 3090e6a052331f674dd70e28af41f654a7874405eabEvan Cheng void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) { 3100e6a052331f674dd70e28af41f654a7874405eabEvan Cheng L2SEHRegs[LLVMReg] = SEHReg; 3110e6a052331f674dd70e28af41f654a7874405eabEvan Cheng } 3120e6a052331f674dd70e28af41f654a7874405eabEvan Cheng 313de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar void mapLLVMRegToCVReg(unsigned LLVMReg, int CVReg) { 314de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar L2CVRegs[LLVMReg] = CVReg; 315de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 316de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 31739758cd55d994c0899acfb365d717e9f877ca001Jim Grosbach /// \brief This method should return the register where the return 3180e6a052331f674dd70e28af41f654a7874405eabEvan Cheng /// address can be found. 3190e6a052331f674dd70e28af41f654a7874405eabEvan Cheng unsigned getRARegister() const { 3200e6a052331f674dd70e28af41f654a7874405eabEvan Cheng return RAReg; 3210e6a052331f674dd70e28af41f654a7874405eabEvan Cheng } 3220e6a052331f674dd70e28af41f654a7874405eabEvan Cheng 323fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach /// Return the register which is the program counter. 324fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach unsigned getProgramCounter() const { 325fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach return PCReg; 326fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach } 327fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach 328f5fa52ed064098be7130aa4ec1236037907ce3faEvan Cheng const MCRegisterDesc &operator[](unsigned RegNo) const { 329a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng assert(RegNo < NumRegs && 330a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng "Attempting to access record for invalid register number!"); 331a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng return Desc[RegNo]; 332a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng } 333a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng 33439758cd55d994c0899acfb365d717e9f877ca001Jim Grosbach /// \brief Provide a get method, equivalent to [], but more useful with a 335a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng /// pointer to this object. 336f5fa52ed064098be7130aa4ec1236037907ce3faEvan Cheng const MCRegisterDesc &get(unsigned RegNo) const { 337a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng return operator[](RegNo); 338a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng } 339a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng 34039758cd55d994c0899acfb365d717e9f877ca001Jim Grosbach /// \brief Returns the physical register number of sub-register "Index" 341b3acdcc00c9dfb01663780e858e586cc5f04423fJim Grosbach /// for physical register RegNo. Return zero if the sub-register does not 342b3acdcc00c9dfb01663780e858e586cc5f04423fJim Grosbach /// exist. 3430371cd8b1c0d2101295ca9381a0b437e1f2d8fa2Jakob Stoklund Olesen unsigned getSubReg(unsigned Reg, unsigned Idx) const; 344b3acdcc00c9dfb01663780e858e586cc5f04423fJim Grosbach 34539758cd55d994c0899acfb365d717e9f877ca001Jim Grosbach /// \brief Return a super-register of the specified register 34633ca87affb81b60c4d50214eb7458bd26d397d53Jim Grosbach /// Reg so its sub-register of index SubIdx is Reg. 34733ca87affb81b60c4d50214eb7458bd26d397d53Jim Grosbach unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 348396618b43a85e12d290a90b181c6af5d7c0c5f11Jakob Stoklund Olesen const MCRegisterClass *RC) const; 34933ca87affb81b60c4d50214eb7458bd26d397d53Jim Grosbach 35039758cd55d994c0899acfb365d717e9f877ca001Jim Grosbach /// \brief For a given register pair, return the sub-register index 3514b1212b4bfac98c688d484bf22ae158875f06ad5Benjamin Kramer /// if the second register is a sub-register of the first. Return zero 3524b1212b4bfac98c688d484bf22ae158875f06ad5Benjamin Kramer /// otherwise. 3530371cd8b1c0d2101295ca9381a0b437e1f2d8fa2Jakob Stoklund Olesen unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const; 3544b1212b4bfac98c688d484bf22ae158875f06ad5Benjamin Kramer 35523ed37a6b76e79272194fb46597f7280661b828fAhmed Bougacha /// \brief Get the size of the bit range covered by a sub-register index. 35623ed37a6b76e79272194fb46597f7280661b828fAhmed Bougacha /// If the index isn't continuous, return the sum of the sizes of its parts. 35723ed37a6b76e79272194fb46597f7280661b828fAhmed Bougacha /// If the index is used to access subregisters of different sizes, return -1. 35823ed37a6b76e79272194fb46597f7280661b828fAhmed Bougacha unsigned getSubRegIdxSize(unsigned Idx) const; 35923ed37a6b76e79272194fb46597f7280661b828fAhmed Bougacha 36023ed37a6b76e79272194fb46597f7280661b828fAhmed Bougacha /// \brief Get the offset of the bit range covered by a sub-register index. 36123ed37a6b76e79272194fb46597f7280661b828fAhmed Bougacha /// If an Offset doesn't make sense (the index isn't continuous, or is used to 36223ed37a6b76e79272194fb46597f7280661b828fAhmed Bougacha /// access sub-registers at different offsets), return -1. 36323ed37a6b76e79272194fb46597f7280661b828fAhmed Bougacha unsigned getSubRegIdxOffset(unsigned Idx) const; 364bed23081860275c79137f65d592920e7991b8198Ahmed Bougacha 36539758cd55d994c0899acfb365d717e9f877ca001Jim Grosbach /// \brief Return the human-readable symbolic target-specific name for the 366a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng /// specified physical register. 367a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng const char *getName(unsigned RegNo) const { 368d5ce3ffa67698b9d21f58011f370a210a214d301Jakob Stoklund Olesen return RegStrings + get(RegNo).Name; 369a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng } 370a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng 37139758cd55d994c0899acfb365d717e9f877ca001Jim Grosbach /// \brief Return the number of registers this target has (useful for 372a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng /// sizing arrays holding per register information) 373a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng unsigned getNumRegs() const { 374a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng return NumRegs; 375a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng } 3760e6a052331f674dd70e28af41f654a7874405eabEvan Cheng 37739758cd55d994c0899acfb365d717e9f877ca001Jim Grosbach /// \brief Return the number of sub-register indices 37859f45e4610e64b88bcee4cd46816ef64e815ff7eJakob Stoklund Olesen /// understood by the target. Index 0 is reserved for the no-op sub-register, 37959f45e4610e64b88bcee4cd46816ef64e815ff7eJakob Stoklund Olesen /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers. 38059f45e4610e64b88bcee4cd46816ef64e815ff7eJakob Stoklund Olesen unsigned getNumSubRegIndices() const { 38159f45e4610e64b88bcee4cd46816ef64e815ff7eJakob Stoklund Olesen return NumSubRegIndices; 38259f45e4610e64b88bcee4cd46816ef64e815ff7eJakob Stoklund Olesen } 38359f45e4610e64b88bcee4cd46816ef64e815ff7eJakob Stoklund Olesen 38439758cd55d994c0899acfb365d717e9f877ca001Jim Grosbach /// \brief Return the number of (native) register units in the 385f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They 386f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen /// can be accessed through MCRegUnitIterator defined below. 387f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen unsigned getNumRegUnits() const { 388f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen return NumRegUnits; 389f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen } 390f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen 39139758cd55d994c0899acfb365d717e9f877ca001Jim Grosbach /// \brief Map a target register to an equivalent dwarf register 3920e6a052331f674dd70e28af41f654a7874405eabEvan Cheng /// number. Returns -1 if there is no equivalent value. The second 3930e6a052331f674dd70e28af41f654a7874405eabEvan Cheng /// parameter allows targets to use different numberings for EH info and 3940e6a052331f674dd70e28af41f654a7874405eabEvan Cheng /// debugging info. 39546c0dc7858da65707340ca62b258f8956def78e8Jakob Stoklund Olesen int getDwarfRegNum(unsigned RegNum, bool isEH) const; 3960e6a052331f674dd70e28af41f654a7874405eabEvan Cheng 39739758cd55d994c0899acfb365d717e9f877ca001Jim Grosbach /// \brief Map a dwarf register back to a target register. 39846c0dc7858da65707340ca62b258f8956def78e8Jakob Stoklund Olesen int getLLVMRegNum(unsigned RegNum, bool isEH) const; 3990e6a052331f674dd70e28af41f654a7874405eabEvan Cheng 40039758cd55d994c0899acfb365d717e9f877ca001Jim Grosbach /// \brief Map a target register to an equivalent SEH register 4010e6a052331f674dd70e28af41f654a7874405eabEvan Cheng /// number. Returns LLVM register number if there is no equivalent value. 40246c0dc7858da65707340ca62b258f8956def78e8Jakob Stoklund Olesen int getSEHRegNum(unsigned RegNum) const; 4038ca9a862038e8c4e9a2ca73b3b75e1be3425155fBenjamin Kramer 404de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar /// \brief Map a target register to an equivalent CodeView register 405de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar /// number. 406de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar int getCodeViewRegNum(unsigned RegNum) const; 407de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 4088ca9a862038e8c4e9a2ca73b3b75e1be3425155fBenjamin Kramer regclass_iterator regclass_begin() const { return Classes; } 4098ca9a862038e8c4e9a2ca73b3b75e1be3425155fBenjamin Kramer regclass_iterator regclass_end() const { return Classes+NumClasses; } 4108ca9a862038e8c4e9a2ca73b3b75e1be3425155fBenjamin Kramer 4118ca9a862038e8c4e9a2ca73b3b75e1be3425155fBenjamin Kramer unsigned getNumRegClasses() const { 4128ca9a862038e8c4e9a2ca73b3b75e1be3425155fBenjamin Kramer return (unsigned)(regclass_end()-regclass_begin()); 4138ca9a862038e8c4e9a2ca73b3b75e1be3425155fBenjamin Kramer } 4148ca9a862038e8c4e9a2ca73b3b75e1be3425155fBenjamin Kramer 41539758cd55d994c0899acfb365d717e9f877ca001Jim Grosbach /// \brief Returns the register class associated with the enumeration 4168ca9a862038e8c4e9a2ca73b3b75e1be3425155fBenjamin Kramer /// value. See class MCOperandInfo. 417f29c05e883dc46f3f1be9b3a5f5c50ee73899380Lang Hames const MCRegisterClass& getRegClass(unsigned i) const { 4188ca9a862038e8c4e9a2ca73b3b75e1be3425155fBenjamin Kramer assert(i < getNumRegClasses() && "Register Class ID out of range"); 4198ca9a862038e8c4e9a2ca73b3b75e1be3425155fBenjamin Kramer return Classes[i]; 4208ca9a862038e8c4e9a2ca73b3b75e1be3425155fBenjamin Kramer } 4210ee07e013095e8c298fbcc5203e0bc9f334e15e1Jim Grosbach 42237ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines const char *getRegClassName(const MCRegisterClass *Class) const { 42337ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines return RegClassStrings + Class->NameIdx; 42437ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines } 42537ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines 42639758cd55d994c0899acfb365d717e9f877ca001Jim Grosbach /// \brief Returns the encoding for RegNo 4270ee07e013095e8c298fbcc5203e0bc9f334e15e1Jim Grosbach uint16_t getEncodingValue(unsigned RegNo) const { 4280ee07e013095e8c298fbcc5203e0bc9f334e15e1Jim Grosbach assert(RegNo < NumRegs && 4290ee07e013095e8c298fbcc5203e0bc9f334e15e1Jim Grosbach "Attempting to get encoding for invalid register number!"); 4300ee07e013095e8c298fbcc5203e0bc9f334e15e1Jim Grosbach return RegEncodingTable[RegNo]; 4310ee07e013095e8c298fbcc5203e0bc9f334e15e1Jim Grosbach } 4320ee07e013095e8c298fbcc5203e0bc9f334e15e1Jim Grosbach 43339758cd55d994c0899acfb365d717e9f877ca001Jim Grosbach /// \brief Returns true if RegB is a sub-register of RegA. 43416f3204b95c952a70c9d2aa3b423162215beb6aeJim Grosbach bool isSubRegister(unsigned RegA, unsigned RegB) const { 43516f3204b95c952a70c9d2aa3b423162215beb6aeJim Grosbach return isSuperRegister(RegB, RegA); 436e188fb7dd91c6fee15aa18c877d664d63d736000Jim Grosbach } 437e188fb7dd91c6fee15aa18c877d664d63d736000Jim Grosbach 43839758cd55d994c0899acfb365d717e9f877ca001Jim Grosbach /// \brief Returns true if RegB is a super-register of RegA. 439e188fb7dd91c6fee15aa18c877d664d63d736000Jim Grosbach bool isSuperRegister(unsigned RegA, unsigned RegB) const; 440e188fb7dd91c6fee15aa18c877d664d63d736000Jim Grosbach 44139758cd55d994c0899acfb365d717e9f877ca001Jim Grosbach /// \brief Returns true if RegB is a sub-register of RegA or if RegB == RegA. 44216f3204b95c952a70c9d2aa3b423162215beb6aeJim Grosbach bool isSubRegisterEq(unsigned RegA, unsigned RegB) const { 44316f3204b95c952a70c9d2aa3b423162215beb6aeJim Grosbach return isSuperRegisterEq(RegB, RegA); 44416f3204b95c952a70c9d2aa3b423162215beb6aeJim Grosbach } 44516f3204b95c952a70c9d2aa3b423162215beb6aeJim Grosbach 44639758cd55d994c0899acfb365d717e9f877ca001Jim Grosbach /// \brief Returns true if RegB is a super-register of RegA or if 44739758cd55d994c0899acfb365d717e9f877ca001Jim Grosbach /// RegB == RegA. 44816f3204b95c952a70c9d2aa3b423162215beb6aeJim Grosbach bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const { 44916f3204b95c952a70c9d2aa3b423162215beb6aeJim Grosbach return RegA == RegB || isSuperRegister(RegA, RegB); 45016f3204b95c952a70c9d2aa3b423162215beb6aeJim Grosbach } 45116f3204b95c952a70c9d2aa3b423162215beb6aeJim Grosbach 452de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar /// \brief Returns true if RegB is a super-register or sub-register of RegA 453de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar /// or if RegB == RegA. 454de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool isSuperOrSubRegisterEq(unsigned RegA, unsigned RegB) const { 455de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB); 456de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 457a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng}; 458492be647722fc2f372e650ce4a5d9e10171dbe0eJim Grosbach 459f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen//===----------------------------------------------------------------------===// 460cd00ef033cf944fc96a0d06ffcf49cd805fc4ee3Jakob Stoklund Olesen// Register List Iterators 461cd00ef033cf944fc96a0d06ffcf49cd805fc4ee3Jakob Stoklund Olesen//===----------------------------------------------------------------------===// 462cd00ef033cf944fc96a0d06ffcf49cd805fc4ee3Jakob Stoklund Olesen 463cd00ef033cf944fc96a0d06ffcf49cd805fc4ee3Jakob Stoklund Olesen// MCRegisterInfo provides lists of super-registers, sub-registers, and 464cd00ef033cf944fc96a0d06ffcf49cd805fc4ee3Jakob Stoklund Olesen// aliasing registers. Use these iterator classes to traverse the lists. 465cd00ef033cf944fc96a0d06ffcf49cd805fc4ee3Jakob Stoklund Olesen 466cd00ef033cf944fc96a0d06ffcf49cd805fc4ee3Jakob Stoklund Olesen/// MCSubRegIterator enumerates all sub-registers of Reg. 4670e1fae4cf22956f59d392b2fc1681075804596baChad Rosier/// If IncludeSelf is set, Reg itself is included in the list. 468303c909d5bb014fbeec395090eb467d724969195Jakob Stoklund Olesenclass MCSubRegIterator : public MCRegisterInfo::DiffListIterator { 469cd00ef033cf944fc96a0d06ffcf49cd805fc4ee3Jakob Stoklund Olesenpublic: 4700e1fae4cf22956f59d392b2fc1681075804596baChad Rosier MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI, 4710e1fae4cf22956f59d392b2fc1681075804596baChad Rosier bool IncludeSelf = false) { 472303c909d5bb014fbeec395090eb467d724969195Jakob Stoklund Olesen init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs); 4730e1fae4cf22956f59d392b2fc1681075804596baChad Rosier // Initially, the iterator points to Reg itself. 4740e1fae4cf22956f59d392b2fc1681075804596baChad Rosier if (!IncludeSelf) 4750e1fae4cf22956f59d392b2fc1681075804596baChad Rosier ++*this; 476303c909d5bb014fbeec395090eb467d724969195Jakob Stoklund Olesen } 477cd00ef033cf944fc96a0d06ffcf49cd805fc4ee3Jakob Stoklund Olesen}; 478cd00ef033cf944fc96a0d06ffcf49cd805fc4ee3Jakob Stoklund Olesen 479ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines/// Iterator that enumerates the sub-registers of a Reg and the associated 480ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines/// sub-register indices. 481ebe69fe11e48d322045d5949c83283927a0d790bStephen Hinesclass MCSubRegIndexIterator { 482ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines MCSubRegIterator SRIter; 483ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines const uint16_t *SRIndex; 484ebe69fe11e48d322045d5949c83283927a0d790bStephen Hinespublic: 485ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines /// Constructs an iterator that traverses subregisters and their 486ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines /// associated subregister indices. 487ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines MCSubRegIndexIterator(unsigned Reg, const MCRegisterInfo *MCRI) 488ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines : SRIter(Reg, MCRI) { 489ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices; 490ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines } 491ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 492ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines /// Returns current sub-register. 493ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines unsigned getSubReg() const { 494ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines return *SRIter; 495ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines } 496ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines /// Returns sub-register index of the current sub-register. 497ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines unsigned getSubRegIndex() const { 498ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines return *SRIndex; 499ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines } 500ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 501ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines /// Returns true if this iterator is not yet at the end. 502ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines bool isValid() const { return SRIter.isValid(); } 503ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 504ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines /// Moves to the next position. 505ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines void operator++() { 506ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines ++SRIter; 507ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines ++SRIndex; 508ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines } 509ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines}; 510ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 511cd00ef033cf944fc96a0d06ffcf49cd805fc4ee3Jakob Stoklund Olesen/// MCSuperRegIterator enumerates all super-registers of Reg. 5120e1fae4cf22956f59d392b2fc1681075804596baChad Rosier/// If IncludeSelf is set, Reg itself is included in the list. 513303c909d5bb014fbeec395090eb467d724969195Jakob Stoklund Olesenclass MCSuperRegIterator : public MCRegisterInfo::DiffListIterator { 514cd00ef033cf944fc96a0d06ffcf49cd805fc4ee3Jakob Stoklund Olesenpublic: 5152275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier MCSuperRegIterator() {} 5160e1fae4cf22956f59d392b2fc1681075804596baChad Rosier MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI, 5170e1fae4cf22956f59d392b2fc1681075804596baChad Rosier bool IncludeSelf = false) { 518303c909d5bb014fbeec395090eb467d724969195Jakob Stoklund Olesen init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs); 5190e1fae4cf22956f59d392b2fc1681075804596baChad Rosier // Initially, the iterator points to Reg itself. 5200e1fae4cf22956f59d392b2fc1681075804596baChad Rosier if (!IncludeSelf) 5210e1fae4cf22956f59d392b2fc1681075804596baChad Rosier ++*this; 522303c909d5bb014fbeec395090eb467d724969195Jakob Stoklund Olesen } 523cd00ef033cf944fc96a0d06ffcf49cd805fc4ee3Jakob Stoklund Olesen}; 524cd00ef033cf944fc96a0d06ffcf49cd805fc4ee3Jakob Stoklund Olesen 525e188fb7dd91c6fee15aa18c877d664d63d736000Jim Grosbach// Definition for isSuperRegister. Put it down here since it needs the 526e188fb7dd91c6fee15aa18c877d664d63d736000Jim Grosbach// iterator defined above in addition to the MCRegisterInfo class itself. 527e188fb7dd91c6fee15aa18c877d664d63d736000Jim Grosbachinline bool MCRegisterInfo::isSuperRegister(unsigned RegA, unsigned RegB) const{ 528e188fb7dd91c6fee15aa18c877d664d63d736000Jim Grosbach for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I) 529e188fb7dd91c6fee15aa18c877d664d63d736000Jim Grosbach if (*I == RegB) 530e188fb7dd91c6fee15aa18c877d664d63d736000Jim Grosbach return true; 531e188fb7dd91c6fee15aa18c877d664d63d736000Jim Grosbach return false; 532e188fb7dd91c6fee15aa18c877d664d63d736000Jim Grosbach} 533e188fb7dd91c6fee15aa18c877d664d63d736000Jim Grosbach 534cd00ef033cf944fc96a0d06ffcf49cd805fc4ee3Jakob Stoklund Olesen//===----------------------------------------------------------------------===// 535f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen// Register Units 536f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen//===----------------------------------------------------------------------===// 537f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen 538f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen// Register units are used to compute register aliasing. Every register has at 539f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen// least one register unit, but it can have more. Two registers overlap if and 540f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen// only if they have a common register unit. 541f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen// 542f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen// A target with a complicated sub-register structure will typically have many 543f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen// fewer register units than actual registers. MCRI::getNumRegUnits() returns 544f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen// the number of register units in the target. 545f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen 546f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen// MCRegUnitIterator enumerates a list of register units for Reg. The list is 547f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen// in ascending numerical order. 548f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesenclass MCRegUnitIterator : public MCRegisterInfo::DiffListIterator { 549f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesenpublic: 550f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen /// MCRegUnitIterator - Create an iterator that traverses the register units 551f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen /// in Reg. 5522275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier MCRegUnitIterator() {} 553f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) { 55470fe6ecb6d0c3b556f2c4e3c1e5013da821bededJakob Stoklund Olesen assert(Reg && "Null register has no regunits"); 555f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen // Decode the RegUnits MCRegisterDesc field. 556f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen unsigned RU = MCRI->get(Reg).RegUnits; 557f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen unsigned Scale = RU & 15; 558f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen unsigned Offset = RU >> 4; 559f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen 560f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen // Initialize the iterator to Reg * Scale, and the List pointer to 561f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen // DiffLists + Offset. 562f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen init(Reg * Scale, MCRI->DiffLists + Offset); 563f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen 564f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen // That may not be a valid unit, we need to advance by one to get the real 565f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen // unit number. The first differential can be 0 which would normally 566f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen // terminate the list, but since we know every register has at least one 567f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen // unit, we can allow a 0 differential here. 568f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen advance(); 569f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen } 570f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen}; 571f52baf72c116d9cf8680d25a8e751ce354c7d44bJakob Stoklund Olesen 572ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines/// MCRegUnitIterator enumerates a list of register units and their associated 573ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines/// lane masks for Reg. The register units are in ascending numerical order. 574ebe69fe11e48d322045d5949c83283927a0d790bStephen Hinesclass MCRegUnitMaskIterator { 575ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines MCRegUnitIterator RUIter; 576ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines const unsigned *MaskListIter; 577ebe69fe11e48d322045d5949c83283927a0d790bStephen Hinespublic: 578ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines MCRegUnitMaskIterator() {} 579ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines /// Constructs an iterator that traverses the register units and their 580ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines /// associated LaneMasks in Reg. 581ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines MCRegUnitMaskIterator(unsigned Reg, const MCRegisterInfo *MCRI) 582ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines : RUIter(Reg, MCRI) { 583ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines uint16_t Idx = MCRI->get(Reg).RegUnitLaneMasks; 584ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines MaskListIter = &MCRI->RegUnitMaskSequences[Idx]; 585ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines } 586ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 587ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines /// Returns a (RegUnit, LaneMask) pair. 588ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines std::pair<unsigned,unsigned> operator*() const { 589ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines return std::make_pair(*RUIter, *MaskListIter); 590ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines } 591ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 592ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines /// Returns true if this iterator is not yet at the end. 593ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines bool isValid() const { return RUIter.isValid(); } 594ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 595ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines /// Moves to the next position. 596ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines void operator++() { 597ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines ++MaskListIter; 598ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines ++RUIter; 599ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines } 600ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines}; 601ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 602f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen// Each register unit has one or two root registers. The complete set of 603f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen// registers containing a register unit is the union of the roots and their 604f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen// super-registers. All registers aliasing Unit can be visited like this: 605f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen// 606f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen// for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) { 607549221f18c8248cd5daa8967ba999b91b1fe2584Chad Rosier// for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI) 608f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen// visit(*SI); 609f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen// } 610f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen 611f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen/// MCRegUnitRootIterator enumerates the root registers of a register unit. 612f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesenclass MCRegUnitRootIterator { 613f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen uint16_t Reg0; 614f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen uint16_t Reg1; 615f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesenpublic: 6162275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier MCRegUnitRootIterator() : Reg0(0), Reg1(0) {} 617f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) { 618f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit"); 619f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen Reg0 = MCRI->RegUnitRoots[RegUnit][0]; 620f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen Reg1 = MCRI->RegUnitRoots[RegUnit][1]; 621f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen } 622f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen 62339758cd55d994c0899acfb365d717e9f877ca001Jim Grosbach /// \brief Dereference to get the current root register. 624f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen unsigned operator*() const { 625f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen return Reg0; 626f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen } 627f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen 62839758cd55d994c0899acfb365d717e9f877ca001Jim Grosbach /// \brief Check if the iterator is at the end of the list. 629f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen bool isValid() const { 630f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen return Reg0; 631f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen } 632f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen 63339758cd55d994c0899acfb365d717e9f877ca001Jim Grosbach /// \brief Preincrement to move to the next root register. 634f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen void operator++() { 635f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen assert(isValid() && "Cannot move off the end of the list."); 636f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen Reg0 = Reg1; 637f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen Reg1 = 0; 638f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen } 639f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen}; 640f5d4e5158fcbec26d1c243daa725878ca1ae560bJakob Stoklund Olesen 6412275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier/// MCRegAliasIterator enumerates all registers aliasing Reg. If IncludeSelf is 6422275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier/// set, Reg itself is included in the list. This iterator does not guarantee 6432275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier/// any ordering or that entries are unique. 6442275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosierclass MCRegAliasIterator { 6452275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosierprivate: 6462275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier unsigned Reg; 6472275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier const MCRegisterInfo *MCRI; 6482275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier bool IncludeSelf; 649f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 6502275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier MCRegUnitIterator RI; 6512275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier MCRegUnitRootIterator RRI; 6522275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier MCSuperRegIterator SI; 6532275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosierpublic: 6542275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI, 6552275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier bool IncludeSelf) 6562275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) { 6572275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier 6582275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier // Initialize the iterators. 6592275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); ++RI) { 6602275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) { 6612275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); ++SI) { 6622275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier if (!(!IncludeSelf && Reg == *SI)) 6632275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier return; 6642275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier } 6652275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier } 6662275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier } 6672275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier } 6682275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier 669f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar bool isValid() const { return RI.isValid(); } 670f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 6712275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier unsigned operator*() const { 6722275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier assert (SI.isValid() && "Cannot dereference an invalid iterator."); 6732275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier return *SI; 6742275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier } 6752275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier 6762275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier void advance() { 6772275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier // Assuming SI is valid. 6782275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier ++SI; 6792275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier if (SI.isValid()) return; 6802275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier 6812275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier ++RRI; 6822275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier if (RRI.isValid()) { 6832275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier SI = MCSuperRegIterator(*RRI, MCRI, true); 6842275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier return; 6852275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier } 6862275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier 6872275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier ++RI; 6882275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier if (RI.isValid()) { 6892275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier RRI = MCRegUnitRootIterator(*RI, MCRI); 6902275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier SI = MCSuperRegIterator(*RRI, MCRI, true); 6912275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier } 6922275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier } 6932275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier 6942275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier void operator++() { 6952275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier assert(isValid() && "Cannot move off the end of the list."); 6962275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier do advance(); 6972275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier while (!IncludeSelf && isValid() && *SI == Reg); 6982275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier } 6992275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier}; 7002275cfd75b65ede0f46f3cf914e76a38daf96417Chad Rosier 701a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng} // End llvm namespace 702a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng 703a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng#endif 704