TargetRegisterInfo.h revision 3ca15c989ca0e09085648771db368d8c94ee1f19
1//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes an abstract interface used to get information about a 11// target machines register file. This information is used for a variety of 12// purposed, especially register allocation. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_TARGET_TARGETREGISTERINFO_H 17#define LLVM_TARGET_TARGETREGISTERINFO_H 18 19#include "llvm/CodeGen/MachineBasicBlock.h" 20#include "llvm/CodeGen/ValueTypes.h" 21#include <cassert> 22#include <functional> 23 24namespace llvm { 25 26class BitVector; 27class MachineFunction; 28class MachineMove; 29class RegScavenger; 30 31/// TargetRegisterDesc - This record contains all of the information known about 32/// a particular register. The AliasSet field (if not null) contains a pointer 33/// to a Zero terminated array of registers that this register aliases. This is 34/// needed for architectures like X86 which have AL alias AX alias EAX. 35/// Registers that this does not apply to simply should set this to null. 36/// The SubRegs field is a zero terminated array of registers that are 37/// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX. 38/// The SuperRegs field is a zero terminated array of registers that are 39/// super-registers of the specific register, e.g. RAX, EAX, are super-registers 40/// of AX. 41/// 42struct TargetRegisterDesc { 43 const char *AsmName; // Assembly language name for the register 44 const char *Name; // Printable name for the reg (for debugging) 45 const unsigned *AliasSet; // Register Alias Set, described above 46 const unsigned *SubRegs; // Sub-register set, described above 47 const unsigned *SuperRegs; // Super-register set, described above 48}; 49 50class TargetRegisterClass { 51public: 52 typedef const unsigned* iterator; 53 typedef const unsigned* const_iterator; 54 55 typedef const MVT* vt_iterator; 56 typedef const TargetRegisterClass* const * sc_iterator; 57private: 58 unsigned ID; 59 const char *Name; 60 bool isSubClass; 61 const vt_iterator VTs; 62 const sc_iterator SubClasses; 63 const sc_iterator SuperClasses; 64 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes 65 const int CopyCost; 66 const iterator RegsBegin, RegsEnd; 67public: 68 TargetRegisterClass(unsigned id, 69 const char *name, 70 const MVT *vts, 71 const TargetRegisterClass * const *subcs, 72 const TargetRegisterClass * const *supcs, 73 unsigned RS, unsigned Al, int CC, 74 iterator RB, iterator RE) 75 : ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs), 76 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {} 77 virtual ~TargetRegisterClass() {} // Allow subclasses 78 79 /// getID() - Return the register class ID number. 80 /// 81 unsigned getID() const { return ID; } 82 83 /// getName() - Return the register class name for debugging. 84 /// 85 const char *getName() const { return Name; } 86 87 /// begin/end - Return all of the registers in this class. 88 /// 89 iterator begin() const { return RegsBegin; } 90 iterator end() const { return RegsEnd; } 91 92 /// getNumRegs - Return the number of registers in this class. 93 /// 94 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); } 95 96 /// getRegister - Return the specified register in the class. 97 /// 98 unsigned getRegister(unsigned i) const { 99 assert(i < getNumRegs() && "Register number out of range!"); 100 return RegsBegin[i]; 101 } 102 103 /// contains - Return true if the specified register is included in this 104 /// register class. 105 bool contains(unsigned Reg) const { 106 for (iterator I = begin(), E = end(); I != E; ++I) 107 if (*I == Reg) return true; 108 return false; 109 } 110 111 /// hasType - return true if this TargetRegisterClass has the ValueType vt. 112 /// 113 bool hasType(MVT vt) const { 114 for(int i = 0; VTs[i] != MVT::Other; ++i) 115 if (VTs[i] == vt) 116 return true; 117 return false; 118 } 119 120 /// vt_begin / vt_end - Loop over all of the value types that can be 121 /// represented by values in this register class. 122 vt_iterator vt_begin() const { 123 return VTs; 124 } 125 126 vt_iterator vt_end() const { 127 vt_iterator I = VTs; 128 while (*I != MVT::Other) ++I; 129 return I; 130 } 131 132 /// hasSubClass - return true if the specified TargetRegisterClass is a 133 /// sub-register class of this TargetRegisterClass. 134 bool hasSubClass(const TargetRegisterClass *cs) const { 135 for (int i = 0; SubClasses[i] != NULL; ++i) 136 if (SubClasses[i] == cs) 137 return true; 138 return false; 139 } 140 141 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of 142 /// this register class. 143 sc_iterator subclasses_begin() const { 144 return SubClasses; 145 } 146 147 sc_iterator subclasses_end() const { 148 sc_iterator I = SubClasses; 149 while (*I != NULL) ++I; 150 return I; 151 } 152 153 /// hasSuperClass - return true if the specified TargetRegisterClass is a 154 /// super-register class of this TargetRegisterClass. 155 bool hasSuperClass(const TargetRegisterClass *cs) const { 156 for (int i = 0; SuperClasses[i] != NULL; ++i) 157 if (SuperClasses[i] == cs) 158 return true; 159 return false; 160 } 161 162 /// superclasses_begin / superclasses_end - Loop over all of the super-classes 163 /// of this register class. 164 sc_iterator superclasses_begin() const { 165 return SuperClasses; 166 } 167 168 sc_iterator superclasses_end() const { 169 sc_iterator I = SuperClasses; 170 while (*I != NULL) ++I; 171 return I; 172 } 173 174 /// isASubClass - return true if this TargetRegisterClass is a sub-class of at 175 /// least one other TargetRegisterClass. 176 bool isASubClass() const { 177 return SuperClasses[0] != 0; 178 } 179 180 /// allocation_order_begin/end - These methods define a range of registers 181 /// which specify the registers in this class that are valid to register 182 /// allocate, and the preferred order to allocate them in. For example, 183 /// callee saved registers should be at the end of the list, because it is 184 /// cheaper to allocate caller saved registers. 185 /// 186 /// These methods take a MachineFunction argument, which can be used to tune 187 /// the allocatable registers based on the characteristics of the function. 188 /// One simple example is that the frame pointer register can be used if 189 /// frame-pointer-elimination is performed. 190 /// 191 /// By default, these methods return all registers in the class. 192 /// 193 virtual iterator allocation_order_begin(const MachineFunction &MF) const { 194 return begin(); 195 } 196 virtual iterator allocation_order_end(const MachineFunction &MF) const { 197 return end(); 198 } 199 200 201 202 /// getSize - Return the size of the register in bytes, which is also the size 203 /// of a stack slot allocated to hold a spilled copy of this register. 204 unsigned getSize() const { return RegSize; } 205 206 /// getAlignment - Return the minimum required alignment for a register of 207 /// this class. 208 unsigned getAlignment() const { return Alignment; } 209 210 /// getCopyCost - Return the cost of copying a value between two registers in 211 /// this class. A negative number means the register class is very expensive 212 /// to copy e.g. status flag register classes. 213 int getCopyCost() const { return CopyCost; } 214}; 215 216 217/// TargetRegisterInfo base class - We assume that the target defines a static 218/// array of TargetRegisterDesc objects that represent all of the machine 219/// registers that the target has. As such, we simply have to track a pointer 220/// to this array so that we can turn register number into a register 221/// descriptor. 222/// 223class TargetRegisterInfo { 224protected: 225 const unsigned* SubregHash; 226 const unsigned SubregHashSize; 227 const unsigned* SuperregHash; 228 const unsigned SuperregHashSize; 229 const unsigned* AliasesHash; 230 const unsigned AliasesHashSize; 231public: 232 typedef const TargetRegisterClass * const * regclass_iterator; 233private: 234 const TargetRegisterDesc *Desc; // Pointer to the descriptor array 235 unsigned NumRegs; // Number of entries in the array 236 237 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 238 239 int CallFrameSetupOpcode, CallFrameDestroyOpcode; 240protected: 241 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR, 242 regclass_iterator RegClassBegin, 243 regclass_iterator RegClassEnd, 244 int CallFrameSetupOpcode = -1, 245 int CallFrameDestroyOpcode = -1, 246 const unsigned* subregs = 0, 247 const unsigned subregsize = 0, 248 const unsigned* superregs = 0, 249 const unsigned superregsize = 0, 250 const unsigned* aliases = 0, 251 const unsigned aliasessize = 0); 252 virtual ~TargetRegisterInfo(); 253public: 254 255 enum { // Define some target independent constants 256 /// NoRegister - This physical register is not a real target register. It 257 /// is useful as a sentinal. 258 NoRegister = 0, 259 260 /// FirstVirtualRegister - This is the first register number that is 261 /// considered to be a 'virtual' register, which is part of the SSA 262 /// namespace. This must be the same for all targets, which means that each 263 /// target is limited to 1024 registers. 264 FirstVirtualRegister = 1024 265 }; 266 267 /// isPhysicalRegister - Return true if the specified register number is in 268 /// the physical register namespace. 269 static bool isPhysicalRegister(unsigned Reg) { 270 assert(Reg && "this is not a register!"); 271 return Reg < FirstVirtualRegister; 272 } 273 274 /// isVirtualRegister - Return true if the specified register number is in 275 /// the virtual register namespace. 276 static bool isVirtualRegister(unsigned Reg) { 277 assert(Reg && "this is not a register!"); 278 return Reg >= FirstVirtualRegister; 279 } 280 281 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical 282 /// register of the given type. If type is MVT::Other, then just return any 283 /// register class the register belongs to. 284 virtual const TargetRegisterClass * 285 getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const; 286 287 /// getAllocatableSet - Returns a bitset indexed by register number 288 /// indicating if a register is allocatable or not. If a register class is 289 /// specified, returns the subset for the class. 290 BitVector getAllocatableSet(MachineFunction &MF, 291 const TargetRegisterClass *RC = NULL) const; 292 293 const TargetRegisterDesc &operator[](unsigned RegNo) const { 294 assert(RegNo < NumRegs && 295 "Attempting to access record for invalid register number!"); 296 return Desc[RegNo]; 297 } 298 299 /// Provide a get method, equivalent to [], but more useful if we have a 300 /// pointer to this object. 301 /// 302 const TargetRegisterDesc &get(unsigned RegNo) const { 303 return operator[](RegNo); 304 } 305 306 /// getAliasSet - Return the set of registers aliased by the specified 307 /// register, or a null list of there are none. The list returned is zero 308 /// terminated. 309 /// 310 const unsigned *getAliasSet(unsigned RegNo) const { 311 return get(RegNo).AliasSet; 312 } 313 314 /// getSubRegisters - Return the list of registers that are sub-registers of 315 /// the specified register, or a null list of there are none. The list 316 /// returned is zero terminated and sorted according to super-sub register 317 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH. 318 /// 319 const unsigned *getSubRegisters(unsigned RegNo) const { 320 return get(RegNo).SubRegs; 321 } 322 323 /// getSuperRegisters - Return the list of registers that are super-registers 324 /// of the specified register, or a null list of there are none. The list 325 /// returned is zero terminated and sorted according to super-sub register 326 /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX. 327 /// 328 const unsigned *getSuperRegisters(unsigned RegNo) const { 329 return get(RegNo).SuperRegs; 330 } 331 332 /// getAsmName - Return the symbolic target-specific name for the 333 /// specified physical register. 334 const char *getAsmName(unsigned RegNo) const { 335 return get(RegNo).AsmName; 336 } 337 338 /// getName - Return the human-readable symbolic target-specific name for the 339 /// specified physical register. 340 const char *getName(unsigned RegNo) const { 341 return get(RegNo).Name; 342 } 343 344 /// getNumRegs - Return the number of registers this target has (useful for 345 /// sizing arrays holding per register information) 346 unsigned getNumRegs() const { 347 return NumRegs; 348 } 349 350 /// areAliases - Returns true if the two registers alias each other, false 351 /// otherwise 352 bool areAliases(unsigned regA, unsigned regB) const { 353 size_t index = (regA + regB * 37) & (AliasesHashSize-1); 354 unsigned ProbeAmt = 0; 355 while (AliasesHash[index*2] != 0 && 356 AliasesHash[index*2+1] != 0) { 357 if (AliasesHash[index*2] == regA && AliasesHash[index*2+1] == regB) 358 return true; 359 360 index = (index + ProbeAmt) & (AliasesHashSize-1); 361 ProbeAmt += 2; 362 } 363 364 return false; 365 } 366 367 /// regsOverlap - Returns true if the two registers are equal or alias each 368 /// other. The registers may be virtual register. 369 bool regsOverlap(unsigned regA, unsigned regB) const { 370 if (regA == regB) 371 return true; 372 373 if (isVirtualRegister(regA) || isVirtualRegister(regB)) 374 return false; 375 return areAliases(regA, regB); 376 } 377 378 /// isSubRegister - Returns true if regB is a sub-register of regA. 379 /// 380 bool isSubRegister(unsigned regA, unsigned regB) const { 381 // SubregHash is a simple quadratically probed hash table. 382 size_t index = (regA + regB * 37) & (SubregHashSize-1); 383 unsigned ProbeAmt = 2; 384 while (SubregHash[index*2] != 0 && 385 SubregHash[index*2+1] != 0) { 386 if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB) 387 return true; 388 389 index = (index + ProbeAmt) & (SubregHashSize-1); 390 ProbeAmt += 2; 391 } 392 393 return false; 394 } 395 396 /// isSuperRegister - Returns true if regB is a super-register of regA. 397 /// 398 bool isSuperRegister(unsigned regA, unsigned regB) const { 399 // SuperregHash is a simple quadratically probed hash table. 400 size_t index = (regA + regB * 37) & (SuperregHashSize-1); 401 unsigned ProbeAmt = 2; 402 while (SuperregHash[index*2] != 0 && 403 SuperregHash[index*2+1] != 0) { 404 if (SuperregHash[index*2] == regA && SuperregHash[index*2+1] == regB) 405 return true; 406 407 index = (index + ProbeAmt) & (SuperregHashSize-1); 408 ProbeAmt += 2; 409 } 410 411 return false; 412 } 413 414 /// getCalleeSavedRegs - Return a null-terminated list of all of the 415 /// callee saved registers on this target. The register should be in the 416 /// order of desired callee-save stack frame offset. The first register is 417 /// closed to the incoming stack pointer if stack grows down, and vice versa. 418 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0) 419 const = 0; 420 421 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred 422 /// register classes to spill each callee saved register with. The order and 423 /// length of this list match the getCalleeSaveRegs() list. 424 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses( 425 const MachineFunction *MF) const =0; 426 427 /// getReservedRegs - Returns a bitset indexed by physical register number 428 /// indicating if a register is a special register that has particular uses 429 /// and should be considered unavailable at all times, e.g. SP, RA. This is 430 /// used by register scavenger to determine what registers are free. 431 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 432 433 /// getSubReg - Returns the physical register number of sub-register "Index" 434 /// for physical register RegNo. Return zero if the sub-register does not 435 /// exist. 436 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0; 437 438 //===--------------------------------------------------------------------===// 439 // Register Class Information 440 // 441 442 /// Register class iterators 443 /// 444 regclass_iterator regclass_begin() const { return RegClassBegin; } 445 regclass_iterator regclass_end() const { return RegClassEnd; } 446 447 unsigned getNumRegClasses() const { 448 return (unsigned)(regclass_end()-regclass_begin()); 449 } 450 451 /// getRegClass - Returns the register class associated with the enumeration 452 /// value. See class TargetOperandInfo. 453 const TargetRegisterClass *getRegClass(unsigned i) const { 454 assert(i <= getNumRegClasses() && "Register Class ID out of range"); 455 return i ? RegClassBegin[i - 1] : NULL; 456 } 457 458 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 459 /// values. 460 virtual const TargetRegisterClass *getPointerRegClass() const { 461 assert(0 && "Target didn't implement getPointerRegClass!"); 462 return 0; // Must return a value in order to compile with VS 2005 463 } 464 465 /// getCrossCopyRegClass - Returns a legal register class to copy a register 466 /// in the specified class to or from. Returns NULL if it is possible to copy 467 /// between a two registers of the specified class. 468 virtual const TargetRegisterClass * 469 getCrossCopyRegClass(const TargetRegisterClass *RC) const { 470 return NULL; 471 } 472 473 /// targetHandlesStackFrameRounding - Returns true if the target is 474 /// responsible for rounding up the stack frame (probably at emitPrologue 475 /// time). 476 virtual bool targetHandlesStackFrameRounding() const { 477 return false; 478 } 479 480 /// requiresRegisterScavenging - returns true if the target requires (and can 481 /// make use of) the register scavenger. 482 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 483 return false; 484 } 485 486 /// hasFP - Return true if the specified function should have a dedicated 487 /// frame pointer register. For most targets this is true only if the function 488 /// has variable sized allocas or if frame pointer elimination is disabled. 489 virtual bool hasFP(const MachineFunction &MF) const = 0; 490 491 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is 492 // not required, we reserve argument space for call sites in the function 493 // immediately on entry to the current function. This eliminates the need for 494 // add/sub sp brackets around call sites. Returns true if the call frame is 495 // included as part of the stack frame. 496 virtual bool hasReservedCallFrame(MachineFunction &MF) const { 497 return !hasFP(MF); 498 } 499 500 // needsStackRealignment - true if storage within the function requires the 501 // stack pointer to be aligned more than the normal calling convention calls 502 // for. 503 virtual bool needsStackRealignment(const MachineFunction &MF) const { 504 return false; 505 } 506 507 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the 508 /// frame setup/destroy instructions if they exist (-1 otherwise). Some 509 /// targets use pseudo instructions in order to abstract away the difference 510 /// between operating with a frame pointer and operating without, through the 511 /// use of these two instructions. 512 /// 513 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } 514 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } 515 516 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog 517 /// code insertion to eliminate call frame setup and destroy pseudo 518 /// instructions (but only if the Target is using them). It is responsible 519 /// for eliminating these instructions, replacing them with concrete 520 /// instructions. This method need only be implemented if using call frame 521 /// setup/destroy pseudo instructions. 522 /// 523 virtual void 524 eliminateCallFramePseudoInstr(MachineFunction &MF, 525 MachineBasicBlock &MBB, 526 MachineBasicBlock::iterator MI) const { 527 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 && 528 "eliminateCallFramePseudoInstr must be implemented if using" 529 " call frame setup/destroy pseudo instructions!"); 530 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!"); 531 } 532 533 /// processFunctionBeforeCalleeSavedScan - This method is called immediately 534 /// before PrologEpilogInserter scans the physical registers used to determine 535 /// what callee saved registers should be spilled. This method is optional. 536 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 537 RegScavenger *RS = NULL) const { 538 539 } 540 541 /// processFunctionBeforeFrameFinalized - This method is called immediately 542 /// before the specified functions frame layout (MF.getFrameInfo()) is 543 /// finalized. Once the frame is finalized, MO_FrameIndex operands are 544 /// replaced with direct constants. This method is optional. 545 /// 546 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const { 547 } 548 549 /// eliminateFrameIndex - This method must be overriden to eliminate abstract 550 /// frame indices from instructions which may use them. The instruction 551 /// referenced by the iterator contains an MO_FrameIndex operand which must be 552 /// eliminated by this method. This method may modify or replace the 553 /// specified instruction, as long as it keeps the iterator pointing the the 554 /// finished product. SPAdj is the SP adjustment due to call frame setup 555 /// instruction. 556 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, 557 int SPAdj, RegScavenger *RS=NULL) const = 0; 558 559 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into 560 /// the function. 561 virtual void emitPrologue(MachineFunction &MF) const = 0; 562 virtual void emitEpilogue(MachineFunction &MF, 563 MachineBasicBlock &MBB) const = 0; 564 565 //===--------------------------------------------------------------------===// 566 /// Debug information queries. 567 568 /// getDwarfRegNum - Map a target register to an equivalent dwarf register 569 /// number. Returns -1 if there is no equivalent value. The second 570 /// parameter allows targets to use different numberings for EH info and 571 /// debugging info. 572 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0; 573 574 /// getFrameRegister - This method should return the register used as a base 575 /// for values allocated in the current stack frame. 576 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0; 577 578 /// getFrameIndexOffset - Returns the displacement from the frame register to 579 /// the stack frame of the specified index. 580 virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const; 581 582 /// getRARegister - This method should return the register where the return 583 /// address can be found. 584 virtual unsigned getRARegister() const = 0; 585 586 /// getInitialFrameState - Returns a list of machine moves that are assumed 587 /// on entry to all functions. Note that LabelID is ignored (assumed to be 588 /// the beginning of the function.) 589 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const; 590}; 591 592// This is useful when building IndexedMaps keyed on virtual registers 593struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> { 594 unsigned operator()(unsigned Reg) const { 595 return Reg - TargetRegisterInfo::FirstVirtualRegister; 596 } 597}; 598 599} // End llvm namespace 600 601#endif 602