TargetRegisterInfo.h revision 536ab130ec95cbb7bf30530251dafa7dfecc8471
1//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes an abstract interface used to get information about a 11// target machines register file. This information is used for a variety of 12// purposed, especially register allocation. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_TARGET_TARGETREGISTERINFO_H 17#define LLVM_TARGET_TARGETREGISTERINFO_H 18 19#include "llvm/CodeGen/MachineBasicBlock.h" 20#include "llvm/CodeGen/ValueTypes.h" 21#include <cassert> 22#include <functional> 23 24namespace llvm { 25 26class BitVector; 27class MachineFunction; 28class MachineMove; 29class RegScavenger; 30 31/// TargetRegisterDesc - This record contains all of the information known about 32/// a particular register. The AliasSet field (if not null) contains a pointer 33/// to a Zero terminated array of registers that this register aliases. This is 34/// needed for architectures like X86 which have AL alias AX alias EAX. 35/// Registers that this does not apply to simply should set this to null. 36/// The SubRegs field is a zero terminated array of registers that are 37/// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX. 38/// The SuperRegs field is a zero terminated array of registers that are 39/// super-registers of the specific register, e.g. RAX, EAX, are super-registers 40/// of AX. 41/// 42struct TargetRegisterDesc { 43 const char *AsmName; // Assembly language name for the register 44 const char *Name; // Printable name for the reg (for debugging) 45 const unsigned *AliasSet; // Register Alias Set, described above 46 const unsigned *SubRegs; // Sub-register set, described above 47 const unsigned *SuperRegs; // Super-register set, described above 48}; 49 50class TargetRegisterClass { 51public: 52 typedef const unsigned* iterator; 53 typedef const unsigned* const_iterator; 54 55 typedef const MVT* vt_iterator; 56 typedef const TargetRegisterClass* const * sc_iterator; 57private: 58 unsigned ID; 59 bool isSubClass; 60 const vt_iterator VTs; 61 const sc_iterator SubClasses; 62 const sc_iterator SuperClasses; 63 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes 64 const int CopyCost; 65 const iterator RegsBegin, RegsEnd; 66public: 67 TargetRegisterClass(unsigned id, 68 const MVT *vts, 69 const TargetRegisterClass * const *subcs, 70 const TargetRegisterClass * const *supcs, 71 unsigned RS, unsigned Al, int CC, 72 iterator RB, iterator RE) 73 : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs), 74 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {} 75 virtual ~TargetRegisterClass() {} // Allow subclasses 76 77 /// getID() - Return the register class ID number. 78 /// 79 unsigned getID() const { return ID; } 80 81 /// begin/end - Return all of the registers in this class. 82 /// 83 iterator begin() const { return RegsBegin; } 84 iterator end() const { return RegsEnd; } 85 86 /// getNumRegs - Return the number of registers in this class. 87 /// 88 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); } 89 90 /// getRegister - Return the specified register in the class. 91 /// 92 unsigned getRegister(unsigned i) const { 93 assert(i < getNumRegs() && "Register number out of range!"); 94 return RegsBegin[i]; 95 } 96 97 /// contains - Return true if the specified register is included in this 98 /// register class. 99 bool contains(unsigned Reg) const { 100 for (iterator I = begin(), E = end(); I != E; ++I) 101 if (*I == Reg) return true; 102 return false; 103 } 104 105 /// hasType - return true if this TargetRegisterClass has the ValueType vt. 106 /// 107 bool hasType(MVT vt) const { 108 for(int i = 0; VTs[i] != MVT::Other; ++i) 109 if (VTs[i] == vt) 110 return true; 111 return false; 112 } 113 114 /// vt_begin / vt_end - Loop over all of the value types that can be 115 /// represented by values in this register class. 116 vt_iterator vt_begin() const { 117 return VTs; 118 } 119 120 vt_iterator vt_end() const { 121 vt_iterator I = VTs; 122 while (*I != MVT::Other) ++I; 123 return I; 124 } 125 126 /// hasSubClass - return true if the specified TargetRegisterClass is a 127 /// sub-register class of this TargetRegisterClass. 128 bool hasSubClass(const TargetRegisterClass *cs) const { 129 for (int i = 0; SubClasses[i] != NULL; ++i) 130 if (SubClasses[i] == cs) 131 return true; 132 return false; 133 } 134 135 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of 136 /// this register class. 137 sc_iterator subclasses_begin() const { 138 return SubClasses; 139 } 140 141 sc_iterator subclasses_end() const { 142 sc_iterator I = SubClasses; 143 while (*I != NULL) ++I; 144 return I; 145 } 146 147 /// hasSuperClass - return true if the specified TargetRegisterClass is a 148 /// super-register class of this TargetRegisterClass. 149 bool hasSuperClass(const TargetRegisterClass *cs) const { 150 for (int i = 0; SuperClasses[i] != NULL; ++i) 151 if (SuperClasses[i] == cs) 152 return true; 153 return false; 154 } 155 156 /// superclasses_begin / superclasses_end - Loop over all of the super-classes 157 /// of this register class. 158 sc_iterator superclasses_begin() const { 159 return SuperClasses; 160 } 161 162 sc_iterator superclasses_end() const { 163 sc_iterator I = SuperClasses; 164 while (*I != NULL) ++I; 165 return I; 166 } 167 168 /// allocation_order_begin/end - These methods define a range of registers 169 /// which specify the registers in this class that are valid to register 170 /// allocate, and the preferred order to allocate them in. For example, 171 /// callee saved registers should be at the end of the list, because it is 172 /// cheaper to allocate caller saved registers. 173 /// 174 /// These methods take a MachineFunction argument, which can be used to tune 175 /// the allocatable registers based on the characteristics of the function. 176 /// One simple example is that the frame pointer register can be used if 177 /// frame-pointer-elimination is performed. 178 /// 179 /// By default, these methods return all registers in the class. 180 /// 181 virtual iterator allocation_order_begin(const MachineFunction &MF) const { 182 return begin(); 183 } 184 virtual iterator allocation_order_end(const MachineFunction &MF) const { 185 return end(); 186 } 187 188 189 190 /// getSize - Return the size of the register in bytes, which is also the size 191 /// of a stack slot allocated to hold a spilled copy of this register. 192 unsigned getSize() const { return RegSize; } 193 194 /// getAlignment - Return the minimum required alignment for a register of 195 /// this class. 196 unsigned getAlignment() const { return Alignment; } 197 198 /// getCopyCost - Return the cost of copying a value between two registers in 199 /// this class. 200 int getCopyCost() const { return CopyCost; } 201}; 202 203 204/// TargetRegisterInfo base class - We assume that the target defines a static 205/// array of TargetRegisterDesc objects that represent all of the machine 206/// registers that the target has. As such, we simply have to track a pointer 207/// to this array so that we can turn register number into a register 208/// descriptor. 209/// 210class TargetRegisterInfo { 211protected: 212 const unsigned* SubregHash; 213 const unsigned SubregHashSize; 214public: 215 typedef const TargetRegisterClass * const * regclass_iterator; 216private: 217 const TargetRegisterDesc *Desc; // Pointer to the descriptor array 218 unsigned NumRegs; // Number of entries in the array 219 220 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 221 222 int CallFrameSetupOpcode, CallFrameDestroyOpcode; 223protected: 224 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR, 225 regclass_iterator RegClassBegin, 226 regclass_iterator RegClassEnd, 227 int CallFrameSetupOpcode = -1, 228 int CallFrameDestroyOpcode = -1, 229 const unsigned* subregs = 0, 230 const unsigned subregsize = 0); 231 virtual ~TargetRegisterInfo(); 232public: 233 234 enum { // Define some target independent constants 235 /// NoRegister - This physical register is not a real target register. It 236 /// is useful as a sentinal. 237 NoRegister = 0, 238 239 /// FirstVirtualRegister - This is the first register number that is 240 /// considered to be a 'virtual' register, which is part of the SSA 241 /// namespace. This must be the same for all targets, which means that each 242 /// target is limited to 1024 registers. 243 FirstVirtualRegister = 1024 244 }; 245 246 /// isPhysicalRegister - Return true if the specified register number is in 247 /// the physical register namespace. 248 static bool isPhysicalRegister(unsigned Reg) { 249 assert(Reg && "this is not a register!"); 250 return Reg < FirstVirtualRegister; 251 } 252 253 /// isVirtualRegister - Return true if the specified register number is in 254 /// the virtual register namespace. 255 static bool isVirtualRegister(unsigned Reg) { 256 assert(Reg && "this is not a register!"); 257 return Reg >= FirstVirtualRegister; 258 } 259 260 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical 261 /// register of the given type. If type is MVT::Other, then just return any 262 /// register class the register belongs to. 263 const TargetRegisterClass *getPhysicalRegisterRegClass(unsigned Reg, 264 MVT VT = MVT::Other) const; 265 266 /// getAllocatableSet - Returns a bitset indexed by register number 267 /// indicating if a register is allocatable or not. If a register class is 268 /// specified, returns the subset for the class. 269 BitVector getAllocatableSet(MachineFunction &MF, 270 const TargetRegisterClass *RC = NULL) const; 271 272 const TargetRegisterDesc &operator[](unsigned RegNo) const { 273 assert(RegNo < NumRegs && 274 "Attempting to access record for invalid register number!"); 275 return Desc[RegNo]; 276 } 277 278 /// Provide a get method, equivalent to [], but more useful if we have a 279 /// pointer to this object. 280 /// 281 const TargetRegisterDesc &get(unsigned RegNo) const { 282 return operator[](RegNo); 283 } 284 285 /// getAliasSet - Return the set of registers aliased by the specified 286 /// register, or a null list of there are none. The list returned is zero 287 /// terminated. 288 /// 289 const unsigned *getAliasSet(unsigned RegNo) const { 290 return get(RegNo).AliasSet; 291 } 292 293 /// getSubRegisters - Return the list of registers that are sub-registers of 294 /// the specified register, or a null list of there are none. The list 295 /// returned is zero terminated and sorted according to super-sub register 296 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH. 297 /// 298 const unsigned *getSubRegisters(unsigned RegNo) const { 299 return get(RegNo).SubRegs; 300 } 301 302 /// getSuperRegisters - Return the list of registers that are super-registers 303 /// of the specified register, or a null list of there are none. The list 304 /// returned is zero terminated and sorted according to super-sub register 305 /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX. 306 /// 307 const unsigned *getSuperRegisters(unsigned RegNo) const { 308 return get(RegNo).SuperRegs; 309 } 310 311 /// getAsmName - Return the symbolic target-specific name for the 312 /// specified physical register. 313 const char *getAsmName(unsigned RegNo) const { 314 return get(RegNo).AsmName; 315 } 316 317 /// getName - Return the human-readable symbolic target-specific name for the 318 /// specified physical register. 319 const char *getName(unsigned RegNo) const { 320 return get(RegNo).Name; 321 } 322 323 /// getNumRegs - Return the number of registers this target has (useful for 324 /// sizing arrays holding per register information) 325 unsigned getNumRegs() const { 326 return NumRegs; 327 } 328 329 /// areAliases - Returns true if the two registers alias each other, false 330 /// otherwise 331 bool areAliases(unsigned regA, unsigned regB) const { 332 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias) 333 if (*Alias == regB) return true; 334 return false; 335 } 336 337 /// regsOverlap - Returns true if the two registers are equal or alias each 338 /// other. The registers may be virtual register. 339 bool regsOverlap(unsigned regA, unsigned regB) const { 340 if (regA == regB) 341 return true; 342 343 if (isVirtualRegister(regA) || isVirtualRegister(regB)) 344 return false; 345 return areAliases(regA, regB); 346 } 347 348 /// isSubRegister - Returns true if regB is a sub-register of regA. 349 /// 350 bool isSubRegister(unsigned regA, unsigned regB) const { 351 // SubregHash is a simple quadratically probed hash table. 352 size_t index = (regA + regB * 37) & (SubregHashSize-1); 353 unsigned ProbeAmt = 2; 354 while (SubregHash[index*2] != 0 && 355 SubregHash[index*2+1] != 0) { 356 if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB) 357 return true; 358 359 index = (index + ProbeAmt) & (SubregHashSize-1); 360 ProbeAmt += 2; 361 } 362 363 return false; 364 } 365 366 /// isSuperRegister - Returns true if regB is a super-register of regA. 367 /// 368 bool isSuperRegister(unsigned regA, unsigned regB) const { 369 for (const unsigned *SR = getSuperRegisters(regA); *SR; ++SR) 370 if (*SR == regB) return true; 371 return false; 372 } 373 374 /// getCalleeSavedRegs - Return a null-terminated list of all of the 375 /// callee saved registers on this target. The register should be in the 376 /// order of desired callee-save stack frame offset. The first register is 377 /// closed to the incoming stack pointer if stack grows down, and vice versa. 378 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0) 379 const = 0; 380 381 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred 382 /// register classes to spill each callee saved register with. The order and 383 /// length of this list match the getCalleeSaveRegs() list. 384 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses( 385 const MachineFunction *MF) const =0; 386 387 /// getReservedRegs - Returns a bitset indexed by physical register number 388 /// indicating if a register is a special register that has particular uses 389 /// and should be considered unavailable at all times, e.g. SP, RA. This is 390 /// used by register scavenger to determine what registers are free. 391 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 392 393 /// getSubReg - Returns the physical register number of sub-register "Index" 394 /// for physical register RegNo. Return zero if the sub-register does not 395 /// exist. 396 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0; 397 398 //===--------------------------------------------------------------------===// 399 // Register Class Information 400 // 401 402 /// Register class iterators 403 /// 404 regclass_iterator regclass_begin() const { return RegClassBegin; } 405 regclass_iterator regclass_end() const { return RegClassEnd; } 406 407 unsigned getNumRegClasses() const { 408 return (unsigned)(regclass_end()-regclass_begin()); 409 } 410 411 /// getRegClass - Returns the register class associated with the enumeration 412 /// value. See class TargetOperandInfo. 413 const TargetRegisterClass *getRegClass(unsigned i) const { 414 assert(i <= getNumRegClasses() && "Register Class ID out of range"); 415 return i ? RegClassBegin[i - 1] : NULL; 416 } 417 418 //===--------------------------------------------------------------------===// 419 // Interfaces used by the register allocator and stack frame 420 // manipulation passes to move data around between registers, 421 // immediates and memory. FIXME: Move these to TargetInstrInfo.h. 422 // 423 424 /// getCrossCopyRegClass - Returns a legal register class to copy a register 425 /// in the specified class to or from. Returns NULL if it is possible to copy 426 /// between a two registers of the specified class. 427 virtual const TargetRegisterClass * 428 getCrossCopyRegClass(const TargetRegisterClass *RC) const { 429 return NULL; 430 } 431 432 /// targetHandlesStackFrameRounding - Returns true if the target is 433 /// responsible for rounding up the stack frame (probably at emitPrologue 434 /// time). 435 virtual bool targetHandlesStackFrameRounding() const { 436 return false; 437 } 438 439 /// requiresRegisterScavenging - returns true if the target requires (and can 440 /// make use of) the register scavenger. 441 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 442 return false; 443 } 444 445 /// hasFP - Return true if the specified function should have a dedicated 446 /// frame pointer register. For most targets this is true only if the function 447 /// has variable sized allocas or if frame pointer elimination is disabled. 448 virtual bool hasFP(const MachineFunction &MF) const = 0; 449 450 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is 451 // not required, we reserve argument space for call sites in the function 452 // immediately on entry to the current function. This eliminates the need for 453 // add/sub sp brackets around call sites. Returns true if the call frame is 454 // included as part of the stack frame. 455 virtual bool hasReservedCallFrame(MachineFunction &MF) const { 456 return !hasFP(MF); 457 } 458 459 // needsStackRealignment - true if storage within the function requires the 460 // stack pointer to be aligned more than the normal calling convention calls 461 // for. 462 virtual bool needsStackRealignment(const MachineFunction &MF) const { 463 return false; 464 } 465 466 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the 467 /// frame setup/destroy instructions if they exist (-1 otherwise). Some 468 /// targets use pseudo instructions in order to abstract away the difference 469 /// between operating with a frame pointer and operating without, through the 470 /// use of these two instructions. 471 /// 472 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } 473 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } 474 475 476 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog 477 /// code insertion to eliminate call frame setup and destroy pseudo 478 /// instructions (but only if the Target is using them). It is responsible 479 /// for eliminating these instructions, replacing them with concrete 480 /// instructions. This method need only be implemented if using call frame 481 /// setup/destroy pseudo instructions. 482 /// 483 virtual void 484 eliminateCallFramePseudoInstr(MachineFunction &MF, 485 MachineBasicBlock &MBB, 486 MachineBasicBlock::iterator MI) const { 487 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 && 488 "eliminateCallFramePseudoInstr must be implemented if using" 489 " call frame setup/destroy pseudo instructions!"); 490 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!"); 491 } 492 493 /// processFunctionBeforeCalleeSavedScan - This method is called immediately 494 /// before PrologEpilogInserter scans the physical registers used to determine 495 /// what callee saved registers should be spilled. This method is optional. 496 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 497 RegScavenger *RS = NULL) const { 498 499 } 500 501 /// processFunctionBeforeFrameFinalized - This method is called immediately 502 /// before the specified functions frame layout (MF.getFrameInfo()) is 503 /// finalized. Once the frame is finalized, MO_FrameIndex operands are 504 /// replaced with direct constants. This method is optional. 505 /// 506 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const { 507 } 508 509 /// eliminateFrameIndex - This method must be overriden to eliminate abstract 510 /// frame indices from instructions which may use them. The instruction 511 /// referenced by the iterator contains an MO_FrameIndex operand which must be 512 /// eliminated by this method. This method may modify or replace the 513 /// specified instruction, as long as it keeps the iterator pointing the the 514 /// finished product. SPAdj is the SP adjustment due to call frame setup 515 /// instruction. 516 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, 517 int SPAdj, RegScavenger *RS=NULL) const = 0; 518 519 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into 520 /// the function. 521 virtual void emitPrologue(MachineFunction &MF) const = 0; 522 virtual void emitEpilogue(MachineFunction &MF, 523 MachineBasicBlock &MBB) const = 0; 524 525 //===--------------------------------------------------------------------===// 526 /// Debug information queries. 527 528 /// getDwarfRegNum - Map a target register to an equivalent dwarf register 529 /// number. Returns -1 if there is no equivalent value. The second 530 /// parameter allows targets to use different numberings for EH info and 531 /// debugging info. 532 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0; 533 534 /// getFrameRegister - This method should return the register used as a base 535 /// for values allocated in the current stack frame. 536 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0; 537 538 /// getFrameIndexOffset - Returns the displacement from the frame register to 539 /// the stack frame of the specified index. 540 virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const; 541 542 /// getRARegister - This method should return the register where the return 543 /// address can be found. 544 virtual unsigned getRARegister() const = 0; 545 546 /// getInitialFrameState - Returns a list of machine moves that are assumed 547 /// on entry to all functions. Note that LabelID is ignored (assumed to be 548 /// the beginning of the function.) 549 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const; 550}; 551 552// This is useful when building IndexedMaps keyed on virtual registers 553struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> { 554 unsigned operator()(unsigned Reg) const { 555 return Reg - TargetRegisterInfo::FirstVirtualRegister; 556 } 557}; 558 559} // End llvm namespace 560 561#endif 562