TargetRegisterInfo.h revision 976ef86689ed065361a748f81c44ca3510af2202
1//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes an abstract interface used to get information about a 11// target machines register file. This information is used for a variety of 12// purposed, especially register allocation. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_TARGET_TARGETREGISTERINFO_H 17#define LLVM_TARGET_TARGETREGISTERINFO_H 18 19#include "llvm/CodeGen/MachineBasicBlock.h" 20#include "llvm/CodeGen/ValueTypes.h" 21#include "llvm/ADT/DenseSet.h" 22#include <cassert> 23#include <functional> 24 25namespace llvm { 26 27class BitVector; 28class MachineFunction; 29class MachineMove; 30class RegScavenger; 31template<class T> class SmallVectorImpl; 32class raw_ostream; 33 34/// TargetRegisterDesc - This record contains all of the information known about 35/// a particular register. The Overlaps field contains a pointer to a zero 36/// terminated array of registers that this register aliases, starting with 37/// itself. This is needed for architectures like X86 which have AL alias AX 38/// alias EAX. The SubRegs field is a zero terminated array of registers that 39/// are sub-registers of the specific register, e.g. AL, AH are sub-registers of 40/// AX. The SuperRegs field is a zero terminated array of registers that are 41/// super-registers of the specific register, e.g. RAX, EAX, are super-registers 42/// of AX. 43/// 44struct TargetRegisterDesc { 45 const char *Name; // Printable name for the reg (for debugging) 46 const unsigned *Overlaps; // Overlapping registers, described above 47 const unsigned *SubRegs; // Sub-register set, described above 48 const unsigned *SuperRegs; // Super-register set, described above 49}; 50 51class TargetRegisterClass { 52public: 53 typedef const unsigned* iterator; 54 typedef const unsigned* const_iterator; 55 56 typedef const EVT* vt_iterator; 57 typedef const TargetRegisterClass* const * sc_iterator; 58private: 59 unsigned ID; 60 const char *Name; 61 const vt_iterator VTs; 62 const sc_iterator SubClasses; 63 const sc_iterator SuperClasses; 64 const sc_iterator SubRegClasses; 65 const sc_iterator SuperRegClasses; 66 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes 67 const int CopyCost; 68 const iterator RegsBegin, RegsEnd; 69 DenseSet<unsigned> RegSet; 70public: 71 TargetRegisterClass(unsigned id, 72 const char *name, 73 const EVT *vts, 74 const TargetRegisterClass * const *subcs, 75 const TargetRegisterClass * const *supcs, 76 const TargetRegisterClass * const *subregcs, 77 const TargetRegisterClass * const *superregcs, 78 unsigned RS, unsigned Al, int CC, 79 iterator RB, iterator RE) 80 : ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs), 81 SubRegClasses(subregcs), SuperRegClasses(superregcs), 82 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) { 83 for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I) 84 RegSet.insert(*I); 85 } 86 virtual ~TargetRegisterClass() {} // Allow subclasses 87 88 /// getID() - Return the register class ID number. 89 /// 90 unsigned getID() const { return ID; } 91 92 /// getName() - Return the register class name for debugging. 93 /// 94 const char *getName() const { return Name; } 95 96 /// begin/end - Return all of the registers in this class. 97 /// 98 iterator begin() const { return RegsBegin; } 99 iterator end() const { return RegsEnd; } 100 101 /// getNumRegs - Return the number of registers in this class. 102 /// 103 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); } 104 105 /// getRegister - Return the specified register in the class. 106 /// 107 unsigned getRegister(unsigned i) const { 108 assert(i < getNumRegs() && "Register number out of range!"); 109 return RegsBegin[i]; 110 } 111 112 /// contains - Return true if the specified register is included in this 113 /// register class. This does not include virtual registers. 114 bool contains(unsigned Reg) const { 115 return RegSet.count(Reg); 116 } 117 118 /// contains - Return true if both registers are in this class. 119 bool contains(unsigned Reg1, unsigned Reg2) const { 120 return contains(Reg1) && contains(Reg2); 121 } 122 123 /// hasType - return true if this TargetRegisterClass has the ValueType vt. 124 /// 125 bool hasType(EVT vt) const { 126 for(int i = 0; VTs[i] != MVT::Other; ++i) 127 if (VTs[i] == vt) 128 return true; 129 return false; 130 } 131 132 /// vt_begin / vt_end - Loop over all of the value types that can be 133 /// represented by values in this register class. 134 vt_iterator vt_begin() const { 135 return VTs; 136 } 137 138 vt_iterator vt_end() const { 139 vt_iterator I = VTs; 140 while (*I != MVT::Other) ++I; 141 return I; 142 } 143 144 /// subregclasses_begin / subregclasses_end - Loop over all of 145 /// the subreg register classes of this register class. 146 sc_iterator subregclasses_begin() const { 147 return SubRegClasses; 148 } 149 150 sc_iterator subregclasses_end() const { 151 sc_iterator I = SubRegClasses; 152 while (*I != NULL) ++I; 153 return I; 154 } 155 156 /// getSubRegisterRegClass - Return the register class of subregisters with 157 /// index SubIdx, or NULL if no such class exists. 158 const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const { 159 assert(SubIdx>0 && "Invalid subregister index"); 160 return SubRegClasses[SubIdx-1]; 161 } 162 163 /// superregclasses_begin / superregclasses_end - Loop over all of 164 /// the superreg register classes of this register class. 165 sc_iterator superregclasses_begin() const { 166 return SuperRegClasses; 167 } 168 169 sc_iterator superregclasses_end() const { 170 sc_iterator I = SuperRegClasses; 171 while (*I != NULL) ++I; 172 return I; 173 } 174 175 /// hasSubClass - return true if the specified TargetRegisterClass 176 /// is a proper subset of this TargetRegisterClass. 177 bool hasSubClass(const TargetRegisterClass *cs) const { 178 for (int i = 0; SubClasses[i] != NULL; ++i) 179 if (SubClasses[i] == cs) 180 return true; 181 return false; 182 } 183 184 /// subclasses_begin / subclasses_end - Loop over all of the classes 185 /// that are proper subsets of this register class. 186 sc_iterator subclasses_begin() const { 187 return SubClasses; 188 } 189 190 sc_iterator subclasses_end() const { 191 sc_iterator I = SubClasses; 192 while (*I != NULL) ++I; 193 return I; 194 } 195 196 /// hasSuperClass - return true if the specified TargetRegisterClass is a 197 /// proper superset of this TargetRegisterClass. 198 bool hasSuperClass(const TargetRegisterClass *cs) const { 199 for (int i = 0; SuperClasses[i] != NULL; ++i) 200 if (SuperClasses[i] == cs) 201 return true; 202 return false; 203 } 204 205 /// superclasses_begin / superclasses_end - Loop over all of the classes 206 /// that are proper supersets of this register class. 207 sc_iterator superclasses_begin() const { 208 return SuperClasses; 209 } 210 211 sc_iterator superclasses_end() const { 212 sc_iterator I = SuperClasses; 213 while (*I != NULL) ++I; 214 return I; 215 } 216 217 /// isASubClass - return true if this TargetRegisterClass is a subset 218 /// class of at least one other TargetRegisterClass. 219 bool isASubClass() const { 220 return SuperClasses[0] != 0; 221 } 222 223 /// allocation_order_begin/end - These methods define a range of registers 224 /// which specify the registers in this class that are valid to register 225 /// allocate, and the preferred order to allocate them in. For example, 226 /// callee saved registers should be at the end of the list, because it is 227 /// cheaper to allocate caller saved registers. 228 /// 229 /// These methods take a MachineFunction argument, which can be used to tune 230 /// the allocatable registers based on the characteristics of the function, 231 /// subtarget, or other criteria. 232 /// 233 /// Register allocators should account for the fact that an allocation 234 /// order iterator may return a reserved register and always check 235 /// if the register is allocatable (getAllocatableSet()) before using it. 236 /// 237 /// By default, these methods return all registers in the class. 238 /// 239 virtual iterator allocation_order_begin(const MachineFunction &MF) const { 240 return begin(); 241 } 242 virtual iterator allocation_order_end(const MachineFunction &MF) const { 243 return end(); 244 } 245 246 /// getSize - Return the size of the register in bytes, which is also the size 247 /// of a stack slot allocated to hold a spilled copy of this register. 248 unsigned getSize() const { return RegSize; } 249 250 /// getAlignment - Return the minimum required alignment for a register of 251 /// this class. 252 unsigned getAlignment() const { return Alignment; } 253 254 /// getCopyCost - Return the cost of copying a value between two registers in 255 /// this class. A negative number means the register class is very expensive 256 /// to copy e.g. status flag register classes. 257 int getCopyCost() const { return CopyCost; } 258}; 259 260 261/// TargetRegisterInfo base class - We assume that the target defines a static 262/// array of TargetRegisterDesc objects that represent all of the machine 263/// registers that the target has. As such, we simply have to track a pointer 264/// to this array so that we can turn register number into a register 265/// descriptor. 266/// 267class TargetRegisterInfo { 268protected: 269 const unsigned* SubregHash; 270 const unsigned SubregHashSize; 271 const unsigned* AliasesHash; 272 const unsigned AliasesHashSize; 273public: 274 typedef const TargetRegisterClass * const * regclass_iterator; 275private: 276 const TargetRegisterDesc *Desc; // Pointer to the descriptor array 277 const char *const *SubRegIndexNames; // Names of subreg indexes. 278 unsigned NumRegs; // Number of entries in the array 279 280 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 281 282 int CallFrameSetupOpcode, CallFrameDestroyOpcode; 283 284protected: 285 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR, 286 regclass_iterator RegClassBegin, 287 regclass_iterator RegClassEnd, 288 const char *const *subregindexnames, 289 int CallFrameSetupOpcode = -1, 290 int CallFrameDestroyOpcode = -1, 291 const unsigned* subregs = 0, 292 const unsigned subregsize = 0, 293 const unsigned* aliases = 0, 294 const unsigned aliasessize = 0); 295 virtual ~TargetRegisterInfo(); 296public: 297 298 enum { // Define some target independent constants 299 /// NoRegister - This physical register is not a real target register. It 300 /// is useful as a sentinal. 301 NoRegister = 0, 302 303 /// FirstVirtualRegister - This is the first register number that is 304 /// considered to be a 'virtual' register, which is part of the SSA 305 /// namespace. This must be the same for all targets, which means that each 306 /// target is limited to this fixed number of registers. 307 FirstVirtualRegister = 16384 308 }; 309 310 /// isPhysicalRegister - Return true if the specified register number is in 311 /// the physical register namespace. 312 static bool isPhysicalRegister(unsigned Reg) { 313 assert(Reg && "this is not a register!"); 314 return Reg < FirstVirtualRegister; 315 } 316 317 /// isVirtualRegister - Return true if the specified register number is in 318 /// the virtual register namespace. 319 static bool isVirtualRegister(unsigned Reg) { 320 assert(Reg && "this is not a register!"); 321 return Reg >= FirstVirtualRegister; 322 } 323 324 /// printReg - Print a virtual or physical register on OS. 325 void printReg(unsigned Reg, raw_ostream &OS) const; 326 327 /// getMinimalPhysRegClass - Returns the Register Class of a physical 328 /// register of the given type, picking the most sub register class of 329 /// the right type that contains this physreg. 330 const TargetRegisterClass * 331 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const; 332 333 /// getAllocatableSet - Returns a bitset indexed by register number 334 /// indicating if a register is allocatable or not. If a register class is 335 /// specified, returns the subset for the class. 336 BitVector getAllocatableSet(const MachineFunction &MF, 337 const TargetRegisterClass *RC = NULL) const; 338 339 const TargetRegisterDesc &operator[](unsigned RegNo) const { 340 assert(RegNo < NumRegs && 341 "Attempting to access record for invalid register number!"); 342 return Desc[RegNo]; 343 } 344 345 /// Provide a get method, equivalent to [], but more useful if we have a 346 /// pointer to this object. 347 /// 348 const TargetRegisterDesc &get(unsigned RegNo) const { 349 return operator[](RegNo); 350 } 351 352 /// getAliasSet - Return the set of registers aliased by the specified 353 /// register, or a null list of there are none. The list returned is zero 354 /// terminated. 355 /// 356 const unsigned *getAliasSet(unsigned RegNo) const { 357 // The Overlaps set always begins with Reg itself. 358 return get(RegNo).Overlaps + 1; 359 } 360 361 /// getOverlaps - Return a list of registers that overlap Reg, including 362 /// itself. This is the same as the alias set except Reg is included in the 363 /// list. 364 /// These are exactly the registers in { x | regsOverlap(x, Reg) }. 365 /// 366 const unsigned *getOverlaps(unsigned RegNo) const { 367 return get(RegNo).Overlaps; 368 } 369 370 /// getSubRegisters - Return the list of registers that are sub-registers of 371 /// the specified register, or a null list of there are none. The list 372 /// returned is zero terminated and sorted according to super-sub register 373 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH. 374 /// 375 const unsigned *getSubRegisters(unsigned RegNo) const { 376 return get(RegNo).SubRegs; 377 } 378 379 /// getSuperRegisters - Return the list of registers that are super-registers 380 /// of the specified register, or a null list of there are none. The list 381 /// returned is zero terminated and sorted according to super-sub register 382 /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX. 383 /// 384 const unsigned *getSuperRegisters(unsigned RegNo) const { 385 return get(RegNo).SuperRegs; 386 } 387 388 /// getName - Return the human-readable symbolic target-specific name for the 389 /// specified physical register. 390 const char *getName(unsigned RegNo) const { 391 return get(RegNo).Name; 392 } 393 394 /// getNumRegs - Return the number of registers this target has (useful for 395 /// sizing arrays holding per register information) 396 unsigned getNumRegs() const { 397 return NumRegs; 398 } 399 400 /// getSubRegIndexName - Return the human-readable symbolic target-specific 401 /// name for the specified SubRegIndex. 402 const char *getSubRegIndexName(unsigned SubIdx) const { 403 assert(SubIdx && "This is not a subregister index"); 404 return SubRegIndexNames[SubIdx-1]; 405 } 406 407 /// regsOverlap - Returns true if the two registers are equal or alias each 408 /// other. The registers may be virtual register. 409 bool regsOverlap(unsigned regA, unsigned regB) const { 410 if (regA == regB) 411 return true; 412 413 if (isVirtualRegister(regA) || isVirtualRegister(regB)) 414 return false; 415 416 // regA and regB are distinct physical registers. Do they alias? 417 size_t index = (regA + regB * 37) & (AliasesHashSize-1); 418 unsigned ProbeAmt = 0; 419 while (AliasesHash[index*2] != 0 && 420 AliasesHash[index*2+1] != 0) { 421 if (AliasesHash[index*2] == regA && AliasesHash[index*2+1] == regB) 422 return true; 423 424 index = (index + ProbeAmt) & (AliasesHashSize-1); 425 ProbeAmt += 2; 426 } 427 428 return false; 429 } 430 431 /// isSubRegister - Returns true if regB is a sub-register of regA. 432 /// 433 bool isSubRegister(unsigned regA, unsigned regB) const { 434 // SubregHash is a simple quadratically probed hash table. 435 size_t index = (regA + regB * 37) & (SubregHashSize-1); 436 unsigned ProbeAmt = 2; 437 while (SubregHash[index*2] != 0 && 438 SubregHash[index*2+1] != 0) { 439 if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB) 440 return true; 441 442 index = (index + ProbeAmt) & (SubregHashSize-1); 443 ProbeAmt += 2; 444 } 445 446 return false; 447 } 448 449 /// isSuperRegister - Returns true if regB is a super-register of regA. 450 /// 451 bool isSuperRegister(unsigned regA, unsigned regB) const { 452 return isSubRegister(regB, regA); 453 } 454 455 /// getCalleeSavedRegs - Return a null-terminated list of all of the 456 /// callee saved registers on this target. The register should be in the 457 /// order of desired callee-save stack frame offset. The first register is 458 /// closed to the incoming stack pointer if stack grows down, and vice versa. 459 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0) 460 const = 0; 461 462 463 /// getReservedRegs - Returns a bitset indexed by physical register number 464 /// indicating if a register is a special register that has particular uses 465 /// and should be considered unavailable at all times, e.g. SP, RA. This is 466 /// used by register scavenger to determine what registers are free. 467 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 468 469 /// getSubReg - Returns the physical register number of sub-register "Index" 470 /// for physical register RegNo. Return zero if the sub-register does not 471 /// exist. 472 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0; 473 474 /// getSubRegIndex - For a given register pair, return the sub-register index 475 /// if the second register is a sub-register of the first. Return zero 476 /// otherwise. 477 virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0; 478 479 /// getMatchingSuperReg - Return a super-register of the specified register 480 /// Reg so its sub-register of index SubIdx is Reg. 481 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 482 const TargetRegisterClass *RC) const { 483 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs) 484 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR)) 485 return SR; 486 return 0; 487 } 488 489 /// canCombineSubRegIndices - Given a register class and a list of 490 /// subregister indices, return true if it's possible to combine the 491 /// subregister indices into one that corresponds to a larger 492 /// subregister. Return the new subregister index by reference. Note the 493 /// new index may be zero if the given subregisters can be combined to 494 /// form the whole register. 495 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC, 496 SmallVectorImpl<unsigned> &SubIndices, 497 unsigned &NewSubIdx) const { 498 return 0; 499 } 500 501 /// getMatchingSuperRegClass - Return a subclass of the specified register 502 /// class A so that each register in it has a sub-register of the 503 /// specified sub-register index which is in the specified register class B. 504 virtual const TargetRegisterClass * 505 getMatchingSuperRegClass(const TargetRegisterClass *A, 506 const TargetRegisterClass *B, unsigned Idx) const { 507 return 0; 508 } 509 510 /// composeSubRegIndices - Return the subregister index you get from composing 511 /// two subregister indices. 512 /// 513 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) 514 /// returns c. Note that composeSubRegIndices does not tell you about illegal 515 /// compositions. If R does not have a subreg a, or R:a does not have a subreg 516 /// b, composeSubRegIndices doesn't tell you. 517 /// 518 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has 519 /// ssub_0:S0 - ssub_3:S3 subregs. 520 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2. 521 /// 522 virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const { 523 // This default implementation is correct for most targets. 524 return b; 525 } 526 527 //===--------------------------------------------------------------------===// 528 // Register Class Information 529 // 530 531 /// Register class iterators 532 /// 533 regclass_iterator regclass_begin() const { return RegClassBegin; } 534 regclass_iterator regclass_end() const { return RegClassEnd; } 535 536 unsigned getNumRegClasses() const { 537 return (unsigned)(regclass_end()-regclass_begin()); 538 } 539 540 /// getRegClass - Returns the register class associated with the enumeration 541 /// value. See class TargetOperandInfo. 542 const TargetRegisterClass *getRegClass(unsigned i) const { 543 assert(i < getNumRegClasses() && "Register Class ID out of range"); 544 return RegClassBegin[i]; 545 } 546 547 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 548 /// values. If a target supports multiple different pointer register classes, 549 /// kind specifies which one is indicated. 550 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const { 551 assert(0 && "Target didn't implement getPointerRegClass!"); 552 return 0; // Must return a value in order to compile with VS 2005 553 } 554 555 /// getCrossCopyRegClass - Returns a legal register class to copy a register 556 /// in the specified class to or from. Returns NULL if it is possible to copy 557 /// between a two registers of the specified class. 558 virtual const TargetRegisterClass * 559 getCrossCopyRegClass(const TargetRegisterClass *RC) const { 560 return NULL; 561 } 562 563 /// getAllocationOrder - Returns the register allocation order for a specified 564 /// register class in the form of a pair of TargetRegisterClass iterators. 565 virtual std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator> 566 getAllocationOrder(const TargetRegisterClass *RC, 567 unsigned HintType, unsigned HintReg, 568 const MachineFunction &MF) const { 569 return std::make_pair(RC->allocation_order_begin(MF), 570 RC->allocation_order_end(MF)); 571 } 572 573 /// ResolveRegAllocHint - Resolves the specified register allocation hint 574 /// to a physical register. Returns the physical register if it is successful. 575 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg, 576 const MachineFunction &MF) const { 577 if (Type == 0 && Reg && isPhysicalRegister(Reg)) 578 return Reg; 579 return 0; 580 } 581 582 /// UpdateRegAllocHint - A callback to allow target a chance to update 583 /// register allocation hints when a register is "changed" (e.g. coalesced) 584 /// to another register. e.g. On ARM, some virtual registers should target 585 /// register pairs, if one of pair is coalesced to another register, the 586 /// allocation hint of the other half of the pair should be changed to point 587 /// to the new register. 588 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 589 MachineFunction &MF) const { 590 // Do nothing. 591 } 592 593 /// requiresRegisterScavenging - returns true if the target requires (and can 594 /// make use of) the register scavenger. 595 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 596 return false; 597 } 598 599 /// requiresFrameIndexScavenging - returns true if the target requires post 600 /// PEI scavenging of registers for materializing frame index constants. 601 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const { 602 return false; 603 } 604 605 /// requiresVirtualBaseRegisters - Returns true if the target wants the 606 /// LocalStackAllocation pass to be run and virtual base registers 607 /// used for more efficient stack access. 608 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const { 609 return false; 610 } 611 612 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in 613 /// the stack frame of the given function for the specified register. e.g. On 614 /// x86, if the frame register is required, the first fixed stack object is 615 /// reserved as its spill slot. This tells PEI not to create a new stack frame 616 /// object for the given register. It should be called only after 617 /// processFunctionBeforeCalleeSavedScan(). 618 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 619 int &FrameIdx) const { 620 return false; 621 } 622 623 /// needsStackRealignment - true if storage within the function requires the 624 /// stack pointer to be aligned more than the normal calling convention calls 625 /// for. 626 virtual bool needsStackRealignment(const MachineFunction &MF) const { 627 return false; 628 } 629 630 /// getFrameIndexInstrOffset - Get the offset from the referenced frame 631 /// index in the instruction, if the is one. 632 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, 633 int Idx) const { 634 return 0; 635 } 636 637 /// needsFrameBaseReg - Returns true if the instruction's frame index 638 /// reference would be better served by a base register other than FP 639 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 640 /// references it should create new base registers for. 641 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 642 return false; 643 } 644 645 /// materializeFrameBaseRegister - Insert defining instruction(s) for 646 /// BaseReg to be a pointer to FrameIdx before insertion point I. 647 virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB, 648 unsigned BaseReg, int FrameIdx, 649 int64_t Offset) const { 650 assert(0 && "materializeFrameBaseRegister does not exist on this target"); 651 } 652 653 /// resolveFrameIndex - Resolve a frame index operand of an instruction 654 /// to reference the indicated base register plus offset instead. 655 virtual void resolveFrameIndex(MachineBasicBlock::iterator I, 656 unsigned BaseReg, int64_t Offset) const { 657 assert(0 && "resolveFrameIndex does not exist on this target"); 658 } 659 660 /// isFrameOffsetLegal - Determine whether a given offset immediate is 661 /// encodable to resolve a frame index. 662 virtual bool isFrameOffsetLegal(const MachineInstr *MI, 663 int64_t Offset) const { 664 assert(0 && "isFrameOffsetLegal does not exist on this target"); 665 return false; // Must return a value in order to compile with VS 2005 666 } 667 668 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the 669 /// frame setup/destroy instructions if they exist (-1 otherwise). Some 670 /// targets use pseudo instructions in order to abstract away the difference 671 /// between operating with a frame pointer and operating without, through the 672 /// use of these two instructions. 673 /// 674 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } 675 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } 676 677 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog 678 /// code insertion to eliminate call frame setup and destroy pseudo 679 /// instructions (but only if the Target is using them). It is responsible 680 /// for eliminating these instructions, replacing them with concrete 681 /// instructions. This method need only be implemented if using call frame 682 /// setup/destroy pseudo instructions. 683 /// 684 virtual void 685 eliminateCallFramePseudoInstr(MachineFunction &MF, 686 MachineBasicBlock &MBB, 687 MachineBasicBlock::iterator MI) const { 688 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 && 689 "eliminateCallFramePseudoInstr must be implemented if using" 690 " call frame setup/destroy pseudo instructions!"); 691 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!"); 692 } 693 694 695 /// saveScavengerRegister - Spill the register so it can be used by the 696 /// register scavenger. Return true if the register was spilled, false 697 /// otherwise. If this function does not spill the register, the scavenger 698 /// will instead spill it to the emergency spill slot. 699 /// 700 virtual bool saveScavengerRegister(MachineBasicBlock &MBB, 701 MachineBasicBlock::iterator I, 702 MachineBasicBlock::iterator &UseMI, 703 const TargetRegisterClass *RC, 704 unsigned Reg) const { 705 return false; 706 } 707 708 /// eliminateFrameIndex - This method must be overriden to eliminate abstract 709 /// frame indices from instructions which may use them. The instruction 710 /// referenced by the iterator contains an MO_FrameIndex operand which must be 711 /// eliminated by this method. This method may modify or replace the 712 /// specified instruction, as long as it keeps the iterator pointing at the 713 /// finished product. SPAdj is the SP adjustment due to call frame setup 714 /// instruction. 715 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, 716 int SPAdj, RegScavenger *RS=NULL) const = 0; 717 718 //===--------------------------------------------------------------------===// 719 /// Debug information queries. 720 721 /// getDwarfRegNum - Map a target register to an equivalent dwarf register 722 /// number. Returns -1 if there is no equivalent value. The second 723 /// parameter allows targets to use different numberings for EH info and 724 /// debugging info. 725 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0; 726 727 /// getFrameRegister - This method should return the register used as a base 728 /// for values allocated in the current stack frame. 729 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0; 730 731 /// getRARegister - This method should return the register where the return 732 /// address can be found. 733 virtual unsigned getRARegister() const = 0; 734}; 735 736 737// This is useful when building IndexedMaps keyed on virtual registers 738struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> { 739 unsigned operator()(unsigned Reg) const { 740 return Reg - TargetRegisterInfo::FirstVirtualRegister; 741 } 742}; 743 744/// getCommonSubClass - find the largest common subclass of A and B. Return NULL 745/// if there is no common subclass. 746const TargetRegisterClass *getCommonSubClass(const TargetRegisterClass *A, 747 const TargetRegisterClass *B); 748 749} // End llvm namespace 750 751#endif 752