TargetRegisterInfo.h revision bd6dc3be1dac2d153f29927cad517af9e579b204
1//=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes an abstract interface used to get information about a 11// target machines register file. This information is used for a variety of 12// purposed, especially register allocation. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_TARGET_TARGETREGISTERINFO_H 17#define LLVM_TARGET_TARGETREGISTERINFO_H 18 19#include "llvm/MC/MCRegisterInfo.h" 20#include "llvm/CodeGen/MachineBasicBlock.h" 21#include "llvm/CodeGen/ValueTypes.h" 22#include "llvm/ADT/ArrayRef.h" 23#include "llvm/CallingConv.h" 24#include <cassert> 25#include <functional> 26 27namespace llvm { 28 29class BitVector; 30class MachineFunction; 31class RegScavenger; 32template<class T> class SmallVectorImpl; 33class raw_ostream; 34 35class TargetRegisterClass { 36public: 37 typedef const unsigned* iterator; 38 typedef const unsigned* const_iterator; 39 typedef const EVT* vt_iterator; 40 typedef const TargetRegisterClass* const * sc_iterator; 41private: 42 virtual void anchor(); 43 const MCRegisterClass *MC; 44 const vt_iterator VTs; 45 const unsigned *SubClassMask; 46 const sc_iterator SuperClasses; 47 const sc_iterator SuperRegClasses; 48public: 49 TargetRegisterClass(const MCRegisterClass *MC, const EVT *vts, 50 const unsigned *subcm, 51 const TargetRegisterClass * const *supcs, 52 const TargetRegisterClass * const *superregcs) 53 : MC(MC), VTs(vts), SubClassMask(subcm), SuperClasses(supcs), 54 SuperRegClasses(superregcs) {} 55 56 virtual ~TargetRegisterClass() {} // Allow subclasses 57 58 /// getID() - Return the register class ID number. 59 /// 60 unsigned getID() const { return MC->getID(); } 61 62 /// getName() - Return the register class name for debugging. 63 /// 64 const char *getName() const { return MC->getName(); } 65 66 /// begin/end - Return all of the registers in this class. 67 /// 68 iterator begin() const { return MC->begin(); } 69 iterator end() const { return MC->end(); } 70 71 /// getNumRegs - Return the number of registers in this class. 72 /// 73 unsigned getNumRegs() const { return MC->getNumRegs(); } 74 75 /// getRegister - Return the specified register in the class. 76 /// 77 unsigned getRegister(unsigned i) const { 78 return MC->getRegister(i); 79 } 80 81 /// contains - Return true if the specified register is included in this 82 /// register class. This does not include virtual registers. 83 bool contains(unsigned Reg) const { 84 return MC->contains(Reg); 85 } 86 87 /// contains - Return true if both registers are in this class. 88 bool contains(unsigned Reg1, unsigned Reg2) const { 89 return MC->contains(Reg1, Reg2); 90 } 91 92 /// getSize - Return the size of the register in bytes, which is also the size 93 /// of a stack slot allocated to hold a spilled copy of this register. 94 unsigned getSize() const { return MC->getSize(); } 95 96 /// getAlignment - Return the minimum required alignment for a register of 97 /// this class. 98 unsigned getAlignment() const { return MC->getAlignment(); } 99 100 /// getCopyCost - Return the cost of copying a value between two registers in 101 /// this class. A negative number means the register class is very expensive 102 /// to copy e.g. status flag register classes. 103 int getCopyCost() const { return MC->getCopyCost(); } 104 105 /// isAllocatable - Return true if this register class may be used to create 106 /// virtual registers. 107 bool isAllocatable() const { return MC->isAllocatable(); } 108 109 /// hasType - return true if this TargetRegisterClass has the ValueType vt. 110 /// 111 bool hasType(EVT vt) const { 112 for(int i = 0; VTs[i] != MVT::Other; ++i) 113 if (VTs[i] == vt) 114 return true; 115 return false; 116 } 117 118 /// vt_begin / vt_end - Loop over all of the value types that can be 119 /// represented by values in this register class. 120 vt_iterator vt_begin() const { 121 return VTs; 122 } 123 124 vt_iterator vt_end() const { 125 vt_iterator I = VTs; 126 while (*I != MVT::Other) ++I; 127 return I; 128 } 129 130 /// superregclasses_begin / superregclasses_end - Loop over all of 131 /// the superreg register classes of this register class. 132 sc_iterator superregclasses_begin() const { 133 return SuperRegClasses; 134 } 135 136 sc_iterator superregclasses_end() const { 137 sc_iterator I = SuperRegClasses; 138 while (*I != NULL) ++I; 139 return I; 140 } 141 142 /// hasSubClass - return true if the specified TargetRegisterClass 143 /// is a proper sub-class of this TargetRegisterClass. 144 bool hasSubClass(const TargetRegisterClass *RC) const { 145 return RC != this && hasSubClassEq(RC); 146 } 147 148 /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this 149 /// class. 150 bool hasSubClassEq(const TargetRegisterClass *RC) const { 151 unsigned ID = RC->getID(); 152 return (SubClassMask[ID / 32] >> (ID % 32)) & 1; 153 } 154 155 /// hasSuperClass - return true if the specified TargetRegisterClass is a 156 /// proper super-class of this TargetRegisterClass. 157 bool hasSuperClass(const TargetRegisterClass *RC) const { 158 return RC->hasSubClass(this); 159 } 160 161 /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this 162 /// class. 163 bool hasSuperClassEq(const TargetRegisterClass *RC) const { 164 return RC->hasSubClassEq(this); 165 } 166 167 /// getSubClassMask - Returns a bit vector of subclasses, including this one. 168 /// The vector is indexed by class IDs, see hasSubClassEq() above for how to 169 /// use it. 170 const unsigned *getSubClassMask() const { 171 return SubClassMask; 172 } 173 174 /// getSuperClasses - Returns a NULL terminated list of super-classes. The 175 /// classes are ordered by ID which is also a topological ordering from large 176 /// to small classes. The list does NOT include the current class. 177 sc_iterator getSuperClasses() const { 178 return SuperClasses; 179 } 180 181 /// isASubClass - return true if this TargetRegisterClass is a subset 182 /// class of at least one other TargetRegisterClass. 183 bool isASubClass() const { 184 return SuperClasses[0] != 0; 185 } 186 187 /// getRawAllocationOrder - Returns the preferred order for allocating 188 /// registers from this register class in MF. The raw order comes directly 189 /// from the .td file and may include reserved registers that are not 190 /// allocatable. Register allocators should also make sure to allocate 191 /// callee-saved registers only after all the volatiles are used. The 192 /// RegisterClassInfo class provides filtered allocation orders with 193 /// callee-saved registers moved to the end. 194 /// 195 /// The MachineFunction argument can be used to tune the allocatable 196 /// registers based on the characteristics of the function, subtarget, or 197 /// other criteria. 198 /// 199 /// By default, this method returns all registers in the class. 200 /// 201 virtual 202 ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction &MF) const { 203 return makeArrayRef(begin(), getNumRegs()); 204 } 205}; 206 207/// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about 208/// registers. These are used by codegen, not by MC. 209struct TargetRegisterInfoDesc { 210 unsigned CostPerUse; // Extra cost of instructions using register. 211 bool inAllocatableClass; // Register belongs to an allocatable regclass. 212}; 213 214/// TargetRegisterInfo base class - We assume that the target defines a static 215/// array of TargetRegisterDesc objects that represent all of the machine 216/// registers that the target has. As such, we simply have to track a pointer 217/// to this array so that we can turn register number into a register 218/// descriptor. 219/// 220class TargetRegisterInfo : public MCRegisterInfo { 221public: 222 typedef const TargetRegisterClass * const * regclass_iterator; 223private: 224 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen 225 const char *const *SubRegIndexNames; // Names of subreg indexes. 226 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 227 228protected: 229 TargetRegisterInfo(const TargetRegisterInfoDesc *ID, 230 regclass_iterator RegClassBegin, 231 regclass_iterator RegClassEnd, 232 const char *const *subregindexnames); 233 virtual ~TargetRegisterInfo(); 234public: 235 236 // Register numbers can represent physical registers, virtual registers, and 237 // sometimes stack slots. The unsigned values are divided into these ranges: 238 // 239 // 0 Not a register, can be used as a sentinel. 240 // [1;2^30) Physical registers assigned by TableGen. 241 // [2^30;2^31) Stack slots. (Rarely used.) 242 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo. 243 // 244 // Further sentinels can be allocated from the small negative integers. 245 // DenseMapInfo<unsigned> uses -1u and -2u. 246 247 /// isStackSlot - Sometimes it is useful the be able to store a non-negative 248 /// frame index in a variable that normally holds a register. isStackSlot() 249 /// returns true if Reg is in the range used for stack slots. 250 /// 251 /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack 252 /// slots, so if a variable may contains a stack slot, always check 253 /// isStackSlot() first. 254 /// 255 static bool isStackSlot(unsigned Reg) { 256 return int(Reg) >= (1 << 30); 257 } 258 259 /// stackSlot2Index - Compute the frame index from a register value 260 /// representing a stack slot. 261 static int stackSlot2Index(unsigned Reg) { 262 assert(isStackSlot(Reg) && "Not a stack slot"); 263 return int(Reg - (1u << 30)); 264 } 265 266 /// index2StackSlot - Convert a non-negative frame index to a stack slot 267 /// register value. 268 static unsigned index2StackSlot(int FI) { 269 assert(FI >= 0 && "Cannot hold a negative frame index."); 270 return FI + (1u << 30); 271 } 272 273 /// isPhysicalRegister - Return true if the specified register number is in 274 /// the physical register namespace. 275 static bool isPhysicalRegister(unsigned Reg) { 276 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 277 return int(Reg) > 0; 278 } 279 280 /// isVirtualRegister - Return true if the specified register number is in 281 /// the virtual register namespace. 282 static bool isVirtualRegister(unsigned Reg) { 283 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 284 return int(Reg) < 0; 285 } 286 287 /// virtReg2Index - Convert a virtual register number to a 0-based index. 288 /// The first virtual register in a function will get the index 0. 289 static unsigned virtReg2Index(unsigned Reg) { 290 assert(isVirtualRegister(Reg) && "Not a virtual register"); 291 return Reg & ~(1u << 31); 292 } 293 294 /// index2VirtReg - Convert a 0-based index to a virtual register number. 295 /// This is the inverse operation of VirtReg2IndexFunctor below. 296 static unsigned index2VirtReg(unsigned Index) { 297 return Index | (1u << 31); 298 } 299 300 /// getMinimalPhysRegClass - Returns the Register Class of a physical 301 /// register of the given type, picking the most sub register class of 302 /// the right type that contains this physreg. 303 const TargetRegisterClass * 304 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const; 305 306 /// getAllocatableSet - Returns a bitset indexed by register number 307 /// indicating if a register is allocatable or not. If a register class is 308 /// specified, returns the subset for the class. 309 BitVector getAllocatableSet(const MachineFunction &MF, 310 const TargetRegisterClass *RC = NULL) const; 311 312 /// getCostPerUse - Return the additional cost of using this register instead 313 /// of other registers in its class. 314 unsigned getCostPerUse(unsigned RegNo) const { 315 return InfoDesc[RegNo].CostPerUse; 316 } 317 318 /// isInAllocatableClass - Return true if the register is in the allocation 319 /// of any register class. 320 bool isInAllocatableClass(unsigned RegNo) const { 321 return InfoDesc[RegNo].inAllocatableClass; 322 } 323 324 /// getSubRegIndexName - Return the human-readable symbolic target-specific 325 /// name for the specified SubRegIndex. 326 const char *getSubRegIndexName(unsigned SubIdx) const { 327 assert(SubIdx && "This is not a subregister index"); 328 return SubRegIndexNames[SubIdx-1]; 329 } 330 331 /// regsOverlap - Returns true if the two registers are equal or alias each 332 /// other. The registers may be virtual register. 333 bool regsOverlap(unsigned regA, unsigned regB) const { 334 if (regA == regB) return true; 335 if (isVirtualRegister(regA) || isVirtualRegister(regB)) 336 return false; 337 for (const unsigned *regList = getOverlaps(regA)+1; *regList; ++regList) { 338 if (*regList == regB) return true; 339 } 340 return false; 341 } 342 343 /// isSubRegister - Returns true if regB is a sub-register of regA. 344 /// 345 bool isSubRegister(unsigned regA, unsigned regB) const { 346 return isSuperRegister(regB, regA); 347 } 348 349 /// isSuperRegister - Returns true if regB is a super-register of regA. 350 /// 351 bool isSuperRegister(unsigned regA, unsigned regB) const { 352 for (const unsigned *regList = getSuperRegisters(regA); *regList;++regList){ 353 if (*regList == regB) return true; 354 } 355 return false; 356 } 357 358 /// getCalleeSavedRegs - Return a null-terminated list of all of the 359 /// callee saved registers on this target. The register should be in the 360 /// order of desired callee-save stack frame offset. The first register is 361 /// closest to the incoming stack pointer if stack grows down, and vice versa. 362 /// 363 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0) 364 const = 0; 365 366 /// getCallPreservedMask - Return a mask of call-preserved registers for the 367 /// given calling convention on the current sub-target. The mask should 368 /// include all call-preserved aliases. This is used by the register 369 /// allocator to determine which registers can be live across a call. 370 /// 371 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries. 372 /// A set bit indicates that all bits of the corresponding register are 373 /// preserved across the function call. The bit mask is expected to be 374 /// sub-register complete, i.e. if A is preserved, so are all its 375 /// sub-registers. 376 /// 377 /// Bits are numbered from the LSB, so the bit for physical register Reg can 378 /// be found as (Mask[Reg / 32] >> Reg % 32) & 1. 379 /// NULL pointer is equivalent to an all-zero mask. 380 /// 381 virtual const uint32_t *getCallPreservedMask(CallingConv::ID) const { 382 // The default mask clobbers everything. All targets should override. 383 return 0; 384 } 385 386 /// getReservedRegs - Returns a bitset indexed by physical register number 387 /// indicating if a register is a special register that has particular uses 388 /// and should be considered unavailable at all times, e.g. SP, RA. This is 389 /// used by register scavenger to determine what registers are free. 390 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 391 392 /// getSubReg - Returns the physical register number of sub-register "Index" 393 /// for physical register RegNo. Return zero if the sub-register does not 394 /// exist. 395 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0; 396 397 /// getSubRegIndex - For a given register pair, return the sub-register index 398 /// if the second register is a sub-register of the first. Return zero 399 /// otherwise. 400 virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0; 401 402 /// getMatchingSuperReg - Return a super-register of the specified register 403 /// Reg so its sub-register of index SubIdx is Reg. 404 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 405 const TargetRegisterClass *RC) const { 406 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs) 407 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR)) 408 return SR; 409 return 0; 410 } 411 412 /// canCombineSubRegIndices - Given a register class and a list of 413 /// subregister indices, return true if it's possible to combine the 414 /// subregister indices into one that corresponds to a larger 415 /// subregister. Return the new subregister index by reference. Note the 416 /// new index may be zero if the given subregisters can be combined to 417 /// form the whole register. 418 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC, 419 SmallVectorImpl<unsigned> &SubIndices, 420 unsigned &NewSubIdx) const { 421 return 0; 422 } 423 424 /// getMatchingSuperRegClass - Return a subclass of the specified register 425 /// class A so that each register in it has a sub-register of the 426 /// specified sub-register index which is in the specified register class B. 427 /// 428 /// TableGen will synthesize missing A sub-classes. 429 virtual const TargetRegisterClass * 430 getMatchingSuperRegClass(const TargetRegisterClass *A, 431 const TargetRegisterClass *B, unsigned Idx) const =0; 432 433 /// getSubClassWithSubReg - Returns the largest legal sub-class of RC that 434 /// supports the sub-register index Idx. 435 /// If no such sub-class exists, return NULL. 436 /// If all registers in RC already have an Idx sub-register, return RC. 437 /// 438 /// TableGen generates a version of this function that is good enough in most 439 /// cases. Targets can override if they have constraints that TableGen 440 /// doesn't understand. For example, the x86 sub_8bit sub-register index is 441 /// supported by the full GR32 register class in 64-bit mode, but only by the 442 /// GR32_ABCD regiister class in 32-bit mode. 443 /// 444 /// TableGen will synthesize missing RC sub-classes. 445 virtual const TargetRegisterClass * 446 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const =0; 447 448 /// composeSubRegIndices - Return the subregister index you get from composing 449 /// two subregister indices. 450 /// 451 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) 452 /// returns c. Note that composeSubRegIndices does not tell you about illegal 453 /// compositions. If R does not have a subreg a, or R:a does not have a subreg 454 /// b, composeSubRegIndices doesn't tell you. 455 /// 456 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has 457 /// ssub_0:S0 - ssub_3:S3 subregs. 458 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2. 459 /// 460 virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const { 461 // This default implementation is correct for most targets. 462 return b; 463 } 464 465 //===--------------------------------------------------------------------===// 466 // Register Class Information 467 // 468 469 /// Register class iterators 470 /// 471 regclass_iterator regclass_begin() const { return RegClassBegin; } 472 regclass_iterator regclass_end() const { return RegClassEnd; } 473 474 unsigned getNumRegClasses() const { 475 return (unsigned)(regclass_end()-regclass_begin()); 476 } 477 478 /// getRegClass - Returns the register class associated with the enumeration 479 /// value. See class MCOperandInfo. 480 const TargetRegisterClass *getRegClass(unsigned i) const { 481 assert(i < getNumRegClasses() && "Register Class ID out of range"); 482 return RegClassBegin[i]; 483 } 484 485 /// getCommonSubClass - find the largest common subclass of A and B. Return 486 /// NULL if there is no common subclass. 487 const TargetRegisterClass * 488 getCommonSubClass(const TargetRegisterClass *A, 489 const TargetRegisterClass *B) const; 490 491 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 492 /// values. If a target supports multiple different pointer register classes, 493 /// kind specifies which one is indicated. 494 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const { 495 assert(0 && "Target didn't implement getPointerRegClass!"); 496 return 0; // Must return a value in order to compile with VS 2005 497 } 498 499 /// getCrossCopyRegClass - Returns a legal register class to copy a register 500 /// in the specified class to or from. If it is possible to copy the register 501 /// directly without using a cross register class copy, return the specified 502 /// RC. Returns NULL if it is not possible to copy between a two registers of 503 /// the specified class. 504 virtual const TargetRegisterClass * 505 getCrossCopyRegClass(const TargetRegisterClass *RC) const { 506 return RC; 507 } 508 509 /// getLargestLegalSuperClass - Returns the largest super class of RC that is 510 /// legal to use in the current sub-target and has the same spill size. 511 /// The returned register class can be used to create virtual registers which 512 /// means that all its registers can be copied and spilled. 513 virtual const TargetRegisterClass* 514 getLargestLegalSuperClass(const TargetRegisterClass *RC) const { 515 /// The default implementation is very conservative and doesn't allow the 516 /// register allocator to inflate register classes. 517 return RC; 518 } 519 520 /// getRegPressureLimit - Return the register pressure "high water mark" for 521 /// the specific register class. The scheduler is in high register pressure 522 /// mode (for the specific register class) if it goes over the limit. 523 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, 524 MachineFunction &MF) const { 525 return 0; 526 } 527 528 /// getRawAllocationOrder - Returns the register allocation order for a 529 /// specified register class with a target-dependent hint. The returned list 530 /// may contain reserved registers that cannot be allocated. 531 /// 532 /// Register allocators need only call this function to resolve 533 /// target-dependent hints, but it should work without hinting as well. 534 virtual ArrayRef<unsigned> 535 getRawAllocationOrder(const TargetRegisterClass *RC, 536 unsigned HintType, unsigned HintReg, 537 const MachineFunction &MF) const { 538 return RC->getRawAllocationOrder(MF); 539 } 540 541 /// ResolveRegAllocHint - Resolves the specified register allocation hint 542 /// to a physical register. Returns the physical register if it is successful. 543 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg, 544 const MachineFunction &MF) const { 545 if (Type == 0 && Reg && isPhysicalRegister(Reg)) 546 return Reg; 547 return 0; 548 } 549 550 /// avoidWriteAfterWrite - Return true if the register allocator should avoid 551 /// writing a register from RC in two consecutive instructions. 552 /// This can avoid pipeline stalls on certain architectures. 553 /// It does cause increased register pressure, though. 554 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 555 return false; 556 } 557 558 /// UpdateRegAllocHint - A callback to allow target a chance to update 559 /// register allocation hints when a register is "changed" (e.g. coalesced) 560 /// to another register. e.g. On ARM, some virtual registers should target 561 /// register pairs, if one of pair is coalesced to another register, the 562 /// allocation hint of the other half of the pair should be changed to point 563 /// to the new register. 564 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 565 MachineFunction &MF) const { 566 // Do nothing. 567 } 568 569 /// requiresRegisterScavenging - returns true if the target requires (and can 570 /// make use of) the register scavenger. 571 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 572 return false; 573 } 574 575 /// useFPForScavengingIndex - returns true if the target wants to use 576 /// frame pointer based accesses to spill to the scavenger emergency spill 577 /// slot. 578 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const { 579 return true; 580 } 581 582 /// requiresFrameIndexScavenging - returns true if the target requires post 583 /// PEI scavenging of registers for materializing frame index constants. 584 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const { 585 return false; 586 } 587 588 /// requiresVirtualBaseRegisters - Returns true if the target wants the 589 /// LocalStackAllocation pass to be run and virtual base registers 590 /// used for more efficient stack access. 591 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const { 592 return false; 593 } 594 595 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in 596 /// the stack frame of the given function for the specified register. e.g. On 597 /// x86, if the frame register is required, the first fixed stack object is 598 /// reserved as its spill slot. This tells PEI not to create a new stack frame 599 /// object for the given register. It should be called only after 600 /// processFunctionBeforeCalleeSavedScan(). 601 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 602 int &FrameIdx) const { 603 return false; 604 } 605 606 /// needsStackRealignment - true if storage within the function requires the 607 /// stack pointer to be aligned more than the normal calling convention calls 608 /// for. 609 virtual bool needsStackRealignment(const MachineFunction &MF) const { 610 return false; 611 } 612 613 /// getFrameIndexInstrOffset - Get the offset from the referenced frame 614 /// index in the instruction, if there is one. 615 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, 616 int Idx) const { 617 return 0; 618 } 619 620 /// needsFrameBaseReg - Returns true if the instruction's frame index 621 /// reference would be better served by a base register other than FP 622 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 623 /// references it should create new base registers for. 624 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 625 return false; 626 } 627 628 /// materializeFrameBaseRegister - Insert defining instruction(s) for 629 /// BaseReg to be a pointer to FrameIdx before insertion point I. 630 virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB, 631 unsigned BaseReg, int FrameIdx, 632 int64_t Offset) const { 633 assert(0 && "materializeFrameBaseRegister does not exist on this target"); 634 } 635 636 /// resolveFrameIndex - Resolve a frame index operand of an instruction 637 /// to reference the indicated base register plus offset instead. 638 virtual void resolveFrameIndex(MachineBasicBlock::iterator I, 639 unsigned BaseReg, int64_t Offset) const { 640 assert(0 && "resolveFrameIndex does not exist on this target"); 641 } 642 643 /// isFrameOffsetLegal - Determine whether a given offset immediate is 644 /// encodable to resolve a frame index. 645 virtual bool isFrameOffsetLegal(const MachineInstr *MI, 646 int64_t Offset) const { 647 assert(0 && "isFrameOffsetLegal does not exist on this target"); 648 return false; // Must return a value in order to compile with VS 2005 649 } 650 651 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog 652 /// code insertion to eliminate call frame setup and destroy pseudo 653 /// instructions (but only if the Target is using them). It is responsible 654 /// for eliminating these instructions, replacing them with concrete 655 /// instructions. This method need only be implemented if using call frame 656 /// setup/destroy pseudo instructions. 657 /// 658 virtual void 659 eliminateCallFramePseudoInstr(MachineFunction &MF, 660 MachineBasicBlock &MBB, 661 MachineBasicBlock::iterator MI) const { 662 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!"); 663 } 664 665 666 /// saveScavengerRegister - Spill the register so it can be used by the 667 /// register scavenger. Return true if the register was spilled, false 668 /// otherwise. If this function does not spill the register, the scavenger 669 /// will instead spill it to the emergency spill slot. 670 /// 671 virtual bool saveScavengerRegister(MachineBasicBlock &MBB, 672 MachineBasicBlock::iterator I, 673 MachineBasicBlock::iterator &UseMI, 674 const TargetRegisterClass *RC, 675 unsigned Reg) const { 676 return false; 677 } 678 679 /// eliminateFrameIndex - This method must be overriden to eliminate abstract 680 /// frame indices from instructions which may use them. The instruction 681 /// referenced by the iterator contains an MO_FrameIndex operand which must be 682 /// eliminated by this method. This method may modify or replace the 683 /// specified instruction, as long as it keeps the iterator pointing at the 684 /// finished product. SPAdj is the SP adjustment due to call frame setup 685 /// instruction. 686 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, 687 int SPAdj, RegScavenger *RS=NULL) const = 0; 688 689 //===--------------------------------------------------------------------===// 690 /// Debug information queries. 691 692 /// getFrameRegister - This method should return the register used as a base 693 /// for values allocated in the current stack frame. 694 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0; 695 696 /// getCompactUnwindRegNum - This function maps the register to the number for 697 /// compact unwind encoding. Return -1 if the register isn't valid. 698 virtual int getCompactUnwindRegNum(unsigned, bool) const { 699 return -1; 700 } 701}; 702 703 704// This is useful when building IndexedMaps keyed on virtual registers 705struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> { 706 unsigned operator()(unsigned Reg) const { 707 return TargetRegisterInfo::virtReg2Index(Reg); 708 } 709}; 710 711/// PrintReg - Helper class for printing registers on a raw_ostream. 712/// Prints virtual and physical registers with or without a TRI instance. 713/// 714/// The format is: 715/// %noreg - NoRegister 716/// %vreg5 - a virtual register. 717/// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI). 718/// %EAX - a physical register 719/// %physreg17 - a physical register when no TRI instance given. 720/// 721/// Usage: OS << PrintReg(Reg, TRI) << '\n'; 722/// 723class PrintReg { 724 const TargetRegisterInfo *TRI; 725 unsigned Reg; 726 unsigned SubIdx; 727public: 728 PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0) 729 : TRI(tri), Reg(reg), SubIdx(subidx) {} 730 void print(raw_ostream&) const; 731}; 732 733static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) { 734 PR.print(OS); 735 return OS; 736} 737 738} // End llvm namespace 739 740#endif 741