DeadMachineInstructionElim.cpp revision fb9ebbf236974beac31705eaeb9f50ab585af6ab 
1//===- DeadMachineInstructionElim.cpp - Remove dead machine instructions --===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This is an extremely simple MachineInstr-level dead-code-elimination pass.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "codegen-dce"
15#include "llvm/CodeGen/Passes.h"
16#include "llvm/Pass.h"
17#include "llvm/CodeGen/MachineFunctionPass.h"
18#include "llvm/CodeGen/MachineRegisterInfo.h"
19#include "llvm/Support/Debug.h"
20#include "llvm/Support/raw_ostream.h"
21#include "llvm/Target/TargetInstrInfo.h"
22#include "llvm/Target/TargetMachine.h"
23#include "llvm/ADT/Statistic.h"
24using namespace llvm;
25
26STATISTIC(NumDeletes,          "Number of dead instructions deleted");
27
28namespace {
29  class DeadMachineInstructionElim : public MachineFunctionPass {
30    virtual bool runOnMachineFunction(MachineFunction &MF);
31
32    const TargetRegisterInfo *TRI;
33    const MachineRegisterInfo *MRI;
34    const TargetInstrInfo *TII;
35    BitVector LivePhysRegs;
36
37  public:
38    static char ID; // Pass identification, replacement for typeid
39    DeadMachineInstructionElim() : MachineFunctionPass(ID) {
40     initializeDeadMachineInstructionElimPass(*PassRegistry::getPassRegistry());
41    }
42
43  private:
44    bool isDead(const MachineInstr *MI) const;
45  };
46}
47char DeadMachineInstructionElim::ID = 0;
48char &llvm::DeadMachineInstructionElimID = DeadMachineInstructionElim::ID;
49
50INITIALIZE_PASS(DeadMachineInstructionElim, "dead-mi-elimination",
51                "Remove dead machine instructions", false, false)
52
53bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const {
54  // Technically speaking inline asm without side effects and no defs can still
55  // be deleted. But there is so much bad inline asm code out there, we should
56  // let them be.
57  if (MI->isInlineAsm())
58    return false;
59
60  // Don't delete instructions with side effects.
61  bool SawStore = false;
62  if (!MI->isSafeToMove(TII, 0, SawStore) && !MI->isPHI())
63    return false;
64
65  // Examine each operand.
66  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
67    const MachineOperand &MO = MI->getOperand(i);
68    if (MO.isReg() && MO.isDef()) {
69      unsigned Reg = MO.getReg();
70      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
71        // Don't delete live physreg defs, or any reserved register defs.
72        if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg))
73          return false;
74      } else {
75        if (!MRI->use_nodbg_empty(Reg))
76          // This def has a non-debug use. Don't delete the instruction!
77          return false;
78      }
79    }
80  }
81
82  // If there are no defs with uses, the instruction is dead.
83  return true;
84}
85
86bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) {
87  bool AnyChanges = false;
88  MRI = &MF.getRegInfo();
89  TRI = MF.getTarget().getRegisterInfo();
90  TII = MF.getTarget().getInstrInfo();
91
92  // Loop over all instructions in all blocks, from bottom to top, so that it's
93  // more likely that chains of dependent but ultimately dead instructions will
94  // be cleaned up.
95  for (MachineFunction::reverse_iterator I = MF.rbegin(), E = MF.rend();
96       I != E; ++I) {
97    MachineBasicBlock *MBB = &*I;
98
99    // Start out assuming that reserved registers are live out of this block.
100    LivePhysRegs = MRI->getReservedRegs();
101
102    // Also add any explicit live-out physregs for this block.
103    if (!MBB->empty() && MBB->back().isReturn())
104      for (MachineRegisterInfo::liveout_iterator LOI = MRI->liveout_begin(),
105           LOE = MRI->liveout_end(); LOI != LOE; ++LOI) {
106        unsigned Reg = *LOI;
107        if (TargetRegisterInfo::isPhysicalRegister(Reg))
108          LivePhysRegs.set(Reg);
109      }
110
111    // Add live-ins from sucessors to LivePhysRegs. Normally, physregs are not
112    // live across blocks, but some targets (x86) can have flags live out of a
113    // block.
114    for (MachineBasicBlock::succ_iterator S = MBB->succ_begin(),
115           E = MBB->succ_end(); S != E; S++)
116      for (MachineBasicBlock::livein_iterator LI = (*S)->livein_begin();
117           LI != (*S)->livein_end(); LI++)
118        LivePhysRegs.set(*LI);
119
120    // Now scan the instructions and delete dead ones, tracking physreg
121    // liveness as we go.
122    for (MachineBasicBlock::reverse_iterator MII = MBB->rbegin(),
123         MIE = MBB->rend(); MII != MIE; ) {
124      MachineInstr *MI = &*MII;
125
126      // If the instruction is dead, delete it!
127      if (isDead(MI)) {
128        DEBUG(dbgs() << "DeadMachineInstructionElim: DELETING: " << *MI);
129        // It is possible that some DBG_VALUE instructions refer to this
130        // instruction.  Examine each def operand for such references;
131        // if found, mark the DBG_VALUE as undef (but don't delete it).
132        for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
133          const MachineOperand &MO = MI->getOperand(i);
134          if (!MO.isReg() || !MO.isDef())
135            continue;
136          unsigned Reg = MO.getReg();
137          if (!TargetRegisterInfo::isVirtualRegister(Reg))
138            continue;
139          MachineRegisterInfo::use_iterator nextI;
140          for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg),
141               E = MRI->use_end(); I!=E; I=nextI) {
142            nextI = llvm::next(I);  // I is invalidated by the setReg
143            MachineOperand& Use = I.getOperand();
144            MachineInstr *UseMI = Use.getParent();
145            if (UseMI==MI)
146              continue;
147            assert(Use.isDebug());
148            UseMI->getOperand(0).setReg(0U);
149          }
150        }
151        AnyChanges = true;
152        MI->eraseFromParent();
153        ++NumDeletes;
154        MIE = MBB->rend();
155        // MII is now pointing to the next instruction to process,
156        // so don't increment it.
157        continue;
158      }
159
160      // Record the physreg defs.
161      for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
162        const MachineOperand &MO = MI->getOperand(i);
163        if (MO.isReg() && MO.isDef()) {
164          unsigned Reg = MO.getReg();
165          if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
166            LivePhysRegs.reset(Reg);
167            // Check the subreg set, not the alias set, because a def
168            // of a super-register may still be partially live after
169            // this def.
170            for (MCSubRegIterator SR(Reg, TRI); SR.isValid(); ++SR)
171              LivePhysRegs.reset(*SR);
172          }
173        } else if (MO.isRegMask()) {
174          // Register mask of preserved registers. All clobbers are dead.
175          LivePhysRegs.clearBitsNotInMask(MO.getRegMask());
176        }
177      }
178      // Record the physreg uses, after the defs, in case a physreg is
179      // both defined and used in the same instruction.
180      for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
181        const MachineOperand &MO = MI->getOperand(i);
182        if (MO.isReg() && MO.isUse()) {
183          unsigned Reg = MO.getReg();
184          if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
185            for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
186              LivePhysRegs.set(*AI);
187          }
188        }
189      }
190
191      // We didn't delete the current instruction, so increment MII to
192      // the next one.
193      ++MII;
194    }
195  }
196
197  LivePhysRegs.clear();
198  return AnyChanges;
199}
200