PHIElimination.cpp revision 6ddba2b933645d308428201e942abe1274fa5085
1//===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass eliminates machine instruction PHI nodes by inserting copy 11// instructions. This destroys SSA information, but is the desired input for 12// some register allocators. 13// 14//===----------------------------------------------------------------------===// 15 16#define DEBUG_TYPE "phielim" 17#include "llvm/CodeGen/LiveVariables.h" 18#include "llvm/CodeGen/Passes.h" 19#include "llvm/CodeGen/MachineFunctionPass.h" 20#include "llvm/CodeGen/MachineInstr.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/Target/TargetInstrInfo.h" 24#include "llvm/Target/TargetMachine.h" 25#include "llvm/ADT/SmallPtrSet.h" 26#include "llvm/ADT/STLExtras.h" 27#include "llvm/ADT/Statistic.h" 28#include "llvm/Support/Compiler.h" 29#include <algorithm> 30#include <map> 31using namespace llvm; 32 33STATISTIC(NumAtomic, "Number of atomic phis lowered"); 34 35namespace { 36 class VISIBILITY_HIDDEN PNE : public MachineFunctionPass { 37 MachineRegisterInfo *MRI; // Machine register information 38 39 public: 40 static char ID; // Pass identification, replacement for typeid 41 PNE() : MachineFunctionPass((intptr_t)&ID) {} 42 43 virtual bool runOnMachineFunction(MachineFunction &Fn); 44 45 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 46 AU.addPreserved<LiveVariables>(); 47 AU.addPreservedID(MachineLoopInfoID); 48 AU.addPreservedID(MachineDominatorsID); 49 MachineFunctionPass::getAnalysisUsage(AU); 50 } 51 52 private: 53 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions 54 /// in predecessor basic blocks. 55 /// 56 bool EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB); 57 void LowerAtomicPHINode(MachineBasicBlock &MBB, 58 MachineBasicBlock::iterator AfterPHIsIt); 59 60 /// analyzePHINodes - Gather information about the PHI nodes in 61 /// here. In particular, we want to map the number of uses of a virtual 62 /// register which is used in a PHI node. We map that to the BB the 63 /// vreg is coming from. This is used later to determine when the vreg 64 /// is killed in the BB. 65 /// 66 void analyzePHINodes(const MachineFunction& Fn); 67 68 typedef std::pair<const MachineBasicBlock*, unsigned> BBVRegPair; 69 typedef std::map<BBVRegPair, unsigned> VRegPHIUse; 70 71 VRegPHIUse VRegPHIUseCount; 72 73 // Defs of PHI sources which are implicit_def. 74 SmallPtrSet<MachineInstr*, 4> ImpDefs; 75 }; 76} 77 78char PNE::ID = 0; 79static RegisterPass<PNE> 80X("phi-node-elimination", "Eliminate PHI nodes for register allocation"); 81 82const PassInfo *const llvm::PHIEliminationID = &X; 83 84bool PNE::runOnMachineFunction(MachineFunction &Fn) { 85 MRI = &Fn.getRegInfo(); 86 87 analyzePHINodes(Fn); 88 89 bool Changed = false; 90 91 // Eliminate PHI instructions by inserting copies into predecessor blocks. 92 for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) 93 Changed |= EliminatePHINodes(Fn, *I); 94 95 // Remove dead IMPLICIT_DEF instructions. 96 for (SmallPtrSet<MachineInstr*,4>::iterator I = ImpDefs.begin(), 97 E = ImpDefs.end(); I != E; ++I) { 98 MachineInstr *DefMI = *I; 99 unsigned DefReg = DefMI->getOperand(0).getReg(); 100 if (MRI->use_begin(DefReg) == MRI->use_end()) 101 DefMI->eraseFromParent(); 102 } 103 104 ImpDefs.clear(); 105 VRegPHIUseCount.clear(); 106 return Changed; 107} 108 109 110/// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in 111/// predecessor basic blocks. 112/// 113bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) { 114 if (MBB.empty() || MBB.front().getOpcode() != TargetInstrInfo::PHI) 115 return false; // Quick exit for basic blocks without PHIs. 116 117 // Get an iterator to the first instruction after the last PHI node (this may 118 // also be the end of the basic block). 119 MachineBasicBlock::iterator AfterPHIsIt = MBB.begin(); 120 while (AfterPHIsIt != MBB.end() && 121 AfterPHIsIt->getOpcode() == TargetInstrInfo::PHI) 122 ++AfterPHIsIt; // Skip over all of the PHI nodes... 123 124 while (MBB.front().getOpcode() == TargetInstrInfo::PHI) 125 LowerAtomicPHINode(MBB, AfterPHIsIt); 126 127 return true; 128} 129 130static bool isSourceDefinedByImplicitDef(const MachineInstr *MPhi, 131 const MachineRegisterInfo *MRI) { 132 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) { 133 unsigned SrcReg = MPhi->getOperand(i).getReg(); 134 const MachineInstr *DefMI = MRI->getVRegDef(SrcReg); 135 if (!DefMI || DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF) 136 return false; 137 } 138 return true; 139} 140 141/// LowerAtomicPHINode - Lower the PHI node at the top of the specified block, 142/// under the assuption that it needs to be lowered in a way that supports 143/// atomic execution of PHIs. This lowering method is always correct all of the 144/// time. 145/// 146void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB, 147 MachineBasicBlock::iterator AfterPHIsIt) { 148 // Unlink the PHI node from the basic block, but don't delete the PHI yet. 149 MachineInstr *MPhi = MBB.remove(MBB.begin()); 150 151 unsigned NumSrcs = (MPhi->getNumOperands() - 1) / 2; 152 unsigned DestReg = MPhi->getOperand(0).getReg(); 153 154 // Create a new register for the incoming PHI arguments. 155 MachineFunction &MF = *MBB.getParent(); 156 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg); 157 unsigned IncomingReg = MF.getRegInfo().createVirtualRegister(RC); 158 159 // Insert a register to register copy at the top of the current block (but 160 // after any remaining phi nodes) which copies the new incoming register 161 // into the phi node destination. 162 const TargetInstrInfo *TII = MF.getTarget().getInstrInfo(); 163 if (isSourceDefinedByImplicitDef(MPhi, MRI)) 164 // If all sources of a PHI node are implicit_def, just emit an implicit_def 165 // instead of a copy. 166 BuildMI(MBB, AfterPHIsIt, TII->get(TargetInstrInfo::IMPLICIT_DEF), DestReg); 167 else 168 TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC); 169 170 // Update live variable information if there is any. 171 LiveVariables *LV = getAnalysisToUpdate<LiveVariables>(); 172 if (LV) { 173 MachineInstr *PHICopy = prior(AfterPHIsIt); 174 175 // Increment use count of the newly created virtual register. 176 LV->getVarInfo(IncomingReg).NumUses++; 177 178 // Add information to LiveVariables to know that the incoming value is 179 // killed. Note that because the value is defined in several places (once 180 // each for each incoming block), the "def" block and instruction fields for 181 // the VarInfo is not filled in. 182 LV->addVirtualRegisterKilled(IncomingReg, PHICopy); 183 184 // Since we are going to be deleting the PHI node, if it is the last use of 185 // any registers, or if the value itself is dead, we need to move this 186 // information over to the new copy we just inserted. 187 LV->removeVirtualRegistersKilled(MPhi); 188 189 // If the result is dead, update LV. 190 if (MPhi->registerDefIsDead(DestReg)) { 191 LV->addVirtualRegisterDead(DestReg, PHICopy); 192 LV->removeVirtualRegistersDead(MPhi); 193 } 194 195 LV->getVarInfo(IncomingReg).UsedBlocks[MBB.getNumber()] = true; 196 } 197 198 // Adjust the VRegPHIUseCount map to account for the removal of this PHI node. 199 for (unsigned i = 1; i != MPhi->getNumOperands(); i += 2) 200 --VRegPHIUseCount[BBVRegPair(MPhi->getOperand(i + 1).getMBB(), 201 MPhi->getOperand(i).getReg())]; 202 203 // Now loop over all of the incoming arguments, changing them to copy into the 204 // IncomingReg register in the corresponding predecessor basic block. 205 SmallPtrSet<MachineBasicBlock*, 8> MBBsInsertedInto; 206 for (int i = NumSrcs - 1; i >= 0; --i) { 207 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg(); 208 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) && 209 "Machine PHI Operands must all be virtual registers!"); 210 211 // If source is defined by an implicit def, there is no need to insert a 212 // copy unless it's the only source. 213 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); 214 if (DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) { 215 ImpDefs.insert(DefMI); 216 continue; 217 } 218 219 // Get the MachineBasicBlock equivalent of the BasicBlock that is the source 220 // path the PHI. 221 MachineBasicBlock &opBlock = *MPhi->getOperand(i*2+2).getMBB(); 222 223 // Check to make sure we haven't already emitted the copy for this block. 224 // This can happen because PHI nodes may have multiple entries for the same 225 // basic block. 226 if (!MBBsInsertedInto.insert(&opBlock)) 227 continue; // If the copy has already been emitted, we're done. 228 229 // Find a safe location to insert the copy, this may be the first terminator 230 // in the block (or end()). 231 MachineBasicBlock::iterator InsertPos = opBlock.getFirstTerminator(); 232 233 // Insert the copy. 234 TII->copyRegToReg(opBlock, InsertPos, IncomingReg, SrcReg, RC, RC); 235 236 // Now update live variable information if we have it. Otherwise we're done 237 if (!LV) continue; 238 239 // We want to be able to insert a kill of the register if this PHI (aka, the 240 // copy we just inserted) is the last use of the source value. Live 241 // variable analysis conservatively handles this by saying that the value is 242 // live until the end of the block the PHI entry lives in. If the value 243 // really is dead at the PHI copy, there will be no successor blocks which 244 // have the value live-in. 245 // 246 // Check to see if the copy is the last use, and if so, update the live 247 // variables information so that it knows the copy source instruction kills 248 // the incoming value. 249 LiveVariables::VarInfo &InRegVI = LV->getVarInfo(SrcReg); 250 InRegVI.UsedBlocks[opBlock.getNumber()] = true; 251 252 // Loop over all of the successors of the basic block, checking to see if 253 // the value is either live in the block, or if it is killed in the block. 254 // Also check to see if this register is in use by another PHI node which 255 // has not yet been eliminated. If so, it will be killed at an appropriate 256 // point later. 257 258 // Is it used by any PHI instructions in this block? 259 bool ValueIsLive = VRegPHIUseCount[BBVRegPair(&opBlock, SrcReg)] != 0; 260 261 std::vector<MachineBasicBlock*> OpSuccBlocks; 262 263 // Otherwise, scan successors, including the BB the PHI node lives in. 264 for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(), 265 E = opBlock.succ_end(); SI != E && !ValueIsLive; ++SI) { 266 MachineBasicBlock *SuccMBB = *SI; 267 268 // Is it alive in this successor? 269 unsigned SuccIdx = SuccMBB->getNumber(); 270 if (SuccIdx < InRegVI.AliveBlocks.size() && 271 InRegVI.AliveBlocks[SuccIdx]) { 272 ValueIsLive = true; 273 break; 274 } 275 276 OpSuccBlocks.push_back(SuccMBB); 277 } 278 279 // Check to see if this value is live because there is a use in a successor 280 // that kills it. 281 if (!ValueIsLive) { 282 switch (OpSuccBlocks.size()) { 283 case 1: { 284 MachineBasicBlock *MBB = OpSuccBlocks[0]; 285 for (unsigned i = 0, e = InRegVI.Kills.size(); i != e; ++i) 286 if (InRegVI.Kills[i]->getParent() == MBB) { 287 ValueIsLive = true; 288 break; 289 } 290 break; 291 } 292 case 2: { 293 MachineBasicBlock *MBB1 = OpSuccBlocks[0], *MBB2 = OpSuccBlocks[1]; 294 for (unsigned i = 0, e = InRegVI.Kills.size(); i != e; ++i) 295 if (InRegVI.Kills[i]->getParent() == MBB1 || 296 InRegVI.Kills[i]->getParent() == MBB2) { 297 ValueIsLive = true; 298 break; 299 } 300 break; 301 } 302 default: 303 std::sort(OpSuccBlocks.begin(), OpSuccBlocks.end()); 304 for (unsigned i = 0, e = InRegVI.Kills.size(); i != e; ++i) 305 if (std::binary_search(OpSuccBlocks.begin(), OpSuccBlocks.end(), 306 InRegVI.Kills[i]->getParent())) { 307 ValueIsLive = true; 308 break; 309 } 310 } 311 } 312 313 // Okay, if we now know that the value is not live out of the block, we can 314 // add a kill marker in this block saying that it kills the incoming value! 315 if (!ValueIsLive) { 316 // In our final twist, we have to decide which instruction kills the 317 // register. In most cases this is the copy, however, the first 318 // terminator instruction at the end of the block may also use the value. 319 // In this case, we should mark *it* as being the killing block, not the 320 // copy. 321 MachineBasicBlock::iterator KillInst = prior(InsertPos); 322 MachineBasicBlock::iterator Term = opBlock.getFirstTerminator(); 323 if (Term != opBlock.end()) { 324 if (Term->readsRegister(SrcReg)) 325 KillInst = Term; 326 327 // Check that no other terminators use values. 328#ifndef NDEBUG 329 for (MachineBasicBlock::iterator TI = next(Term); TI != opBlock.end(); 330 ++TI) { 331 assert(!TI->readsRegister(SrcReg) && 332 "Terminator instructions cannot use virtual registers unless" 333 "they are the first terminator in a block!"); 334 } 335#endif 336 } 337 338 // Finally, mark it killed. 339 LV->addVirtualRegisterKilled(SrcReg, KillInst); 340 341 // This vreg no longer lives all of the way through opBlock. 342 unsigned opBlockNum = opBlock.getNumber(); 343 if (opBlockNum < InRegVI.AliveBlocks.size()) 344 InRegVI.AliveBlocks[opBlockNum] = false; 345 } 346 } 347 348 // Really delete the PHI instruction now! 349 delete MPhi; 350 ++NumAtomic; 351} 352 353/// analyzePHINodes - Gather information about the PHI nodes in here. In 354/// particular, we want to map the number of uses of a virtual register which is 355/// used in a PHI node. We map that to the BB the vreg is coming from. This is 356/// used later to determine when the vreg is killed in the BB. 357/// 358void PNE::analyzePHINodes(const MachineFunction& Fn) { 359 for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end(); 360 I != E; ++I) 361 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end(); 362 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) 363 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) 364 ++VRegPHIUseCount[BBVRegPair(BBI->getOperand(i + 1).getMBB(), 365 BBI->getOperand(i).getReg())]; 366} 367