16f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman//===- TargetRegisterInfo.cpp - Target Register Information Implementation ===// 2f976c856fcc5055f3fc7d9f070d72c2d027c1d9dMisha Brukman// 3b576c94c15af9a440f69d9d03c2afead7971118cJohn Criswell// The LLVM Compiler Infrastructure 4b576c94c15af9a440f69d9d03c2afead7971118cJohn Criswell// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 7f976c856fcc5055f3fc7d9f070d72c2d027c1d9dMisha Brukman// 8b576c94c15af9a440f69d9d03c2afead7971118cJohn Criswell//===----------------------------------------------------------------------===// 99208bbf5c9f12099de3f0a0716c33b0759075f03Chris Lattner// 106f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman// This file implements the TargetRegisterInfo interface. 119208bbf5c9f12099de3f0a0716c33b0759075f03Chris Lattner// 129208bbf5c9f12099de3f0a0716c33b0759075f03Chris Lattner//===----------------------------------------------------------------------===// 139208bbf5c9f12099de3f0a0716c33b0759075f03Chris Lattner 1461de82d8853a02fe39c47302432abb70a586704fEvan Cheng#include "llvm/ADT/BitVector.h" 15f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar#include "llvm/CodeGen/MachineFrameInfo.h" 167eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen#include "llvm/CodeGen/MachineFunction.h" 177eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen#include "llvm/CodeGen/MachineRegisterInfo.h" 187eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen#include "llvm/CodeGen/VirtRegMap.h" 19f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar#include "llvm/IR/Function.h" 2037ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines#include "llvm/Support/Debug.h" 21f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar#include "llvm/Support/Format.h" 22414e5023f8f8b22486313e2867fdb39c7c4f564bJakob Stoklund Olesen#include "llvm/Support/raw_ostream.h" 23f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar#include "llvm/Target/TargetFrameLowering.h" 24f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar#include "llvm/Target/TargetRegisterInfo.h" 25f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 26f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar#define DEBUG_TYPE "target-reg-info" 27a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4Jim Laskey 2820ea062192778c5cc1d05f771fbc58a6e99d753cChris Lattnerusing namespace llvm; 29d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 30a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan ChengTargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID, 313ad764290179871ad00253e2b6e235596caa3db1Chris Lattner regclass_iterator RCB, regclass_iterator RCE, 32a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen const char *const *SRINames, 33997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen const unsigned *SRILaneMasks, 34997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen unsigned SRICoveringLanes) 35a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen : InfoDesc(ID), SubRegIndexNames(SRINames), 36a6035773d8d29827a124e65c258adbf0dcbb1a5aJakob Stoklund Olesen SubRegIndexLaneMasks(SRILaneMasks), 37997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen RegClassBegin(RCB), RegClassEnd(RCE), 38997fa623fc14122153c58ddda8c90aa30f192cc8Jakob Stoklund Olesen CoveringLanes(SRICoveringLanes) { 399208bbf5c9f12099de3f0a0716c33b0759075f03Chris Lattner} 409208bbf5c9f12099de3f0a0716c33b0759075f03Chris Lattner 416f0d024a534af18d9e60b3ea757376cd8a3a980eDan GohmanTargetRegisterInfo::~TargetRegisterInfo() {} 420aafc3289c3043abd5e8f2efdd8b9fc3e830d97fNate Begeman 43f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainarnamespace llvm { 44f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 45f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga NainarPrintable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI, 46f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar unsigned SubIdx) { 47f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar return Printable([Reg, TRI, SubIdx](raw_ostream &OS) { 48f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (!Reg) 49f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar OS << "%noreg"; 50f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar else if (TargetRegisterInfo::isStackSlot(Reg)) 51f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg); 52f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar else if (TargetRegisterInfo::isVirtualRegister(Reg)) 53f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg); 54f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar else if (TRI && Reg < TRI->getNumRegs()) 55f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar OS << '%' << TRI->getName(Reg); 564314268128be6d54c9a7f0709680e5a5b40f3ab3Jakob Stoklund Olesen else 57f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar OS << "%physreg" << Reg; 58f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (SubIdx) { 59f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (TRI) 60f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar OS << ':' << TRI->getSubRegIndexName(SubIdx); 61f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar else 62f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar OS << ":sub(" << SubIdx << ')'; 63f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar } 64f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar }); 65414e5023f8f8b22486313e2867fdb39c7c4f564bJakob Stoklund Olesen} 66414e5023f8f8b22486313e2867fdb39c7c4f564bJakob Stoklund Olesen 67f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga NainarPrintable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) { 68f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar return Printable([Unit, TRI](raw_ostream &OS) { 69f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar // Generic printout when TRI is missing. 70f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (!TRI) { 71f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar OS << "Unit~" << Unit; 72f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar return; 73f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar } 745ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen 75f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar // Check for invalid register units. 76f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (Unit >= TRI->getNumRegUnits()) { 77f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar OS << "BadUnit~" << Unit; 78f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar return; 79f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar } 805ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen 81f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar // Normal units have at least one root. 82f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar MCRegUnitRootIterator Roots(Unit, TRI); 83f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar assert(Roots.isValid() && "Unit has no roots."); 84f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar OS << TRI->getName(*Roots); 85f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar for (++Roots; Roots.isValid(); ++Roots) 86f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar OS << '~' << TRI->getName(*Roots); 87f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar }); 885ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen} 895ddc04caf25a649963c99be02646c3a9fc88d514Jakob Stoklund Olesen 90f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga NainarPrintable PrintVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) { 91f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar return Printable([Unit, TRI](raw_ostream &OS) { 92f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (TRI && TRI->isVirtualRegister(Unit)) { 93f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Unit); 94f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar } else { 95f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar OS << PrintRegUnit(Unit, TRI); 96f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar } 97f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar }); 98f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar} 99f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 100f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga NainarPrintable PrintLaneMask(LaneBitmask LaneMask) { 101f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar return Printable([LaneMask](raw_ostream &OS) { 102f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar OS << format("%08X", LaneMask); 103f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar }); 10412d3dc73dc44acd8b11cca783b826ccbd66f44daAndrew Trick} 10512d3dc73dc44acd8b11cca783b826ccbd66f44daAndrew Trick 106f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar} // End of llvm namespace 107f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 108f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick/// getAllocatableClass - Return the maximal subclass of the given register 109f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick/// class that is alloctable, or NULL. 110f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trickconst TargetRegisterClass * 111f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew TrickTargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const { 112f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick if (!RC || RC->isAllocatable()) 113f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick return RC; 114f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick 115de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (BitMaskClassIterator It(RC->getSubClassMask(), *this); It.isValid(); 116de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar ++It) { 117de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar const TargetRegisterClass *SubRC = getRegClass(It.getID()); 118de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (SubRC->isAllocatable()) 119de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return SubRC; 120f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick } 121dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 122f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick} 123f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick 124ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola/// getMinimalPhysRegClass - Returns the Register Class of a physical 125c2af869d629b338861e1c6f0b360a233c0c0f9c4Dan Gohman/// register of the given type, picking the most sub register class of 126c2af869d629b338861e1c6f0b360a233c0c0f9c4Dan Gohman/// the right type that contains this physreg. 127ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindolaconst TargetRegisterClass * 12837ed9c199ca639565f6ce88105f9e39e898d82d0Stephen HinesTargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, MVT VT) const { 129ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola assert(isPhysicalRegister(reg) && "reg must be a physical register"); 130ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola 131ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola // Pick the most sub register class of the right type that contains 132ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola // this physreg. 133dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const TargetRegisterClass* BestRC = nullptr; 134ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){ 135ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola const TargetRegisterClass* RC = *I; 136d31f972bd33de85071c716f69bf5c6d735f730f2Rafael Espindola if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) && 137d31f972bd33de85071c716f69bf5c6d735f730f2Rafael Espindola (!BestRC || BestRC->hasSubClass(RC))) 138ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola BestRC = RC; 139ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola } 140ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola 141ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola assert(BestRC && "Couldn't find the register class"); 142ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola return BestRC; 143ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola} 144ce48c1de828688b34cf5c2038fde23368a0a45f4Rafael Espindola 1457be6368cacf361c86abe23b650b182ae0ee296d7Evan Cheng/// getAllocatableSetForRC - Toggle the bits that represent allocatable 1467be6368cacf361c86abe23b650b182ae0ee296d7Evan Cheng/// registers for the specific register class. 147769b7f89534caed11d7595b5c84aa47d3de30ad9Dan Gohmanstatic void getAllocatableSetForRC(const MachineFunction &MF, 1483e234e757965a3c30f31227b60575841441368b6Jim Grosbach const TargetRegisterClass *RC, BitVector &R){ 149f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick assert(RC->isAllocatable() && "invalid for nonallocatable sets"); 150dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF); 1518936b947760a278b6371335f3411de647989c665Jakob Stoklund Olesen for (unsigned i = 0; i != Order.size(); ++i) 1528936b947760a278b6371335f3411de647989c665Jakob Stoklund Olesen R.set(Order[i]); 1537be6368cacf361c86abe23b650b182ae0ee296d7Evan Cheng} 1547be6368cacf361c86abe23b650b182ae0ee296d7Evan Cheng 155769b7f89534caed11d7595b5c84aa47d3de30ad9Dan GohmanBitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, 1566f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman const TargetRegisterClass *RC) const { 157a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng BitVector Allocatable(getNumRegs()); 1587be6368cacf361c86abe23b650b182ae0ee296d7Evan Cheng if (RC) { 159f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick // A register class with no allocatable subclass returns an empty set. 160f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick const TargetRegisterClass *SubClass = getAllocatableClass(RC); 161f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick if (SubClass) 162f12f6dff9784805e8f89309787231c1ec53a8c6eAndrew Trick getAllocatableSetForRC(MF, SubClass, Allocatable); 163bb5a039b76cc2cc6de6a5b6bdd4ebf6aefd9d564Jim Grosbach } else { 164bb5a039b76cc2cc6de6a5b6bdd4ebf6aefd9d564Jim Grosbach for (TargetRegisterInfo::regclass_iterator I = regclass_begin(), 1657be6368cacf361c86abe23b650b182ae0ee296d7Evan Cheng E = regclass_end(); I != E; ++I) 166f462e3fac7ac67503657d63dc35330d0b19359b3Jakob Stoklund Olesen if ((*I)->isAllocatable()) 167f462e3fac7ac67503657d63dc35330d0b19359b3Jakob Stoklund Olesen getAllocatableSetForRC(MF, *I, Allocatable); 168bb5a039b76cc2cc6de6a5b6bdd4ebf6aefd9d564Jim Grosbach } 1695a0fabae5a1792d20df23b6cbd573a9121637d12Jim Grosbach 1705a0fabae5a1792d20df23b6cbd573a9121637d12Jim Grosbach // Mask out the reserved registers 1715a0fabae5a1792d20df23b6cbd573a9121637d12Jim Grosbach BitVector Reserved = getReservedRegs(MF); 17257ca3ccd455160e30e727ef53122c82edf3c6b50Benjamin Kramer Allocatable &= Reserved.flip(); 1735a0fabae5a1792d20df23b6cbd573a9121637d12Jim Grosbach 174bb4bdf4fe4c931e45d0a37e24ec79accd815c1d8Alkis Evlogimenos return Allocatable; 175f976c856fcc5055f3fc7d9f070d72c2d027c1d9dMisha Brukman} 176a99791886d5d4af2b900cd8cc1c9ed1677b6f0f4Jim Laskey 177fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesenstatic inline 178fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesenconst TargetRegisterClass *firstCommonClass(const uint32_t *A, 179fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen const uint32_t *B, 180f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const TargetRegisterInfo *TRI, 181f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const MVT::SimpleValueType SVT = 182f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar MVT::SimpleValueType::Any) { 183f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const MVT VT(SVT); 184fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32) 185f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (unsigned Common = *A++ & *B++) { 186f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const TargetRegisterClass *RC = 187f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar TRI->getRegClass(I + countTrailingZeros(Common)); 188f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (SVT == MVT::SimpleValueType::Any || RC->hasType(VT)) 189f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar return RC; 190f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar } 191dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 192fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen} 193fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen 194ba67d87fe4f0ec9a3d9729f1b0f3b70d85ac8357Jakob Stoklund Olesenconst TargetRegisterClass * 195e27e1ca3c90b69e78242c98a669337f84ccded7fJakob Stoklund OlesenTargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A, 196f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const TargetRegisterClass *B, 197f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const MVT::SimpleValueType SVT) const { 198c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen // First take care of the trivial cases. 199ba67d87fe4f0ec9a3d9729f1b0f3b70d85ac8357Jakob Stoklund Olesen if (A == B) 200ba67d87fe4f0ec9a3d9729f1b0f3b70d85ac8357Jakob Stoklund Olesen return A; 201ba67d87fe4f0ec9a3d9729f1b0f3b70d85ac8357Jakob Stoklund Olesen if (!A || !B) 202dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 203ba67d87fe4f0ec9a3d9729f1b0f3b70d85ac8357Jakob Stoklund Olesen 204c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen // Register classes are ordered topologically, so the largest common 205c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen // sub-class it the common sub-class with the smallest ID. 206f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this, SVT); 207ba67d87fe4f0ec9a3d9729f1b0f3b70d85ac8357Jakob Stoklund Olesen} 208dd63a063e2df0d0bc52b50732e3462fd58a636c0Jakob Stoklund Olesen 209dd63a063e2df0d0bc52b50732e3462fd58a636c0Jakob Stoklund Olesenconst TargetRegisterClass * 210dd63a063e2df0d0bc52b50732e3462fd58a636c0Jakob Stoklund OlesenTargetRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, 211dd63a063e2df0d0bc52b50732e3462fd58a636c0Jakob Stoklund Olesen const TargetRegisterClass *B, 212dd63a063e2df0d0bc52b50732e3462fd58a636c0Jakob Stoklund Olesen unsigned Idx) const { 213dd63a063e2df0d0bc52b50732e3462fd58a636c0Jakob Stoklund Olesen assert(A && B && "Missing register class"); 214dd63a063e2df0d0bc52b50732e3462fd58a636c0Jakob Stoklund Olesen assert(Idx && "Bad sub-register index"); 215dd63a063e2df0d0bc52b50732e3462fd58a636c0Jakob Stoklund Olesen 216dd63a063e2df0d0bc52b50732e3462fd58a636c0Jakob Stoklund Olesen // Find Idx in the list of super-register indices. 21789e38f87211f6cf34c8b2e88a06c275a70c05421Jakob Stoklund Olesen for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI) 218f191b43103113119e60b19b8e78966803a20c655Jakob Stoklund Olesen if (RCI.getSubReg() == Idx) 219f191b43103113119e60b19b8e78966803a20c655Jakob Stoklund Olesen // The bit mask contains all register classes that are projected into B 220f191b43103113119e60b19b8e78966803a20c655Jakob Stoklund Olesen // by Idx. Find a class that is also a sub-class of A. 221f191b43103113119e60b19b8e78966803a20c655Jakob Stoklund Olesen return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this); 222dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 223dd63a063e2df0d0bc52b50732e3462fd58a636c0Jakob Stoklund Olesen} 224fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen 225fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesenconst TargetRegisterClass *TargetRegisterInfo:: 226fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund OlesengetCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, 227fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen const TargetRegisterClass *RCB, unsigned SubB, 228fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen unsigned &PreA, unsigned &PreB) const { 229fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen assert(RCA && SubA && RCB && SubB && "Invalid arguments"); 230fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen 231fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // Search all pairs of sub-register indices that project into RCA and RCB 232fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // respectively. This is quadratic, but usually the sets are very small. On 233fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // most targets like X86, there will only be a single sub-register index 234fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // (e.g., sub_16bit projecting into GR16). 235fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // 236fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // The worst case is a register class like DPR on ARM. 237fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // We have indices dsub_0..dsub_7 projecting into that class. 238fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // 239fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // It is very common that one register class is a sub-register of the other. 240fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // Arrange for RCA to be the larger register so the answer will be found in 241fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // the first iteration. This makes the search linear for the most common 242fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // case. 243dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const TargetRegisterClass *BestRC = nullptr; 244fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen unsigned *BestPreA = &PreA; 245fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen unsigned *BestPreB = &PreB; 246fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen if (RCA->getSize() < RCB->getSize()) { 247fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen std::swap(RCA, RCB); 2489b23d57dc480a34eee9867be52b9c2022e8979f6Jakob Stoklund Olesen std::swap(SubA, SubB); 249fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen std::swap(BestPreA, BestPreB); 250fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen } 251fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen 252fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // Also terminate the search one we have found a register class as small as 253fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // RCA. 254fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen unsigned MinSize = RCA->getSize(); 255fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen 256fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) { 257fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA); 258fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) { 259fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // Check if a common super-register class exists for this index pair. 260fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen const TargetRegisterClass *RC = 261fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen firstCommonClass(IA.getMask(), IB.getMask(), this); 262fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen if (!RC || RC->getSize() < MinSize) 263fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen continue; 264fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen 265fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // The indexes must compose identically: PreA+SubA == PreB+SubB. 266fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB); 267fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen if (FinalA != FinalB) 268fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen continue; 269fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen 270fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // Is RC a better candidate than BestRC? 271fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen if (BestRC && RC->getSize() >= BestRC->getSize()) 272fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen continue; 273fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen 274fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // Yes, RC is the smallest super-register seen so far. 275fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen BestRC = RC; 276fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen *BestPreA = IA.getSubReg(); 277fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen *BestPreB = IB.getSubReg(); 278fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen 279fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen // Bail early if we reached MinSize. We won't find a better candidate. 280fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen if (BestRC->getSize() == MinSize) 281fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen return BestRC; 282fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen } 283fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen } 284fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen return BestRC; 285fd87839a4888840ab5718fd116ab169ac04126afJakob Stoklund Olesen} 2867eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen 287f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar/// \brief Check if the registers defined by the pair (RegisterClass, SubReg) 288f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar/// share the same register file. 289f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainarstatic bool shareSameRegisterFile(const TargetRegisterInfo &TRI, 290f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const TargetRegisterClass *DefRC, 291f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar unsigned DefSubReg, 292f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const TargetRegisterClass *SrcRC, 293f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar unsigned SrcSubReg) { 294f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar // Same register class. 295f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (DefRC == SrcRC) 296f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar return true; 297f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 298f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar // Both operands are sub registers. Check if they share a register class. 299f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar unsigned SrcIdx, DefIdx; 300f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (SrcSubReg && DefSubReg) { 301f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, 302f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar SrcIdx, DefIdx) != nullptr; 303f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar } 304f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 305f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar // At most one of the register is a sub register, make it Src to avoid 306f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar // duplicating the test. 307f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (!SrcSubReg) { 308f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar std::swap(DefSubReg, SrcSubReg); 309f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar std::swap(DefRC, SrcRC); 310f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar } 311f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 312f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar // One of the register is a sub register, check if we can get a superclass. 313f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (SrcSubReg) 314f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr; 315f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 316f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar // Plain copy. 317f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; 318f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar} 319f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 320f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainarbool TargetRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC, 321f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar unsigned DefSubReg, 322f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const TargetRegisterClass *SrcRC, 323f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar unsigned SrcSubReg) const { 324f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar // If this source does not incur a cross register bank copy, use it. 325f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg); 326f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar} 327f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 3287eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen// Compute target-independent register allocator hints to help eliminate copies. 3297eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesenvoid 3307eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund OlesenTargetRegisterInfo::getRegAllocationHints(unsigned VirtReg, 3317eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen ArrayRef<MCPhysReg> Order, 3327eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen SmallVectorImpl<MCPhysReg> &Hints, 3337eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen const MachineFunction &MF, 334f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const VirtRegMap *VRM, 335f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const LiveRegMatrix *Matrix) const { 3367eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen const MachineRegisterInfo &MRI = MF.getRegInfo(); 3377eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 3387eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen 3397eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen // Hints with HintType != 0 were set by target-dependent code. 3407eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen // Such targets must provide their own implementation of 3417eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen // TRI::getRegAllocationHints to interpret those hint types. 3427eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen assert(Hint.first == 0 && "Target must implement TRI::getRegAllocationHints"); 3437eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen 3447eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen // Target-independent hints are either a physical or a virtual register. 3457eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen unsigned Phys = Hint.second; 3467eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen if (VRM && isVirtualRegister(Phys)) 3477eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen Phys = VRM->getPhys(Phys); 3487eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen 3497eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen // Check that Phys is a valid hint in VirtReg's register class. 3507eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen if (!isPhysicalRegister(Phys)) 3517eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen return; 3527eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen if (MRI.isReserved(Phys)) 3537eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen return; 3547eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen // Check that Phys is in the allocation order. We shouldn't heed hints 3557eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen // from VirtReg's register class if they aren't in the allocation order. The 3567eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen // target probably has a reason for removing the register. 3577eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen if (std::find(Order.begin(), Order.end(), Phys) == Order.end()) 3587eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen return; 3597eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen 3607eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen // All clear, tell the register allocator to prefer this register. 3617eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen Hints.push_back(Phys); 3627eafc3e7be067709c6fcdae7b7fc4994c7ec2377Jakob Stoklund Olesen} 36337ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines 364f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainarbool TargetRegisterInfo::canRealignStack(const MachineFunction &MF) const { 365f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar return !MF.getFunction()->hasFnAttribute("no-realign-stack"); 366f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar} 367f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 368f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainarbool TargetRegisterInfo::needsStackRealignment( 369f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const MachineFunction &MF) const { 370f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const MachineFrameInfo *MFI = MF.getFrameInfo(); 371f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); 372f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const Function *F = MF.getFunction(); 373f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar unsigned StackAlign = TFI->getStackAlignment(); 374f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) || 375f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar F->hasFnAttribute(Attribute::StackAlignment)); 376f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (MF.getFunction()->hasFnAttribute("stackrealign") || requiresRealignment) { 377f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (canRealignStack(MF)) 378f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar return true; 379f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar DEBUG(dbgs() << "Can't realign function's stack: " << F->getName() << "\n"); 380f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar } 381f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar return false; 382f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar} 383f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 384de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarbool TargetRegisterInfo::regmaskSubsetEqual(const uint32_t *mask0, 385de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar const uint32_t *mask1) const { 386de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned N = (getNumRegs()+31) / 32; 387de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (unsigned I = 0; I < N; ++I) 388de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if ((mask0[I] & mask1[I]) != mask0[I]) 389de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return false; 390de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return true; 391de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar} 392de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 39337ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 39437ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hinesvoid 39537ed9c199ca639565f6ce88105f9e39e898d82d0Stephen HinesTargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex, 39637ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines const TargetRegisterInfo *TRI) { 39737ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines dbgs() << PrintReg(Reg, TRI, SubRegIndex) << "\n"; 39837ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines} 39937ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines#endif 400