1//===-- AArch64AsmBackend.cpp - AArch64 Assembler Backend -----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "AArch64.h"
11#include "AArch64RegisterInfo.h"
12#include "MCTargetDesc/AArch64FixupKinds.h"
13#include "llvm/ADT/Triple.h"
14#include "llvm/MC/MCAsmBackend.h"
15#include "llvm/MC/MCContext.h"
16#include "llvm/MC/MCDirectives.h"
17#include "llvm/MC/MCELFObjectWriter.h"
18#include "llvm/MC/MCFixupKindInfo.h"
19#include "llvm/MC/MCObjectWriter.h"
20#include "llvm/MC/MCSectionELF.h"
21#include "llvm/MC/MCSectionMachO.h"
22#include "llvm/MC/MCValue.h"
23#include "llvm/Support/ErrorHandling.h"
24#include "llvm/Support/MachO.h"
25using namespace llvm;
26
27namespace {
28
29class AArch64AsmBackend : public MCAsmBackend {
30  static const unsigned PCRelFlagVal =
31      MCFixupKindInfo::FKF_IsAlignedDownTo32Bits | MCFixupKindInfo::FKF_IsPCRel;
32public:
33  bool IsLittleEndian;
34
35public:
36  AArch64AsmBackend(const Target &T, bool IsLittleEndian)
37     : MCAsmBackend(), IsLittleEndian(IsLittleEndian) {}
38
39  unsigned getNumFixupKinds() const override {
40    return AArch64::NumTargetFixupKinds;
41  }
42
43  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
44    const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = {
45      // This table *must* be in the order that the fixup_* kinds are defined in
46      // AArch64FixupKinds.h.
47      //
48      // Name                           Offset (bits) Size (bits)     Flags
49      { "fixup_aarch64_pcrel_adr_imm21", 0, 32, PCRelFlagVal },
50      { "fixup_aarch64_pcrel_adrp_imm21", 0, 32, PCRelFlagVal },
51      { "fixup_aarch64_add_imm12", 10, 12, 0 },
52      { "fixup_aarch64_ldst_imm12_scale1", 10, 12, 0 },
53      { "fixup_aarch64_ldst_imm12_scale2", 10, 12, 0 },
54      { "fixup_aarch64_ldst_imm12_scale4", 10, 12, 0 },
55      { "fixup_aarch64_ldst_imm12_scale8", 10, 12, 0 },
56      { "fixup_aarch64_ldst_imm12_scale16", 10, 12, 0 },
57      { "fixup_aarch64_ldr_pcrel_imm19", 5, 19, PCRelFlagVal },
58      { "fixup_aarch64_movw", 5, 16, 0 },
59      { "fixup_aarch64_pcrel_branch14", 5, 14, PCRelFlagVal },
60      { "fixup_aarch64_pcrel_branch19", 5, 19, PCRelFlagVal },
61      { "fixup_aarch64_pcrel_branch26", 0, 26, PCRelFlagVal },
62      { "fixup_aarch64_pcrel_call26", 0, 26, PCRelFlagVal },
63      { "fixup_aarch64_tlsdesc_call", 0, 0, 0 }
64    };
65
66    if (Kind < FirstTargetFixupKind)
67      return MCAsmBackend::getFixupKindInfo(Kind);
68
69    assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
70           "Invalid kind!");
71    return Infos[Kind - FirstTargetFixupKind];
72  }
73
74  void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
75                  uint64_t Value, bool IsPCRel) const override;
76
77  bool mayNeedRelaxation(const MCInst &Inst) const override;
78  bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
79                            const MCRelaxableFragment *DF,
80                            const MCAsmLayout &Layout) const override;
81  void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
82                        MCInst &Res) const override;
83  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
84
85  void HandleAssemblerFlag(MCAssemblerFlag Flag) {}
86
87  unsigned getPointerSize() const { return 8; }
88
89  unsigned getFixupKindContainereSizeInBytes(unsigned Kind) const;
90};
91
92} // end anonymous namespace
93
94/// \brief The number of bytes the fixup may change.
95static unsigned getFixupKindNumBytes(unsigned Kind) {
96  switch (Kind) {
97  default:
98    llvm_unreachable("Unknown fixup kind!");
99
100  case AArch64::fixup_aarch64_tlsdesc_call:
101    return 0;
102
103  case FK_Data_1:
104    return 1;
105
106  case FK_Data_2:
107  case AArch64::fixup_aarch64_movw:
108    return 2;
109
110  case AArch64::fixup_aarch64_pcrel_branch14:
111  case AArch64::fixup_aarch64_add_imm12:
112  case AArch64::fixup_aarch64_ldst_imm12_scale1:
113  case AArch64::fixup_aarch64_ldst_imm12_scale2:
114  case AArch64::fixup_aarch64_ldst_imm12_scale4:
115  case AArch64::fixup_aarch64_ldst_imm12_scale8:
116  case AArch64::fixup_aarch64_ldst_imm12_scale16:
117  case AArch64::fixup_aarch64_ldr_pcrel_imm19:
118  case AArch64::fixup_aarch64_pcrel_branch19:
119    return 3;
120
121  case AArch64::fixup_aarch64_pcrel_adr_imm21:
122  case AArch64::fixup_aarch64_pcrel_adrp_imm21:
123  case AArch64::fixup_aarch64_pcrel_branch26:
124  case AArch64::fixup_aarch64_pcrel_call26:
125  case FK_Data_4:
126    return 4;
127
128  case FK_Data_8:
129    return 8;
130  }
131}
132
133static unsigned AdrImmBits(unsigned Value) {
134  unsigned lo2 = Value & 0x3;
135  unsigned hi19 = (Value & 0x1ffffc) >> 2;
136  return (hi19 << 5) | (lo2 << 29);
137}
138
139static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
140                                 MCContext *Ctx) {
141  unsigned Kind = Fixup.getKind();
142  int64_t SignedValue = static_cast<int64_t>(Value);
143  switch (Kind) {
144  default:
145    llvm_unreachable("Unknown fixup kind!");
146  case AArch64::fixup_aarch64_pcrel_adr_imm21:
147    if (Ctx && (SignedValue > 2097151 || SignedValue < -2097152))
148      Ctx->reportError(Fixup.getLoc(), "fixup value out of range");
149    return AdrImmBits(Value & 0x1fffffULL);
150  case AArch64::fixup_aarch64_pcrel_adrp_imm21:
151    return AdrImmBits((Value & 0x1fffff000ULL) >> 12);
152  case AArch64::fixup_aarch64_ldr_pcrel_imm19:
153  case AArch64::fixup_aarch64_pcrel_branch19:
154    // Signed 21-bit immediate
155    if (SignedValue > 2097151 || SignedValue < -2097152)
156      if (Ctx) Ctx->reportError(Fixup.getLoc(), "fixup value out of range");
157    if (Ctx && (Value & 0x3))
158      Ctx->reportError(Fixup.getLoc(), "fixup not sufficiently aligned");
159    // Low two bits are not encoded.
160    return (Value >> 2) & 0x7ffff;
161  case AArch64::fixup_aarch64_add_imm12:
162  case AArch64::fixup_aarch64_ldst_imm12_scale1:
163    // Unsigned 12-bit immediate
164    if (Ctx && Value >= 0x1000)
165      Ctx->reportError(Fixup.getLoc(), "fixup value out of range");
166    return Value;
167  case AArch64::fixup_aarch64_ldst_imm12_scale2:
168    // Unsigned 12-bit immediate which gets multiplied by 2
169    if (Ctx && (Value >= 0x2000))
170      Ctx->reportError(Fixup.getLoc(), "fixup value out of range");
171    if (Ctx && (Value & 0x1))
172      Ctx->reportError(Fixup.getLoc(), "fixup must be 2-byte aligned");
173    return Value >> 1;
174  case AArch64::fixup_aarch64_ldst_imm12_scale4:
175    // Unsigned 12-bit immediate which gets multiplied by 4
176    if (Ctx && (Value >= 0x4000))
177      Ctx->reportError(Fixup.getLoc(), "fixup value out of range");
178    if (Ctx && (Value & 0x3))
179      Ctx->reportError(Fixup.getLoc(), "fixup must be 4-byte aligned");
180    return Value >> 2;
181  case AArch64::fixup_aarch64_ldst_imm12_scale8:
182    // Unsigned 12-bit immediate which gets multiplied by 8
183    if (Ctx && (Value >= 0x8000))
184      Ctx->reportError(Fixup.getLoc(), "fixup value out of range");
185    if (Ctx && (Value & 0x7))
186      Ctx->reportError(Fixup.getLoc(), "fixup must be 8-byte aligned");
187    return Value >> 3;
188  case AArch64::fixup_aarch64_ldst_imm12_scale16:
189    // Unsigned 12-bit immediate which gets multiplied by 16
190    if (Ctx && (Value >= 0x10000))
191      Ctx->reportError(Fixup.getLoc(), "fixup value out of range");
192    if (Ctx && (Value & 0xf))
193      Ctx->reportError(Fixup.getLoc(), "fixup must be 16-byte aligned");
194    return Value >> 4;
195  case AArch64::fixup_aarch64_movw:
196    if (Ctx)
197      Ctx->reportError(Fixup.getLoc(),
198                       "no resolvable MOVZ/MOVK fixups supported yet");
199    return Value;
200  case AArch64::fixup_aarch64_pcrel_branch14:
201    // Signed 16-bit immediate
202    if (Ctx && (SignedValue > 32767 || SignedValue < -32768))
203      Ctx->reportError(Fixup.getLoc(), "fixup value out of range");
204    // Low two bits are not encoded (4-byte alignment assumed).
205    if (Ctx && (Value & 0x3))
206      Ctx->reportError(Fixup.getLoc(), "fixup not sufficiently aligned");
207    return (Value >> 2) & 0x3fff;
208  case AArch64::fixup_aarch64_pcrel_branch26:
209  case AArch64::fixup_aarch64_pcrel_call26:
210    // Signed 28-bit immediate
211    if (Ctx && (SignedValue > 134217727 || SignedValue < -134217728))
212      Ctx->reportError(Fixup.getLoc(), "fixup value out of range");
213    // Low two bits are not encoded (4-byte alignment assumed).
214    if (Ctx && (Value & 0x3))
215      Ctx->reportError(Fixup.getLoc(), "fixup not sufficiently aligned");
216    return (Value >> 2) & 0x3ffffff;
217  case FK_Data_1:
218  case FK_Data_2:
219  case FK_Data_4:
220  case FK_Data_8:
221    return Value;
222  }
223}
224
225/// getFixupKindContainereSizeInBytes - The number of bytes of the
226/// container involved in big endian or 0 if the item is little endian
227unsigned AArch64AsmBackend::getFixupKindContainereSizeInBytes(unsigned Kind) const {
228  if (IsLittleEndian)
229    return 0;
230
231  switch (Kind) {
232  default:
233    llvm_unreachable("Unknown fixup kind!");
234
235  case FK_Data_1:
236    return 1;
237  case FK_Data_2:
238    return 2;
239  case FK_Data_4:
240    return 4;
241  case FK_Data_8:
242    return 8;
243
244  case AArch64::fixup_aarch64_tlsdesc_call:
245  case AArch64::fixup_aarch64_movw:
246  case AArch64::fixup_aarch64_pcrel_branch14:
247  case AArch64::fixup_aarch64_add_imm12:
248  case AArch64::fixup_aarch64_ldst_imm12_scale1:
249  case AArch64::fixup_aarch64_ldst_imm12_scale2:
250  case AArch64::fixup_aarch64_ldst_imm12_scale4:
251  case AArch64::fixup_aarch64_ldst_imm12_scale8:
252  case AArch64::fixup_aarch64_ldst_imm12_scale16:
253  case AArch64::fixup_aarch64_ldr_pcrel_imm19:
254  case AArch64::fixup_aarch64_pcrel_branch19:
255  case AArch64::fixup_aarch64_pcrel_adr_imm21:
256  case AArch64::fixup_aarch64_pcrel_adrp_imm21:
257  case AArch64::fixup_aarch64_pcrel_branch26:
258  case AArch64::fixup_aarch64_pcrel_call26:
259    // Instructions are always little endian
260    return 0;
261  }
262}
263
264void AArch64AsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
265                                   unsigned DataSize, uint64_t Value,
266                                   bool IsPCRel) const {
267  unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
268  if (!Value)
269    return; // Doesn't change encoding.
270  MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
271  // Apply any target-specific value adjustments.
272  Value = adjustFixupValue(Fixup, Value, nullptr);
273
274  // Shift the value into position.
275  Value <<= Info.TargetOffset;
276
277  unsigned Offset = Fixup.getOffset();
278  assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
279
280  // Used to point to big endian bytes.
281  unsigned FulleSizeInBytes = getFixupKindContainereSizeInBytes(Fixup.getKind());
282
283  // For each byte of the fragment that the fixup touches, mask in the
284  // bits from the fixup value.
285  if (FulleSizeInBytes == 0) {
286    // Handle as little-endian
287    for (unsigned i = 0; i != NumBytes; ++i) {
288      Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
289    }
290  } else {
291    // Handle as big-endian
292    assert((Offset + FulleSizeInBytes) <= DataSize && "Invalid fixup size!");
293    assert(NumBytes <= FulleSizeInBytes && "Invalid fixup size!");
294    for (unsigned i = 0; i != NumBytes; ++i) {
295      unsigned Idx = FulleSizeInBytes - 1 - i;
296      Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
297    }
298  }
299}
300
301bool AArch64AsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
302  return false;
303}
304
305bool AArch64AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
306                                             uint64_t Value,
307                                             const MCRelaxableFragment *DF,
308                                             const MCAsmLayout &Layout) const {
309  // FIXME:  This isn't correct for AArch64. Just moving the "generic" logic
310  // into the targets for now.
311  //
312  // Relax if the value is too big for a (signed) i8.
313  return int64_t(Value) != int64_t(int8_t(Value));
314}
315
316void AArch64AsmBackend::relaxInstruction(const MCInst &Inst,
317                                         const MCSubtargetInfo &STI,
318                                         MCInst &Res) const {
319  llvm_unreachable("AArch64AsmBackend::relaxInstruction() unimplemented");
320}
321
322bool AArch64AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
323  // If the count is not 4-byte aligned, we must be writing data into the text
324  // section (otherwise we have unaligned instructions, and thus have far
325  // bigger problems), so just write zeros instead.
326  OW->WriteZeros(Count % 4);
327
328  // We are properly aligned, so write NOPs as requested.
329  Count /= 4;
330  for (uint64_t i = 0; i != Count; ++i)
331    OW->write32(0xd503201f);
332  return true;
333}
334
335namespace {
336
337namespace CU {
338
339/// \brief Compact unwind encoding values.
340enum CompactUnwindEncodings {
341  /// \brief A "frameless" leaf function, where no non-volatile registers are
342  /// saved. The return remains in LR throughout the function.
343  UNWIND_ARM64_MODE_FRAMELESS = 0x02000000,
344
345  /// \brief No compact unwind encoding available. Instead the low 23-bits of
346  /// the compact unwind encoding is the offset of the DWARF FDE in the
347  /// __eh_frame section. This mode is never used in object files. It is only
348  /// generated by the linker in final linked images, which have only DWARF info
349  /// for a function.
350  UNWIND_ARM64_MODE_DWARF = 0x03000000,
351
352  /// \brief This is a standard arm64 prologue where FP/LR are immediately
353  /// pushed on the stack, then SP is copied to FP. If there are any
354  /// non-volatile register saved, they are copied into the stack fame in pairs
355  /// in a contiguous ranger right below the saved FP/LR pair. Any subset of the
356  /// five X pairs and four D pairs can be saved, but the memory layout must be
357  /// in register number order.
358  UNWIND_ARM64_MODE_FRAME = 0x04000000,
359
360  /// \brief Frame register pair encodings.
361  UNWIND_ARM64_FRAME_X19_X20_PAIR = 0x00000001,
362  UNWIND_ARM64_FRAME_X21_X22_PAIR = 0x00000002,
363  UNWIND_ARM64_FRAME_X23_X24_PAIR = 0x00000004,
364  UNWIND_ARM64_FRAME_X25_X26_PAIR = 0x00000008,
365  UNWIND_ARM64_FRAME_X27_X28_PAIR = 0x00000010,
366  UNWIND_ARM64_FRAME_D8_D9_PAIR = 0x00000100,
367  UNWIND_ARM64_FRAME_D10_D11_PAIR = 0x00000200,
368  UNWIND_ARM64_FRAME_D12_D13_PAIR = 0x00000400,
369  UNWIND_ARM64_FRAME_D14_D15_PAIR = 0x00000800
370};
371
372} // end CU namespace
373
374// FIXME: This should be in a separate file.
375class DarwinAArch64AsmBackend : public AArch64AsmBackend {
376  const MCRegisterInfo &MRI;
377
378  /// \brief Encode compact unwind stack adjustment for frameless functions.
379  /// See UNWIND_ARM64_FRAMELESS_STACK_SIZE_MASK in compact_unwind_encoding.h.
380  /// The stack size always needs to be 16 byte aligned.
381  uint32_t encodeStackAdjustment(uint32_t StackSize) const {
382    return (StackSize / 16) << 12;
383  }
384
385public:
386  DarwinAArch64AsmBackend(const Target &T, const MCRegisterInfo &MRI)
387      : AArch64AsmBackend(T, /*IsLittleEndian*/true), MRI(MRI) {}
388
389  MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
390    return createAArch64MachObjectWriter(OS, MachO::CPU_TYPE_ARM64,
391                                         MachO::CPU_SUBTYPE_ARM64_ALL);
392  }
393
394  /// \brief Generate the compact unwind encoding from the CFI directives.
395  uint32_t generateCompactUnwindEncoding(
396                             ArrayRef<MCCFIInstruction> Instrs) const override {
397    if (Instrs.empty())
398      return CU::UNWIND_ARM64_MODE_FRAMELESS;
399
400    bool HasFP = false;
401    unsigned StackSize = 0;
402
403    uint32_t CompactUnwindEncoding = 0;
404    for (size_t i = 0, e = Instrs.size(); i != e; ++i) {
405      const MCCFIInstruction &Inst = Instrs[i];
406
407      switch (Inst.getOperation()) {
408      default:
409        // Cannot handle this directive:  bail out.
410        return CU::UNWIND_ARM64_MODE_DWARF;
411      case MCCFIInstruction::OpDefCfa: {
412        // Defines a frame pointer.
413        assert(getXRegFromWReg(MRI.getLLVMRegNum(Inst.getRegister(), true)) ==
414                   AArch64::FP &&
415               "Invalid frame pointer!");
416        assert(i + 2 < e && "Insufficient CFI instructions to define a frame!");
417
418        const MCCFIInstruction &LRPush = Instrs[++i];
419        assert(LRPush.getOperation() == MCCFIInstruction::OpOffset &&
420               "Link register not pushed!");
421        const MCCFIInstruction &FPPush = Instrs[++i];
422        assert(FPPush.getOperation() == MCCFIInstruction::OpOffset &&
423               "Frame pointer not pushed!");
424
425        unsigned LRReg = MRI.getLLVMRegNum(LRPush.getRegister(), true);
426        unsigned FPReg = MRI.getLLVMRegNum(FPPush.getRegister(), true);
427
428        LRReg = getXRegFromWReg(LRReg);
429        FPReg = getXRegFromWReg(FPReg);
430
431        assert(LRReg == AArch64::LR && FPReg == AArch64::FP &&
432               "Pushing invalid registers for frame!");
433
434        // Indicate that the function has a frame.
435        CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAME;
436        HasFP = true;
437        break;
438      }
439      case MCCFIInstruction::OpDefCfaOffset: {
440        assert(StackSize == 0 && "We already have the CFA offset!");
441        StackSize = std::abs(Inst.getOffset());
442        break;
443      }
444      case MCCFIInstruction::OpOffset: {
445        // Registers are saved in pairs. We expect there to be two consecutive
446        // `.cfi_offset' instructions with the appropriate registers specified.
447        unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true);
448        if (i + 1 == e)
449          return CU::UNWIND_ARM64_MODE_DWARF;
450
451        const MCCFIInstruction &Inst2 = Instrs[++i];
452        if (Inst2.getOperation() != MCCFIInstruction::OpOffset)
453          return CU::UNWIND_ARM64_MODE_DWARF;
454        unsigned Reg2 = MRI.getLLVMRegNum(Inst2.getRegister(), true);
455
456        // N.B. The encodings must be in register number order, and the X
457        // registers before the D registers.
458
459        // X19/X20 pair = 0x00000001,
460        // X21/X22 pair = 0x00000002,
461        // X23/X24 pair = 0x00000004,
462        // X25/X26 pair = 0x00000008,
463        // X27/X28 pair = 0x00000010
464        Reg1 = getXRegFromWReg(Reg1);
465        Reg2 = getXRegFromWReg(Reg2);
466
467        if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 &&
468            (CompactUnwindEncoding & 0xF1E) == 0)
469          CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X19_X20_PAIR;
470        else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 &&
471                 (CompactUnwindEncoding & 0xF1C) == 0)
472          CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X21_X22_PAIR;
473        else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 &&
474                 (CompactUnwindEncoding & 0xF18) == 0)
475          CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X23_X24_PAIR;
476        else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 &&
477                 (CompactUnwindEncoding & 0xF10) == 0)
478          CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X25_X26_PAIR;
479        else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 &&
480                 (CompactUnwindEncoding & 0xF00) == 0)
481          CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X27_X28_PAIR;
482        else {
483          Reg1 = getDRegFromBReg(Reg1);
484          Reg2 = getDRegFromBReg(Reg2);
485
486          // D8/D9 pair   = 0x00000100,
487          // D10/D11 pair = 0x00000200,
488          // D12/D13 pair = 0x00000400,
489          // D14/D15 pair = 0x00000800
490          if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 &&
491              (CompactUnwindEncoding & 0xE00) == 0)
492            CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D8_D9_PAIR;
493          else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 &&
494                   (CompactUnwindEncoding & 0xC00) == 0)
495            CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D10_D11_PAIR;
496          else if (Reg1 == AArch64::D12 && Reg2 == AArch64::D13 &&
497                   (CompactUnwindEncoding & 0x800) == 0)
498            CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D12_D13_PAIR;
499          else if (Reg1 == AArch64::D14 && Reg2 == AArch64::D15)
500            CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D14_D15_PAIR;
501          else
502            // A pair was pushed which we cannot handle.
503            return CU::UNWIND_ARM64_MODE_DWARF;
504        }
505
506        break;
507      }
508      }
509    }
510
511    if (!HasFP) {
512      // With compact unwind info we can only represent stack adjustments of up
513      // to 65520 bytes.
514      if (StackSize > 65520)
515        return CU::UNWIND_ARM64_MODE_DWARF;
516
517      CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAMELESS;
518      CompactUnwindEncoding |= encodeStackAdjustment(StackSize);
519    }
520
521    return CompactUnwindEncoding;
522  }
523};
524
525} // end anonymous namespace
526
527namespace {
528
529class ELFAArch64AsmBackend : public AArch64AsmBackend {
530public:
531  uint8_t OSABI;
532
533  ELFAArch64AsmBackend(const Target &T, uint8_t OSABI, bool IsLittleEndian)
534    : AArch64AsmBackend(T, IsLittleEndian), OSABI(OSABI) {}
535
536  MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
537    return createAArch64ELFObjectWriter(OS, OSABI, IsLittleEndian);
538  }
539
540  void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
541                         const MCFixup &Fixup, const MCFragment *DF,
542                         const MCValue &Target, uint64_t &Value,
543                         bool &IsResolved) override;
544};
545
546void ELFAArch64AsmBackend::processFixupValue(
547    const MCAssembler &Asm, const MCAsmLayout &Layout, const MCFixup &Fixup,
548    const MCFragment *DF, const MCValue &Target, uint64_t &Value,
549    bool &IsResolved) {
550  // The ADRP instruction adds some multiple of 0x1000 to the current PC &
551  // ~0xfff. This means that the required offset to reach a symbol can vary by
552  // up to one step depending on where the ADRP is in memory. For example:
553  //
554  //     ADRP x0, there
555  //  there:
556  //
557  // If the ADRP occurs at address 0xffc then "there" will be at 0x1000 and
558  // we'll need that as an offset. At any other address "there" will be in the
559  // same page as the ADRP and the instruction should encode 0x0. Assuming the
560  // section isn't 0x1000-aligned, we therefore need to delegate this decision
561  // to the linker -- a relocation!
562  if ((uint32_t)Fixup.getKind() == AArch64::fixup_aarch64_pcrel_adrp_imm21)
563    IsResolved = false;
564
565  // Try to get the encoded value for the fixup as-if we're mapping it into
566  // the instruction. This allows adjustFixupValue() to issue a diagnostic
567  // if the value is invalid.
568  if (IsResolved)
569    (void)adjustFixupValue(Fixup, Value, &Asm.getContext());
570}
571
572}
573
574MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T,
575                                              const MCRegisterInfo &MRI,
576                                              const Triple &TheTriple,
577                                              StringRef CPU) {
578  if (TheTriple.isOSBinFormatMachO())
579    return new DarwinAArch64AsmBackend(T, MRI);
580
581  assert(TheTriple.isOSBinFormatELF() && "Expect either MachO or ELF target");
582  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
583  return new ELFAArch64AsmBackend(T, OSABI, /*IsLittleEndian=*/true);
584}
585
586MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T,
587                                              const MCRegisterInfo &MRI,
588                                              const Triple &TheTriple,
589                                              StringRef CPU) {
590  assert(TheTriple.isOSBinFormatELF() &&
591         "Big endian is only supported for ELF targets!");
592  uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
593  return new ELFAArch64AsmBackend(T, OSABI,
594                                  /*IsLittleEndian=*/false);
595}
596