1de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar//===-- GCNHazardRecognizers.h - GCN Hazard Recognizers ---------*- C++ -*-===//
2de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar//
3de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar//                     The LLVM Compiler Infrastructure
4de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar//
5de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// This file is distributed under the University of Illinois Open Source
6de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// License. See LICENSE.TXT for details.
7de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar//
8de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar//===----------------------------------------------------------------------===//
9de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar//
10de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// This file defines hazard recognizers for scheduling on GCN processors.
11de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar//
12de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar//===----------------------------------------------------------------------===//
13de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar
14de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#ifndef LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
15de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#define LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
16de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar
17de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#include "llvm/ADT/STLExtras.h"
18de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
19de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#include <list>
20de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar
21de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarnamespace llvm {
22de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar
23de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarclass MachineFunction;
24de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarclass MachineInstr;
25de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarclass ScheduleDAG;
26de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarclass SIInstrInfo;
27de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarclass SISubtarget;
28de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar
29de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarclass GCNHazardRecognizer final : public ScheduleHazardRecognizer {
30de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar  // This variable stores the instruction that has been emitted this cycle. It
31de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar  // will be added to EmittedInstrs, when AdvanceCycle() or RecedeCycle() is
32de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar  // called.
33de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar  MachineInstr *CurrCycleInstr;
34de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar  std::list<MachineInstr*> EmittedInstrs;
35de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar  const MachineFunction &MF;
36de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar  const SISubtarget &ST;
37de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar
38de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar  int getWaitStatesSinceDef(unsigned Reg,
39de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar                            function_ref<bool(MachineInstr *)> IsHazardDef =
40de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar                                [](MachineInstr *) { return true; });
41de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar
42de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar  int checkSMEMSoftClauseHazards(MachineInstr *SMEM);
43de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar  int checkSMRDHazards(MachineInstr *SMRD);
44de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar  int checkVMEMHazards(MachineInstr* VMEM);
45de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar  int checkDPPHazards(MachineInstr *DPP);
46de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarpublic:
47de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar  GCNHazardRecognizer(const MachineFunction &MF);
48de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar  // We can only issue one instruction per cycle.
49de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar  bool atIssueLimit() const override { return true; }
50de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar  void EmitInstruction(SUnit *SU) override;
51de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar  void EmitInstruction(MachineInstr *MI) override;
52de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar  HazardType getHazardType(SUnit *SU, int Stalls) override;
53de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar  void EmitNoop() override;
54de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar  unsigned PreEmitNoops(SUnit *SU) override;
55de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar  unsigned PreEmitNoops(MachineInstr *) override;
56de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar  void AdvanceCycle() override;
57de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar  void RecedeCycle() override;
58de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar};
59de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar
60de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar} // end namespace llvm
61de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar
62de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#endif //LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
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