131d157ae1ac2cd9c787dc3c1d28e64c682803844Jia Liu//===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===// 2c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 3c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// The LLVM Compiler Infrastructure 4c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 5c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// This file is distributed under the University of Illinois Open Source 6c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// License. See LICENSE.TXT for details. 7c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 8c140c4803dc3e10e08138670829bc0494986abe9David Goodwin//===----------------------------------------------------------------------===// 9c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 10c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// This file contains the base ARM implementation of TargetRegisterInfo class. 11c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 12c140c4803dc3e10e08138670829bc0494986abe9David Goodwin//===----------------------------------------------------------------------===// 13c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 14c1f6f42049696e7357fb4837e1b25dabbaed3fe6Craig Topper#include "ARMBaseRegisterInfo.h" 15c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARM.h" 16db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin#include "ARMBaseInstrInfo.h" 1716c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov#include "ARMFrameLowering.h" 18c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMMachineFunctionInfo.h" 19c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMSubtarget.h" 20ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "MCTargetDesc/ARMAddressingModes.h" 21d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/ADT/BitVector.h" 22d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/ADT/SmallVector.h" 23c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineConstantPool.h" 24c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 25c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineFunction.h" 26c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 27c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineRegisterInfo.h" 28c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/RegisterScavenging.h" 29303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen#include "llvm/CodeGen/VirtRegMap.h" 300b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/Constants.h" 310b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/DerivedTypes.h" 320b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/Function.h" 330b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/LLVMContext.h" 343dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach#include "llvm/Support/Debug.h" 35ab7c09b6b6f4516a631fd6788918c237c83939afTorok Edwin#include "llvm/Support/ErrorHandling.h" 36dac237e18209b697a8ba122d0ddd9cad4dfba1f8Torok Edwin#include "llvm/Support/raw_ostream.h" 3716c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov#include "llvm/Target/TargetFrameLowering.h" 38c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/Target/TargetMachine.h" 39c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/Target/TargetOptions.h" 4073f50d9bc3bd46cc0abeba9bb0d46977ba1aea42Evan Cheng 4137ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines#define DEBUG_TYPE "arm-register-info" 4237ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines 4373f50d9bc3bd46cc0abeba9bb0d46977ba1aea42Evan Cheng#define GET_REGINFO_TARGET_DESC 44a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng#include "ARMGenRegisterInfo.inc" 45c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 461b4886dd00578038c0ca70b3bab97382b89def26Evan Chengusing namespace llvm; 471b4886dd00578038c0ca70b3bab97382b89def26Evan Cheng 484c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga NainarARMBaseRegisterInfo::ARMBaseRegisterInfo() 494c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), BasePtr(ARM::R6) {} 504c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar 514c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainarstatic unsigned getFramePointerReg(const ARMSubtarget &STI) { 52de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (STI.isTargetMachO()) 53de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return ARM::R7; 54de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar else if (STI.isTargetWindows()) 554c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar return ARM::R11; 56dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines else // ARM EABI 574c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar return STI.isThumb() ? ARM::R7 : ARM::R11; 58c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 59c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 60dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesconst MCPhysReg* 61c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 624c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>(); 63de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool UseSplitPush = STI.splitFramePushPop(); 64ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines const MCPhysReg *RegList = 65de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar STI.isTargetDarwin() 66de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar ? CSR_iOS_SaveList 67de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar : (UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList); 68bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover 69bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover const Function *F = MF->getFunction(); 70bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover if (F->getCallingConv() == CallingConv::GHC) { 7162da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin // GHC set of callee saved regs is empty as all those regs are 7262da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin // used for passing STG regs around 7362da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin return CSR_NoRegs_SaveList; 74bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover } else if (F->hasFnAttribute("interrupt")) { 75bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover if (STI.isMClass()) { 76bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover // M-class CPUs have hardware which saves the registers needed to allow a 77bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover // function conforming to the AAPCS to function as a handler. 78de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList; 79bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover } else if (F->getFnAttribute("interrupt").getValueAsString() == "FIQ") { 80bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover // Fast interrupt mode gives the handler a private copy of R8-R14, so less 81bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover // need to be saved to restore user-mode state. 82bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover return CSR_FIQ_SaveList; 83bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover } else { 84bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by 85bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover // exception handling. 86bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover return CSR_GenericInt_SaveList; 87bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover } 88bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover } 89bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover 90de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (STI.isTargetDarwin() && STI.getTargetLowering()->supportSwiftError() && 91de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar F->getAttributes().hasAttrSomewhere(Attribute::SwiftError)) 92de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return CSR_iOS_SwiftError_SaveList; 93de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 94de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (STI.isTargetDarwin() && F->getCallingConv() == CallingConv::CXX_FAST_TLS) 95de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return MF->getInfo<ARMFunctionInfo>()->isSplitCSR() 96de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar ? CSR_iOS_CXX_TLS_PE_SaveList 97de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar : CSR_iOS_CXX_TLS_SaveList; 98bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover return RegList; 993ee7d15284f188672e9e429e9e5cf7b870698677Jakob Stoklund Olesen} 100c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 101de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarconst MCPhysReg *ARMBaseRegisterInfo::getCalleeSavedRegsViaCopy( 102de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar const MachineFunction *MF) const { 103de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar assert(MF && "Invalid MachineFunction pointer."); 104de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS && 105de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MF->getInfo<ARMFunctionInfo>()->isSplitCSR()) 106de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return CSR_iOS_CXX_TLS_ViaCopy_SaveList; 107de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return nullptr; 108de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar} 109de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 1104c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainarconst uint32_t * 1114c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga NainarARMBaseRegisterInfo::getCallPreservedMask(const MachineFunction &MF, 1124c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar CallingConv::ID CC) const { 1134c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); 11462da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin if (CC == CallingConv::GHC) 11562da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin // This is academic becase all GHC calls are (supposed to be) tail calls 11662da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin return CSR_NoRegs_RegMask; 117de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 118de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (STI.isTargetDarwin() && STI.getTargetLowering()->supportSwiftError() && 119de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MF.getFunction()->getAttributes().hasAttrSomewhere(Attribute::SwiftError)) 120de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return CSR_iOS_SwiftError_RegMask; 121de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 122de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (STI.isTargetDarwin() && CC == CallingConv::CXX_FAST_TLS) 123de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return CSR_iOS_CXX_TLS_RegMask; 124ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines return STI.isTargetDarwin() ? CSR_iOS_RegMask : CSR_AAPCS_RegMask; 125c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 126c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 127e7bd51980a1341fb60322e5922cfcc0c9b92b165Chad Rosierconst uint32_t* 128165a7a925d73286abfc826b3d6339843b02c09e0Stephen LinARMBaseRegisterInfo::getNoPreservedMask() const { 129165a7a925d73286abfc826b3d6339843b02c09e0Stephen Lin return CSR_NoRegs_RegMask; 130456ca048af35163b9f52187e92a23ee0a9f059e8Stephen Lin} 131456ca048af35163b9f52187e92a23ee0a9f059e8Stephen Lin 1324c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainarconst uint32_t * 133de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga NainarARMBaseRegisterInfo::getTLSCallPreservedMask(const MachineFunction &MF) const { 134de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar assert(MF.getSubtarget<ARMSubtarget>().isTargetDarwin() && 135de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar "only know about special TLS call on Darwin"); 136de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return CSR_iOS_TLSCall_RegMask; 137de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar} 138de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 139de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 140de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarconst uint32_t * 1414c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga NainarARMBaseRegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF, 1424c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar CallingConv::ID CC) const { 1434c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); 144165a7a925d73286abfc826b3d6339843b02c09e0Stephen Lin // This should return a register mask that is the same as that returned by 145165a7a925d73286abfc826b3d6339843b02c09e0Stephen Lin // getCallPreservedMask but that additionally preserves the register used for 146165a7a925d73286abfc826b3d6339843b02c09e0Stephen Lin // the first i32 argument (which must also be the register used to return a 147165a7a925d73286abfc826b3d6339843b02c09e0Stephen Lin // single i32 return value) 148165a7a925d73286abfc826b3d6339843b02c09e0Stephen Lin // 149165a7a925d73286abfc826b3d6339843b02c09e0Stephen Lin // In case that the calling convention does not use the same register for 15062da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin // both or otherwise does not want to enable this optimization, the function 15162da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin // should return NULL 15262da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin if (CC == CallingConv::GHC) 15362da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin // This is academic becase all GHC calls are (supposed to be) tail calls 154dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 155ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines return STI.isTargetDarwin() ? CSR_iOS_ThisReturn_RegMask 156ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines : CSR_AAPCS_ThisReturn_RegMask; 157e7bd51980a1341fb60322e5922cfcc0c9b92b165Chad Rosier} 158e7bd51980a1341fb60322e5922cfcc0c9b92b165Chad Rosier 1599631864688c593711f82bb8d21f8b724c628d786Jim GrosbachBitVector ARMBaseRegisterInfo:: 1609631864688c593711f82bb8d21f8b724c628d786Jim GrosbachgetReservedRegs(const MachineFunction &MF) const { 1614c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); 162f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const ARMFrameLowering *TFI = getFrameLowering(MF); 163d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov 1647a2bdde0a0eebcd2125055e0eacaca040f0b766cChris Lattner // FIXME: avoid re-calculating this every time. 165c140c4803dc3e10e08138670829bc0494986abe9David Goodwin BitVector Reserved(getNumRegs()); 166c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(ARM::SP); 167c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(ARM::PC); 1684f92b5e6163b16d63eb63269c2aec670b55ea19aLang Hames Reserved.set(ARM::FPSCR); 169f86e436fb95670ed110818fefa403f21ae104639Mihai Popa Reserved.set(ARM::APSR_NZCV); 170d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov if (TFI->hasFP(MF)) 1714c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar Reserved.set(getFramePointerReg(STI)); 17265482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach if (hasBasePointer(MF)) 17365482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach Reserved.set(BasePtr); 174c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Some targets reserve R9. 175c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (STI.isR9Reserved()) 176c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(ARM::R9); 1773b6434e360315849a65b1ac85e16d160131a77a4Jakob Stoklund Olesen // Reserve D16-D31 if the subtarget doesn't support them. 1783b6434e360315849a65b1ac85e16d160131a77a4Jakob Stoklund Olesen if (!STI.hasVFP3() || STI.hasD16()) { 179de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!"); 180de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar Reserved.set(ARM::D16, ARM::D31 + 1); 1813b6434e360315849a65b1ac85e16d160131a77a4Jakob Stoklund Olesen } 182cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen const TargetRegisterClass *RC = &ARM::GPRPairRegClass; 183cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I) 184cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI) 185cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen if (Reserved.test(*SI)) Reserved.set(*I); 186cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen 187c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return Reserved; 188c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 189c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1904c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainarconst TargetRegisterClass * 1914c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga NainarARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, 1924c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar const MachineFunction &) const { 193c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen const TargetRegisterClass *Super = RC; 194c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); 195c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen do { 196c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen switch (Super->getID()) { 197c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::GPRRegClassID: 198c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::SPRRegClassID: 199c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::DPRRegClassID: 200c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::QPRRegClassID: 201c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::QQPRRegClassID: 202c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::QQQQPRRegClassID: 203cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen case ARM::GPRPairRegClassID: 204c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen return Super; 205c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen } 206c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen Super = *I++; 207c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen } while (Super); 208c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen return RC; 209c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen} 210b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng 2114f54c1293af174a8002db20faf7b4f82ba4e8514Evan Chengconst TargetRegisterClass * 212397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund OlesenARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 213397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen const { 214420761a0f193e87d08ee1c51b26bba23ab4bac7fCraig Topper return &ARM::GPRRegClass; 215c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 216be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich 217342e3161d9dd4fa485b47788aa0266f9c91c3832Evan Chengconst TargetRegisterClass * 218342e3161d9dd4fa485b47788aa0266f9c91c3832Evan ChengARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { 219342e3161d9dd4fa485b47788aa0266f9c91c3832Evan Cheng if (RC == &ARM::CCRRegClass) 22037ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines return &ARM::rGPRRegClass; // Can't copy CCR registers. 221342e3161d9dd4fa485b47788aa0266f9c91c3832Evan Cheng return RC; 222342e3161d9dd4fa485b47788aa0266f9c91c3832Evan Cheng} 223342e3161d9dd4fa485b47788aa0266f9c91c3832Evan Cheng 224be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarichunsigned 225be2119e8e2bc7006cfd638a24367acbfda625d16Cameron ZwarichARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 226be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich MachineFunction &MF) const { 2274c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); 228f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const ARMFrameLowering *TFI = getFrameLowering(MF); 229be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich 230be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich switch (RC->getID()) { 231be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich default: 232be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich return 0; 233be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich case ARM::tGPRRegClassID: 234be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich return TFI->hasFP(MF) ? 4 : 5; 235be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich case ARM::GPRRegClassID: { 236be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich unsigned FP = TFI->hasFP(MF) ? 1 : 0; 237be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich return 10 - FP - (STI.isR9Reserved() ? 1 : 0); 238be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich } 239be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich case ARM::SPRRegClassID: // Currently not used as 'rep' register class. 240be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich case ARM::DPRRegClassID: 241be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich return 32 - 10; 242be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich } 243be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich} 244c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 245303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen// Get the other register in a GPRPair. 246303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesenstatic unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) { 247303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers) 248303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen if (ARM::GPRPairRegClass.contains(*Supers)) 249303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0); 250303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen return 0; 251303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen} 252303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen 253303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen// Resolve the RegPairEven / RegPairOdd register allocator hints. 254303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesenvoid 255303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund OlesenARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, 256303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen ArrayRef<MCPhysReg> Order, 257303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen SmallVectorImpl<MCPhysReg> &Hints, 258303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen const MachineFunction &MF, 259f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const VirtRegMap *VRM, 260f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const LiveRegMatrix *Matrix) const { 261303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen const MachineRegisterInfo &MRI = MF.getRegInfo(); 262303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 263303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen 264303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen unsigned Odd; 265303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen switch (Hint.first) { 266303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen case ARMRI::RegPairEven: 267303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen Odd = 0; 268303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen break; 269303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen case ARMRI::RegPairOdd: 270303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen Odd = 1; 271303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen break; 272303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen default: 273303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM); 274303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen return; 275303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen } 276303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen 277303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen // This register should preferably be even (Odd == 0) or odd (Odd == 1). 278303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen // Check if the other part of the pair has already been assigned, and provide 279303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen // the paired register as the first hint. 2800c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned Paired = Hint.second; 2810c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (Paired == 0) 2820c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return; 2830c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 284303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen unsigned PairedPhys = 0; 2850c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (TargetRegisterInfo::isPhysicalRegister(Paired)) { 2860c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar PairedPhys = Paired; 2870c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } else if (VRM && VRM->hasPhys(Paired)) { 2880c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar PairedPhys = getPairedGPR(VRM->getPhys(Paired), Odd, this); 289303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen } 290303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen 291303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen // First prefer the paired physreg. 2924fd4c91c40fa40ae4cd671b03056de8c3c961046Jim Grosbach if (PairedPhys && 2934fd4c91c40fa40ae4cd671b03056de8c3c961046Jim Grosbach std::find(Order.begin(), Order.end(), PairedPhys) != Order.end()) 294303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen Hints.push_back(PairedPhys); 295303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen 296303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen // Then prefer even or odd registers. 297303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen for (unsigned I = 0, E = Order.size(); I != E; ++I) { 298303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen unsigned Reg = Order[I]; 299303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd) 300303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen continue; 301303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen // Don't provide hints that are paired to a reserved register. 302303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen unsigned Paired = getPairedGPR(Reg, !Odd, this); 303303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen if (!Paired || MRI.isReserved(Paired)) 304303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen continue; 305303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen Hints.push_back(Reg); 306303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen } 307303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen} 308303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen 309c140c4803dc3e10e08138670829bc0494986abe9David Goodwinvoid 310ebe69fe11e48d322045d5949c83283927a0d790bStephen HinesARMBaseRegisterInfo::updateRegAllocHint(unsigned Reg, unsigned NewReg, 311c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MachineFunction &MF) const { 312c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MachineRegisterInfo *MRI = &MF.getRegInfo(); 313c140c4803dc3e10e08138670829bc0494986abe9David Goodwin std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 314c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 315c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Hint.first == (unsigned)ARMRI::RegPairEven) && 316c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen TargetRegisterInfo::isVirtualRegister(Hint.second)) { 317c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // If 'Reg' is one of the even / odd register pair and it's now changed 318c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // (e.g. coalesced) into a different register. The other register of the 319c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // pair allocation hint must be updated to reflect the relationship 320c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // change. 321c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned OtherReg = Hint.second; 322c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Hint = MRI->getRegAllocationHint(OtherReg); 3230c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Make sure the pair has not already divorced. 3240c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (Hint.second == Reg) { 325c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 3260c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (TargetRegisterInfo::isVirtualRegister(NewReg)) 3270c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MRI->setRegAllocationHint(NewReg, 3280c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Hint.first == (unsigned)ARMRI::RegPairOdd ? ARMRI::RegPairEven 3290c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar : ARMRI::RegPairOdd, OtherReg); 3300c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 331c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 332c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 333f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson 33465482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbachbool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 3356a8700301ca6f8f2f5f787c8d1f5206a7dfceed6Daniel Dunbar const MachineFrameInfo *MFI = MF.getFrameInfo(); 3361755b3964f931bdd6fa9b4c0138f666ccfa12acaJim Grosbach const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 337f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const ARMFrameLowering *TFI = getFrameLowering(MF); 33865482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach 3390f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // When outgoing call frames are so large that we adjust the stack pointer 3400f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // around the call, we can no longer use the stack pointer to reach the 3410f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // emergency spill slot. 342055a8127c9ffee287807fe7cc1b115d0f40162b0Bob Wilson if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF)) 34365482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach return true; 34465482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach 34565482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited 34665482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // negative range for ldr/str (255), and thumb1 is positive offsets only. 34765482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // It's going to be better to use the SP or Base Pointer instead. When there 34865482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // are variable sized objects, we can't reference off of the SP, so we 34965482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // reserve a Base Pointer. 35065482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) { 35165482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // Conservatively estimate whether the negative offset from the frame 35265482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // pointer will be sufficient to reach. If a function has a smallish 35365482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // frame, it's less likely to have lots of spills and callee saved 35465482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // space, so it's all more likely to be within range of the frame pointer. 35565482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // If it's wrong, the scavenger will still enable access to work, it just 35665482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // won't be optimal. 35765482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128) 35865482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach return false; 35965482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach return true; 36065482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach } 36165482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach 36265482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach return false; 36365482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach} 36465482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach 36565482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbachbool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { 36654f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen const MachineRegisterInfo *MRI = &MF.getRegInfo(); 3676690bca623d1f6405b95db5b1760f7ba8436e3fbChad Rosier const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 368f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const ARMFrameLowering *TFI = getFrameLowering(MF); 36930c93e1cd3e43e174994834900325fcff3322288Jim Grosbach // We can't realign the stack if: 37030c93e1cd3e43e174994834900325fcff3322288Jim Grosbach // 1. Dynamic stack realignment is explicitly disabled, 3716690bca623d1f6405b95db5b1760f7ba8436e3fbChad Rosier // 2. This is a Thumb1 function (it's not useful, so we don't bother), or 3726690bca623d1f6405b95db5b1760f7ba8436e3fbChad Rosier // 3. There are VLAs in the function and the base pointer is disabled. 373f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (!TargetRegisterInfo::canRealignStack(MF)) 37454f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen return false; 37554f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen if (AFI->isThumb1OnlyFunction()) 37654f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen return false; 37754f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen // Stack realignment requires a frame pointer. If we already started 37854f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen // register allocation with frame pointer elimination, it is too late now. 3794c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar if (!MRI->canReserveReg(getFramePointerReg(MF.getSubtarget<ARMSubtarget>()))) 38054f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen return false; 381aaa1e2f820e61a2f4b878d97599b3ca093bc96edBob Wilson // We may also need a base pointer if there are dynamic allocas or stack 382aaa1e2f820e61a2f4b878d97599b3ca093bc96edBob Wilson // pointer adjustments around calls. 383f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (TFI->hasReservedCallFrame(MF)) 38454f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen return true; 38554f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen // A base pointer is required and allowed. Check that it isn't too late to 38654f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen // reserve it. 38754f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen return MRI->canReserveReg(BasePtr); 388e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3Jim Grosbach} 389e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3Jim Grosbach 3903dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbachbool ARMBaseRegisterInfo:: 3919631864688c593711f82bb8d21f8b724c628d786Jim GrosbachcannotEliminateFrame(const MachineFunction &MF) const { 39298a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng const MachineFrameInfo *MFI = MF.getFrameInfo(); 3938a8d479214745c82ef00f08d4e4f1c173b5f9ce2Nick Lewycky if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack()) 39498a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng return true; 39531bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() 39631bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach || needsStackRealignment(MF); 39798a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng} 39898a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng 3995c33f5bf67f61e3a1addda6de735d28d550dd0ebJim Grosbachunsigned 4003f2bf85d14759cc4b28a86805f566ac805a54d00David GreeneARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 4014c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); 402f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const ARMFrameLowering *TFI = getFrameLowering(MF); 403d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov 404d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov if (TFI->hasFP(MF)) 4054c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar return getFramePointerReg(STI); 406c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::SP; 407c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 408c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 409db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// emitLoadConstPool - Emits a load from constpool to materialize the 410db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// specified immediate. 411de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarvoid ARMBaseRegisterInfo::emitLoadConstPool( 412de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 413de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, 414de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { 415db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineFunction &MF = *MBB.getParent(); 41637ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 417db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineConstantPool *ConstantPool = MF.getConstantPool(); 41846510a73e977273ec67747eb34cbdb43f815e451Dan Gohman const Constant *C = 4191d0be15f89cb5056e20e2d24faa8d6afb1573bcaOwen Anderson ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); 420db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 421db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 422378445303b10b092a898a75131141a8259cff50bEvan Cheng BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 423378445303b10b092a898a75131141a8259cff50bEvan Cheng .addReg(DestReg, getDefRegState(true), SubIdx) 424db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin .addConstantPoolIndex(Idx) 4253daccd82d3151fa3629de430b55698a81084fc9eAnton Korobeynikov .addImm(0).addImm(Pred).addReg(PredReg) 4263daccd82d3151fa3629de430b55698a81084fc9eAnton Korobeynikov .setMIFlags(MIFlags); 427db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 428db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 429db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinbool ARMBaseRegisterInfo:: 430db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinrequiresRegisterScavenging(const MachineFunction &MF) const { 431db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return true; 432db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 43341fff8c19ab6d8e28f5362481c184ad628f8c704Jim Grosbach 4347e831db1d4f5dc51ca6526739cf41e59895c5c20Jim Grosbachbool ARMBaseRegisterInfo:: 4356a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston GurdtrackLivenessAfterRegAlloc(const MachineFunction &MF) const { 4366a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd return true; 4376a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd} 4386a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd 4396a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurdbool ARMBaseRegisterInfo:: 4407e831db1d4f5dc51ca6526739cf41e59895c5c20Jim GrosbachrequiresFrameIndexScavenging(const MachineFunction &MF) const { 441ca5dfb71ba4aa4a8392a021ec056cf0b70f74f1eJim Grosbach return true; 4427e831db1d4f5dc51ca6526739cf41e59895c5c20Jim Grosbach} 443db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 444a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbachbool ARMBaseRegisterInfo:: 445a273442891ae20fd8192526132e3819ea9e5eda9Jim GrosbachrequiresVirtualBaseRegisters(const MachineFunction &MF) const { 446c8cd8aa9d8582d2632db8fee8b2932efcdec34f1Jim Grosbach return true; 447a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach} 448a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach 449e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbachint64_t ARMBaseRegisterInfo:: 4501ab3f16f06698596716593a30545799688acccd7Jim GrosbachgetFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { 451e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = MI->getDesc(); 452e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 45390f20044ade3712c8b0c3f4ebe47d57ad15ae6ceChad Rosier int64_t InstrOffs = 0; 454e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach int Scale = 1; 455e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach unsigned ImmIdx = 0; 4561ab3f16f06698596716593a30545799688acccd7Jim Grosbach switch (AddrMode) { 457e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrModeT2_i8: 458e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrModeT2_i12: 4593e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARMII::AddrMode_i12: 460e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = MI->getOperand(Idx+1).getImm(); 461e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach Scale = 1; 462e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 463e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrMode5: { 464e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach // VFP address mode. 465e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach const MachineOperand &OffOp = MI->getOperand(Idx+1); 466f78ee6316bc755779920ac207edc27a89c0bd2f9Jim Grosbach InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); 467e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) 468e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = -InstrOffs; 469e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach Scale = 4; 470e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 471e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 472e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrMode2: { 473e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach ImmIdx = Idx+2; 474e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); 475e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 476e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = -InstrOffs; 477e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 478e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 479e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrMode3: { 480e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach ImmIdx = Idx+2; 481e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); 482e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 483e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = -InstrOffs; 484e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 485e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 486e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrModeT1_s: { 487e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach ImmIdx = Idx+1; 488e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = MI->getOperand(ImmIdx).getImm(); 489e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach Scale = 4; 490e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 491e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 492e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach default: 493e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach llvm_unreachable("Unsupported addressing mode!"); 494e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 495e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach 496e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach return InstrOffs * Scale; 497e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach} 498e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach 4998708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// needsFrameBaseReg - Returns true if the instruction's frame index 5008708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// reference would be better served by a base register other than FP 5018708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// or SP. Used by LocalStackFrameAllocation to determine which frame index 5028708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// references it should create new base registers for. 5038708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbachbool ARMBaseRegisterInfo:: 5043197380143cdc18837722129ac888528b9fbfc2bJim GrosbachneedsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 5053197380143cdc18837722129ac888528b9fbfc2bJim Grosbach for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) { 5063197380143cdc18837722129ac888528b9fbfc2bJim Grosbach assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 5073197380143cdc18837722129ac888528b9fbfc2bJim Grosbach } 5088708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 5098708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // It's the load/store FI references that cause issues, as it can be difficult 5108708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // to materialize the offset if it won't fit in the literal field. Estimate 5118708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // based on the size of the local frame and some conservative assumptions 5128708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // about the rest of the stack frame (note, this is pre-regalloc, so 5138708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // we don't know everything for certain yet) whether this offset is likely 5148708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // to be out of range of the immediate. Return true if so. 5158708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 516cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach // We only generate virtual base registers for loads and stores, so 517cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach // return false for everything else. 5188708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach unsigned Opc = MI->getOpcode(); 5198708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach switch (Opc) { 520cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12: 5217e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach case ARM::STRi12: case ARM::STRH: case ARM::STRBi12: 522cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRi12: case ARM::t2LDRi8: 523cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2STRi12: case ARM::t2STRi8: 5248708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach case ARM::VLDRS: case ARM::VLDRD: 5258708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach case ARM::VSTRS: case ARM::VSTRD: 52674d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach case ARM::tSTRspi: case ARM::tLDRspi: 527cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach break; 5288708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach default: 5298708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach return false; 5308708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach } 531cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach 532cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach // Without a virtual base register, if the function has variable sized 533cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach // objects, all fixed-size local references will be via the frame pointer, 5343197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Approximate the offset and see if it's legal for the instruction. 5353197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Note that the incoming offset is based on the SP value at function entry, 5363197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // so it'll be negative. 5373197380143cdc18837722129ac888528b9fbfc2bJim Grosbach MachineFunction &MF = *MI->getParent()->getParent(); 538f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const ARMFrameLowering *TFI = getFrameLowering(MF); 5393197380143cdc18837722129ac888528b9fbfc2bJim Grosbach MachineFrameInfo *MFI = MF.getFrameInfo(); 5403197380143cdc18837722129ac888528b9fbfc2bJim Grosbach ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 5413197380143cdc18837722129ac888528b9fbfc2bJim Grosbach 5423197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Estimate an offset from the frame pointer. 5433197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Conservatively assume all callee-saved registers get pushed. R4-R6 5443197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // will be earlier than the FP, so we ignore those. 5453197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // R7, LR 5463197380143cdc18837722129ac888528b9fbfc2bJim Grosbach int64_t FPOffset = Offset - 8; 5473197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15 5483197380143cdc18837722129ac888528b9fbfc2bJim Grosbach if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction()) 5493197380143cdc18837722129ac888528b9fbfc2bJim Grosbach FPOffset -= 80; 5503197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Estimate an offset from the stack pointer. 551c1dc78de762e8a65fe1edd0cced13d94ab5a971fJim Grosbach // The incoming offset is relating to the SP at the start of the function, 552c1dc78de762e8a65fe1edd0cced13d94ab5a971fJim Grosbach // but when we access the local it'll be relative to the SP after local 553c1dc78de762e8a65fe1edd0cced13d94ab5a971fJim Grosbach // allocation, so adjust our SP-relative offset by that allocation size. 554c1dc78de762e8a65fe1edd0cced13d94ab5a971fJim Grosbach Offset += MFI->getLocalFrameSize(); 5553197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Assume that we'll have at least some spill slots allocated. 5563197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // FIXME: This is a total SWAG number. We should run some statistics 5573197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // and pick a real one. 5583197380143cdc18837722129ac888528b9fbfc2bJim Grosbach Offset += 128; // 128 bytes of spill slots 5593197380143cdc18837722129ac888528b9fbfc2bJim Grosbach 560ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // If there's a frame pointer and the addressing mode allows it, try using it. 5613197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // The FP is only available if there is no dynamic realignment. We 5623197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // don't know for sure yet whether we'll need that, so we guess based 5633197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // on whether there are any local variables that would trigger it. 56416c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov unsigned StackAlign = TFI->getStackAlignment(); 565ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines if (TFI->hasFP(MF) && 5663197380143cdc18837722129ac888528b9fbfc2bJim Grosbach !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) { 5674c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar if (isFrameOffsetLegal(MI, getFrameRegister(MF), FPOffset)) 5683197380143cdc18837722129ac888528b9fbfc2bJim Grosbach return false; 5693197380143cdc18837722129ac888528b9fbfc2bJim Grosbach } 5703197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // If we can reference via the stack pointer, try that. 5713197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // FIXME: This (and the code that resolves the references) can be improved 5723197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // to only disallow SP relative references in the live range of 5733197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // the VLA(s). In practice, it's unclear how much difference that 5743197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // would make, but it may be worth doing. 5754c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, ARM::SP, Offset)) 5763197380143cdc18837722129ac888528b9fbfc2bJim Grosbach return false; 577cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach 5783197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // The offset likely isn't legal, we want to allocate a virtual base register. 579cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach return true; 5808708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach} 5818708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 582976ef86689ed065361a748f81c44ca3510af2202Bill Wendling/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to 583976ef86689ed065361a748f81c44ca3510af2202Bill Wendling/// be a pointer to FrameIdx at the beginning of the basic block. 584dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbachvoid ARMBaseRegisterInfo:: 585976ef86689ed065361a748f81c44ca3510af2202Bill WendlingmaterializeFrameBaseRegister(MachineBasicBlock *MBB, 586976ef86689ed065361a748f81c44ca3510af2202Bill Wendling unsigned BaseReg, int FrameIdx, 587976ef86689ed065361a748f81c44ca3510af2202Bill Wendling int64_t Offset) const { 588976ef86689ed065361a748f81c44ca3510af2202Bill Wendling ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>(); 58974d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : 59037ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines (AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri); 591dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 592976ef86689ed065361a748f81c44ca3510af2202Bill Wendling MachineBasicBlock::iterator Ins = MBB->begin(); 593976ef86689ed065361a748f81c44ca3510af2202Bill Wendling DebugLoc DL; // Defaults to "unknown" 594976ef86689ed065361a748f81c44ca3510af2202Bill Wendling if (Ins != MBB->end()) 595976ef86689ed065361a748f81c44ca3510af2202Bill Wendling DL = Ins->getDebugLoc(); 596976ef86689ed065361a748f81c44ca3510af2202Bill Wendling 597397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen const MachineFunction &MF = *MBB->getParent(); 59857148c166ab232191098492633c924fad9c44ef3Bill Wendling MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 59937ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 60057148c166ab232191098492633c924fad9c44ef3Bill Wendling const MCInstrDesc &MCID = TII.get(ADDriOpc); 601397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 60221803721d538255e4d223c29b6c8d3c9e93d4d86Cameron Zwarich 60337ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg) 60437ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines .addFrameIndex(FrameIdx).addImm(Offset); 605976ef86689ed065361a748f81c44ca3510af2202Bill Wendling 60674d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach if (!AFI->isThumb1OnlyFunction()) 60737ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines AddDefaultCC(AddDefaultPred(MIB)); 608dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach} 609dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 61036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hinesvoid ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 61136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines int64_t Offset) const { 612dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach MachineBasicBlock &MBB = *MI.getParent(); 613dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach MachineFunction &MF = *MBB.getParent(); 61457148c166ab232191098492633c924fad9c44ef3Bill Wendling const ARMBaseInstrInfo &TII = 61537ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); 616dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 617dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach int Off = Offset; // ARM doesn't need the general 64-bit offsets 618dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach unsigned i = 0; 619dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 620dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach assert(!AFI->isThumb1OnlyFunction() && 621dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach "This resolveFrameIndex does not support Thumb1!"); 622dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 623dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach while (!MI.getOperand(i).isFI()) { 624dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach ++i; 625dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 626dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach } 627dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach bool Done = false; 628dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach if (!AFI->isThumbFunction()) 629dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); 630dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach else { 631dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach assert(AFI->isThumb2Function()); 632dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII); 633dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach } 634dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach assert (Done && "Unable to resolve frame index!"); 6351f6a329f79b3568d379142f921f59c4143ddaa14Duncan Sands (void)Done; 636dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach} 6378708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 6384c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainarbool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, 639e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach int64_t Offset) const { 640e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = MI->getDesc(); 6412b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 6422b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned i = 0; 6432b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 6442b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach while (!MI->getOperand(i).isFI()) { 6452b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach ++i; 6462b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 6472b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach } 6482b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 6492b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach // AddrMode4 and AddrMode6 cannot handle any offset. 6502b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) 6512b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach return Offset == 0; 6522b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 6532b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned NumBits = 0; 6542b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned Scale = 1; 655e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach bool isSigned = true; 6561ab3f16f06698596716593a30545799688acccd7Jim Grosbach switch (AddrMode) { 6572b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach case ARMII::AddrModeT2_i8: 6582b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach case ARMII::AddrModeT2_i12: 6592b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach // i8 supports only negative, and i12 supports only positive, so 6602b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach // based on Offset sign, consider the appropriate instruction 66174d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach Scale = 1; 6622b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach if (Offset < 0) { 6632b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 8; 6642b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach Offset = -Offset; 6652b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach } else { 6662b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 12; 6672b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach } 6682b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach break; 6691ab3f16f06698596716593a30545799688acccd7Jim Grosbach case ARMII::AddrMode5: 6702b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach // VFP address mode. 6712b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 8; 6722b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach Scale = 4; 6732b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach break; 6743e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARMII::AddrMode_i12: 6751ab3f16f06698596716593a30545799688acccd7Jim Grosbach case ARMII::AddrMode2: 6762b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 12; 6772b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach break; 6781ab3f16f06698596716593a30545799688acccd7Jim Grosbach case ARMII::AddrMode3: 6792b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 8; 6802b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach break; 681e575499d830008784b11499dae290ad0480c8f9dBill Wendling case ARMII::AddrModeT1_s: 6824c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar NumBits = (BaseReg == ARM::SP ? 8 : 5); 68374d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach Scale = 4; 684e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach isSigned = false; 68574d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach break; 6862b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach default: 6872b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach llvm_unreachable("Unsupported addressing mode!"); 6882b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach } 6892b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 6901ab3f16f06698596716593a30545799688acccd7Jim Grosbach Offset += getFrameIndexInstrOffset(MI, i); 691d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach // Make sure the offset is encodable for instructions that scale the 692d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach // immediate. 693d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach if ((Offset & (Scale-1)) != 0) 694d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach return false; 695d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach 696e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach if (isSigned && Offset < 0) 6972b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach Offset = -Offset; 6982b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 6992b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned Mask = (1 << NumBits) - 1; 7002b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach if ((unsigned)Offset <= Mask * Scale) 7012b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach return true; 70274d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach 70374d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach return false; 70474d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach} 70574d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach 706fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbachvoid 7076495f63945e8dbde81f03a1dc2ab421993b9a495Evan ChengARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 708108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier int SPAdj, unsigned FIOperandNum, 709108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier RegScavenger *RS) const { 7105ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MachineInstr &MI = *II; 7115ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MachineBasicBlock &MBB = *MI.getParent(); 7125ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MachineFunction &MF = *MBB.getParent(); 71357148c166ab232191098492633c924fad9c44ef3Bill Wendling const ARMBaseInstrInfo &TII = 71437ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); 715f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const ARMFrameLowering *TFI = getFrameLowering(MF); 7165ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 7176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(!AFI->isThumb1OnlyFunction() && 718a15de00f8246f19180b26ee5fe7ff8f436e0de08Bob Wilson "This eliminateFrameIndex does not support Thumb1!"); 719108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 720a37aa546224ec03ba1f1a1598e0781af4b692673Jim Grosbach unsigned FrameReg; 7215ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 72282f58740c76b42af8370247b23677a0318f6dde8Anton Korobeynikov int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); 7235ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 7240f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the 7250f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // call frame setup/destroy instructions have already been eliminated. That 7260f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // means the stack pointer cannot be used to access the emergency spill slot 7270f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // when !hasReservedCallFrame(). 7280f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen#ifndef NDEBUG 729dc3beb90178fc316f63790812b22201884eaa017Hal Finkel if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){ 7300f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen assert(TFI->hasReservedCallFrame(MF) && 7310f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen "Cannot use SP to access the emergency spill slot in " 7320f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen "functions without a reserved call frame"); 7330f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen assert(!MF.getFrameInfo()->hasVarSizedObjects() && 7340f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen "Cannot use SP to access the emergency spill slot in " 7350f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen "functions with variable sized frame objects"); 7360f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen } 7370f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen#endif // NDEBUG 7380f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen 7396d9dbd5526e3161db884fc4fe99c278bb59ccc19David Blaikie assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code"); 74062b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng 74148d8afab73d72418cf9505a020f621014920463cEvan Cheng // Modify MI as necessary to handle as much of 'Offset' as possible 742cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng bool Done = false; 7436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (!AFI->isThumbFunction()) 744108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 7456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng else { 7466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(AFI->isThumb2Function()); 747108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 7486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 749cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng if (Done) 750fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach return; 7515ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 752db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // If we get here, the immediate doesn't fit into the instruction. We folded 753db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // as much as possible above, handle the rest, providing a register that is 754db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // SP+LargeImm. 75519bb87d0f80f3e6eed38a9fa267bf2b0474aeaabDaniel Dunbar assert((Offset || 756a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || 757a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && 758cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng "This code isn't needed if offset already handled!"); 759db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 7607e831db1d4f5dc51ca6526739cf41e59895c5c20Jim Grosbach unsigned ScratchReg = 0; 761db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin int PIdx = MI.findFirstPredOperandIdx(); 762db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMCC::CondCodes Pred = (PIdx == -1) 763db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 764db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 765cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng if (Offset == 0) 766a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach // Must be addrmode4/6. 767108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false); 7686495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng else { 769420761a0f193e87d08ee1c51b26bba23ab4bac7fCraig Topper ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass); 770cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng if (!AFI->isThumbFunction()) 771cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 772cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset, Pred, PredReg, TII); 773cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng else { 774cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng assert(AFI->isThumb2Function()); 775cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 776cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset, Pred, PredReg, TII); 777cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng } 778cde31293d45f14ddff482d385429d256bd4e0820Jim Grosbach // Update the original instruction to use the scratch register. 779108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true); 7806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 781db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 78237ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines 78337ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hinesbool ARMBaseRegisterInfo::shouldCoalesce(MachineInstr *MI, 78437ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines const TargetRegisterClass *SrcRC, 78537ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines unsigned SubReg, 78637ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines const TargetRegisterClass *DstRC, 78737ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines unsigned DstSubReg, 78837ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines const TargetRegisterClass *NewRC) const { 78937ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines auto MBB = MI->getParent(); 79037ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines auto MF = MBB->getParent(); 79137ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines const MachineRegisterInfo &MRI = MF->getRegInfo(); 79237ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // If not copying into a sub-register this should be ok because we shouldn't 79337ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // need to split the reg. 79437ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines if (!DstSubReg) 79537ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines return true; 79637ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // Small registers don't frequently cause a problem, so we can coalesce them. 79737ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines if (NewRC->getSize() < 32 && DstRC->getSize() < 32 && SrcRC->getSize() < 32) 79837ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines return true; 79937ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines 80037ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines auto NewRCWeight = 80137ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC); 80237ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines auto SrcRCWeight = 80337ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC); 80437ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines auto DstRCWeight = 80537ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC); 80637ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // If the source register class is more expensive than the destination, the 80737ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // coalescing is probably profitable. 80837ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines if (SrcRCWeight.RegWeight > NewRCWeight.RegWeight) 80937ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines return true; 81037ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines if (DstRCWeight.RegWeight > NewRCWeight.RegWeight) 81137ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines return true; 81237ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines 81337ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // If the register allocator isn't constrained, we can always allow coalescing 81437ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // unfortunately we don't know yet if we will be constrained. 81537ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // The goal of this heuristic is to restrict how many expensive registers 81637ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // we allow to coalesce in a given basic block. 81737ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines auto AFI = MF->getInfo<ARMFunctionInfo>(); 81837ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines auto It = AFI->getCoalescedWeight(MBB); 81937ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines 82037ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: " 82137ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines << It->second << "\n"); 82237ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: " 82337ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines << NewRCWeight.RegWeight << "\n"); 82437ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines 82537ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // This number is the largest round number that which meets the criteria: 82637ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // (1) addresses PR18825 82737ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // (2) generates better code in some test cases (like vldm-shed-a9.ll) 82837ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC) 82937ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // In practice the SizeMultiplier will only factor in for straight line code 83037ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // that uses a lot of NEON vectors, which isn't terribly common. 83137ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines unsigned SizeMultiplier = MBB->size()/100; 83237ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1; 83337ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) { 83437ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines It->second += NewRCWeight.RegWeight; 83537ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines return true; 83637ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines } 83737ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines return false; 83837ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines} 839