ARMBaseRegisterInfo.cpp revision 4c5e43da7792f75567b693105cc53e3f1992ad98
131d157ae1ac2cd9c787dc3c1d28e64c682803844Jia Liu//===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===// 2c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 3c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// The LLVM Compiler Infrastructure 4c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 5c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// This file is distributed under the University of Illinois Open Source 6c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// License. See LICENSE.TXT for details. 7c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 8c140c4803dc3e10e08138670829bc0494986abe9David Goodwin//===----------------------------------------------------------------------===// 9c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 10c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// This file contains the base ARM implementation of TargetRegisterInfo class. 11c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 12c140c4803dc3e10e08138670829bc0494986abe9David Goodwin//===----------------------------------------------------------------------===// 13c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 14c1f6f42049696e7357fb4837e1b25dabbaed3fe6Craig Topper#include "ARMBaseRegisterInfo.h" 15c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARM.h" 16db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin#include "ARMBaseInstrInfo.h" 1716c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov#include "ARMFrameLowering.h" 18c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMMachineFunctionInfo.h" 19c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMSubtarget.h" 20ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "MCTargetDesc/ARMAddressingModes.h" 21d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/ADT/BitVector.h" 22d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/ADT/SmallVector.h" 23c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineConstantPool.h" 24c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 25c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineFunction.h" 26c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 27c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineRegisterInfo.h" 28c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/RegisterScavenging.h" 29303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen#include "llvm/CodeGen/VirtRegMap.h" 300b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/Constants.h" 310b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/DerivedTypes.h" 320b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/Function.h" 330b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/LLVMContext.h" 343dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach#include "llvm/Support/Debug.h" 35ab7c09b6b6f4516a631fd6788918c237c83939afTorok Edwin#include "llvm/Support/ErrorHandling.h" 36dac237e18209b697a8ba122d0ddd9cad4dfba1f8Torok Edwin#include "llvm/Support/raw_ostream.h" 3716c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov#include "llvm/Target/TargetFrameLowering.h" 38c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/Target/TargetMachine.h" 39c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/Target/TargetOptions.h" 4073f50d9bc3bd46cc0abeba9bb0d46977ba1aea42Evan Cheng 4137ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines#define DEBUG_TYPE "arm-register-info" 4237ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines 4373f50d9bc3bd46cc0abeba9bb0d46977ba1aea42Evan Cheng#define GET_REGINFO_TARGET_DESC 44a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng#include "ARMGenRegisterInfo.inc" 45c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 461b4886dd00578038c0ca70b3bab97382b89def26Evan Chengusing namespace llvm; 471b4886dd00578038c0ca70b3bab97382b89def26Evan Cheng 484c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga NainarARMBaseRegisterInfo::ARMBaseRegisterInfo() 494c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), BasePtr(ARM::R6) {} 504c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar 514c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainarstatic unsigned getFramePointerReg(const ARMSubtarget &STI) { 52c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines if (STI.isTargetMachO()) { 53c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines if (STI.isTargetDarwin() || STI.isThumb1Only()) 544c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar return ARM::R7; 55c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines else 564c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar return ARM::R11; 57c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines } else if (STI.isTargetWindows()) 584c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar return ARM::R11; 59dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines else // ARM EABI 604c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar return STI.isThumb() ? ARM::R7 : ARM::R11; 61c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 62c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 63dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesconst MCPhysReg* 64c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 654c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>(); 66ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines const MCPhysReg *RegList = 67ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines STI.isTargetDarwin() ? CSR_iOS_SaveList : CSR_AAPCS_SaveList; 68bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover 69bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover const Function *F = MF->getFunction(); 70bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover if (F->getCallingConv() == CallingConv::GHC) { 7162da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin // GHC set of callee saved regs is empty as all those regs are 7262da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin // used for passing STG regs around 7362da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin return CSR_NoRegs_SaveList; 74bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover } else if (F->hasFnAttribute("interrupt")) { 75bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover if (STI.isMClass()) { 76bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover // M-class CPUs have hardware which saves the registers needed to allow a 77bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover // function conforming to the AAPCS to function as a handler. 78bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover return CSR_AAPCS_SaveList; 79bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover } else if (F->getFnAttribute("interrupt").getValueAsString() == "FIQ") { 80bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover // Fast interrupt mode gives the handler a private copy of R8-R14, so less 81bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover // need to be saved to restore user-mode state. 82bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover return CSR_FIQ_SaveList; 83bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover } else { 84bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by 85bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover // exception handling. 86bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover return CSR_GenericInt_SaveList; 87bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover } 88bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover } 89bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover 90bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover return RegList; 913ee7d15284f188672e9e429e9e5cf7b870698677Jakob Stoklund Olesen} 92c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 934c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainarconst uint32_t * 944c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga NainarARMBaseRegisterInfo::getCallPreservedMask(const MachineFunction &MF, 954c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar CallingConv::ID CC) const { 964c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); 9762da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin if (CC == CallingConv::GHC) 9862da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin // This is academic becase all GHC calls are (supposed to be) tail calls 9962da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin return CSR_NoRegs_RegMask; 100ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines return STI.isTargetDarwin() ? CSR_iOS_RegMask : CSR_AAPCS_RegMask; 101c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 102c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 103e7bd51980a1341fb60322e5922cfcc0c9b92b165Chad Rosierconst uint32_t* 104165a7a925d73286abfc826b3d6339843b02c09e0Stephen LinARMBaseRegisterInfo::getNoPreservedMask() const { 105165a7a925d73286abfc826b3d6339843b02c09e0Stephen Lin return CSR_NoRegs_RegMask; 106456ca048af35163b9f52187e92a23ee0a9f059e8Stephen Lin} 107456ca048af35163b9f52187e92a23ee0a9f059e8Stephen Lin 1084c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainarconst uint32_t * 1094c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga NainarARMBaseRegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF, 1104c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar CallingConv::ID CC) const { 1114c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); 112165a7a925d73286abfc826b3d6339843b02c09e0Stephen Lin // This should return a register mask that is the same as that returned by 113165a7a925d73286abfc826b3d6339843b02c09e0Stephen Lin // getCallPreservedMask but that additionally preserves the register used for 114165a7a925d73286abfc826b3d6339843b02c09e0Stephen Lin // the first i32 argument (which must also be the register used to return a 115165a7a925d73286abfc826b3d6339843b02c09e0Stephen Lin // single i32 return value) 116165a7a925d73286abfc826b3d6339843b02c09e0Stephen Lin // 117165a7a925d73286abfc826b3d6339843b02c09e0Stephen Lin // In case that the calling convention does not use the same register for 11862da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin // both or otherwise does not want to enable this optimization, the function 11962da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin // should return NULL 12062da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin if (CC == CallingConv::GHC) 12162da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin // This is academic becase all GHC calls are (supposed to be) tail calls 122dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 123ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines return STI.isTargetDarwin() ? CSR_iOS_ThisReturn_RegMask 124ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines : CSR_AAPCS_ThisReturn_RegMask; 125e7bd51980a1341fb60322e5922cfcc0c9b92b165Chad Rosier} 126e7bd51980a1341fb60322e5922cfcc0c9b92b165Chad Rosier 1279631864688c593711f82bb8d21f8b724c628d786Jim GrosbachBitVector ARMBaseRegisterInfo:: 1289631864688c593711f82bb8d21f8b724c628d786Jim GrosbachgetReservedRegs(const MachineFunction &MF) const { 1294c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); 1304c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar const TargetFrameLowering *TFI = STI.getFrameLowering(); 131d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov 1327a2bdde0a0eebcd2125055e0eacaca040f0b766cChris Lattner // FIXME: avoid re-calculating this every time. 133c140c4803dc3e10e08138670829bc0494986abe9David Goodwin BitVector Reserved(getNumRegs()); 134c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(ARM::SP); 135c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(ARM::PC); 1364f92b5e6163b16d63eb63269c2aec670b55ea19aLang Hames Reserved.set(ARM::FPSCR); 137f86e436fb95670ed110818fefa403f21ae104639Mihai Popa Reserved.set(ARM::APSR_NZCV); 138d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov if (TFI->hasFP(MF)) 1394c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar Reserved.set(getFramePointerReg(STI)); 14065482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach if (hasBasePointer(MF)) 14165482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach Reserved.set(BasePtr); 142c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Some targets reserve R9. 143c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (STI.isR9Reserved()) 144c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(ARM::R9); 1453b6434e360315849a65b1ac85e16d160131a77a4Jakob Stoklund Olesen // Reserve D16-D31 if the subtarget doesn't support them. 1463b6434e360315849a65b1ac85e16d160131a77a4Jakob Stoklund Olesen if (!STI.hasVFP3() || STI.hasD16()) { 1473b6434e360315849a65b1ac85e16d160131a77a4Jakob Stoklund Olesen assert(ARM::D31 == ARM::D16 + 15); 1483b6434e360315849a65b1ac85e16d160131a77a4Jakob Stoklund Olesen for (unsigned i = 0; i != 16; ++i) 1493b6434e360315849a65b1ac85e16d160131a77a4Jakob Stoklund Olesen Reserved.set(ARM::D16 + i); 1503b6434e360315849a65b1ac85e16d160131a77a4Jakob Stoklund Olesen } 151cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen const TargetRegisterClass *RC = &ARM::GPRPairRegClass; 152cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I) 153cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI) 154cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen if (Reserved.test(*SI)) Reserved.set(*I); 155cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen 156c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return Reserved; 157c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 158c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1594c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainarconst TargetRegisterClass * 1604c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga NainarARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, 1614c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar const MachineFunction &) const { 162c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen const TargetRegisterClass *Super = RC; 163c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); 164c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen do { 165c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen switch (Super->getID()) { 166c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::GPRRegClassID: 167c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::SPRRegClassID: 168c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::DPRRegClassID: 169c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::QPRRegClassID: 170c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::QQPRRegClassID: 171c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::QQQQPRRegClassID: 172cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen case ARM::GPRPairRegClassID: 173c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen return Super; 174c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen } 175c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen Super = *I++; 176c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen } while (Super); 177c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen return RC; 178c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen} 179b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng 1804f54c1293af174a8002db20faf7b4f82ba4e8514Evan Chengconst TargetRegisterClass * 181397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund OlesenARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 182397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen const { 183420761a0f193e87d08ee1c51b26bba23ab4bac7fCraig Topper return &ARM::GPRRegClass; 184c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 185be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich 186342e3161d9dd4fa485b47788aa0266f9c91c3832Evan Chengconst TargetRegisterClass * 187342e3161d9dd4fa485b47788aa0266f9c91c3832Evan ChengARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { 188342e3161d9dd4fa485b47788aa0266f9c91c3832Evan Cheng if (RC == &ARM::CCRRegClass) 18937ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines return &ARM::rGPRRegClass; // Can't copy CCR registers. 190342e3161d9dd4fa485b47788aa0266f9c91c3832Evan Cheng return RC; 191342e3161d9dd4fa485b47788aa0266f9c91c3832Evan Cheng} 192342e3161d9dd4fa485b47788aa0266f9c91c3832Evan Cheng 193be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarichunsigned 194be2119e8e2bc7006cfd638a24367acbfda625d16Cameron ZwarichARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 195be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich MachineFunction &MF) const { 1964c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); 1974c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar const TargetFrameLowering *TFI = STI.getFrameLowering(); 198be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich 199be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich switch (RC->getID()) { 200be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich default: 201be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich return 0; 202be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich case ARM::tGPRRegClassID: 203be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich return TFI->hasFP(MF) ? 4 : 5; 204be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich case ARM::GPRRegClassID: { 205be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich unsigned FP = TFI->hasFP(MF) ? 1 : 0; 206be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich return 10 - FP - (STI.isR9Reserved() ? 1 : 0); 207be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich } 208be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich case ARM::SPRRegClassID: // Currently not used as 'rep' register class. 209be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich case ARM::DPRRegClassID: 210be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich return 32 - 10; 211be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich } 212be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich} 213c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 214303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen// Get the other register in a GPRPair. 215303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesenstatic unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) { 216303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers) 217303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen if (ARM::GPRPairRegClass.contains(*Supers)) 218303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0); 219303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen return 0; 220303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen} 221303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen 222303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen// Resolve the RegPairEven / RegPairOdd register allocator hints. 223303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesenvoid 224303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund OlesenARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, 225303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen ArrayRef<MCPhysReg> Order, 226303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen SmallVectorImpl<MCPhysReg> &Hints, 227303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen const MachineFunction &MF, 228303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen const VirtRegMap *VRM) const { 229303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen const MachineRegisterInfo &MRI = MF.getRegInfo(); 230303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 231303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen 232303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen unsigned Odd; 233303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen switch (Hint.first) { 234303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen case ARMRI::RegPairEven: 235303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen Odd = 0; 236303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen break; 237303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen case ARMRI::RegPairOdd: 238303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen Odd = 1; 239303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen break; 240303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen default: 241303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM); 242303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen return; 243303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen } 244303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen 245303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen // This register should preferably be even (Odd == 0) or odd (Odd == 1). 246303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen // Check if the other part of the pair has already been assigned, and provide 247303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen // the paired register as the first hint. 248303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen unsigned PairedPhys = 0; 249303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen if (VRM && VRM->hasPhys(Hint.second)) { 250303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen PairedPhys = getPairedGPR(VRM->getPhys(Hint.second), Odd, this); 251303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen if (PairedPhys && MRI.isReserved(PairedPhys)) 252303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen PairedPhys = 0; 253303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen } 254303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen 255303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen // First prefer the paired physreg. 2564fd4c91c40fa40ae4cd671b03056de8c3c961046Jim Grosbach if (PairedPhys && 2574fd4c91c40fa40ae4cd671b03056de8c3c961046Jim Grosbach std::find(Order.begin(), Order.end(), PairedPhys) != Order.end()) 258303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen Hints.push_back(PairedPhys); 259303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen 260303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen // Then prefer even or odd registers. 261303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen for (unsigned I = 0, E = Order.size(); I != E; ++I) { 262303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen unsigned Reg = Order[I]; 263303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd) 264303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen continue; 265303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen // Don't provide hints that are paired to a reserved register. 266303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen unsigned Paired = getPairedGPR(Reg, !Odd, this); 267303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen if (!Paired || MRI.isReserved(Paired)) 268303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen continue; 269303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen Hints.push_back(Reg); 270303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen } 271303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen} 272303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen 273c140c4803dc3e10e08138670829bc0494986abe9David Goodwinvoid 274ebe69fe11e48d322045d5949c83283927a0d790bStephen HinesARMBaseRegisterInfo::updateRegAllocHint(unsigned Reg, unsigned NewReg, 275c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MachineFunction &MF) const { 276c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MachineRegisterInfo *MRI = &MF.getRegInfo(); 277c140c4803dc3e10e08138670829bc0494986abe9David Goodwin std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 278c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 279c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Hint.first == (unsigned)ARMRI::RegPairEven) && 280c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen TargetRegisterInfo::isVirtualRegister(Hint.second)) { 281c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // If 'Reg' is one of the even / odd register pair and it's now changed 282c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // (e.g. coalesced) into a different register. The other register of the 283c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // pair allocation hint must be updated to reflect the relationship 284c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // change. 285c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned OtherReg = Hint.second; 286c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Hint = MRI->getRegAllocationHint(OtherReg); 287c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (Hint.second == Reg) 288c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Make sure the pair has not already divorced. 289c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 290c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 291c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 292f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson 29365482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbachbool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 2946a8700301ca6f8f2f5f787c8d1f5206a7dfceed6Daniel Dunbar const MachineFrameInfo *MFI = MF.getFrameInfo(); 2951755b3964f931bdd6fa9b4c0138f666ccfa12acaJim Grosbach const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 29637ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); 29765482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach 2980f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // When outgoing call frames are so large that we adjust the stack pointer 2990f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // around the call, we can no longer use the stack pointer to reach the 3000f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // emergency spill slot. 301055a8127c9ffee287807fe7cc1b115d0f40162b0Bob Wilson if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF)) 30265482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach return true; 30365482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach 30465482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited 30565482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // negative range for ldr/str (255), and thumb1 is positive offsets only. 30665482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // It's going to be better to use the SP or Base Pointer instead. When there 30765482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // are variable sized objects, we can't reference off of the SP, so we 30865482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // reserve a Base Pointer. 30965482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) { 31065482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // Conservatively estimate whether the negative offset from the frame 31165482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // pointer will be sufficient to reach. If a function has a smallish 31265482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // frame, it's less likely to have lots of spills and callee saved 31365482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // space, so it's all more likely to be within range of the frame pointer. 31465482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // If it's wrong, the scavenger will still enable access to work, it just 31565482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // won't be optimal. 31665482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128) 31765482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach return false; 31865482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach return true; 31965482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach } 32065482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach 32165482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach return false; 32265482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach} 32365482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach 32465482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbachbool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { 32554f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen const MachineRegisterInfo *MRI = &MF.getRegInfo(); 3266690bca623d1f6405b95db5b1760f7ba8436e3fbChad Rosier const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 32730c93e1cd3e43e174994834900325fcff3322288Jim Grosbach // We can't realign the stack if: 32830c93e1cd3e43e174994834900325fcff3322288Jim Grosbach // 1. Dynamic stack realignment is explicitly disabled, 3296690bca623d1f6405b95db5b1760f7ba8436e3fbChad Rosier // 2. This is a Thumb1 function (it's not useful, so we don't bother), or 3306690bca623d1f6405b95db5b1760f7ba8436e3fbChad Rosier // 3. There are VLAs in the function and the base pointer is disabled. 33161fc8d670f1e991804c2ab753e567981e60962cbBill Wendling if (MF.getFunction()->hasFnAttribute("no-realign-stack")) 33254f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen return false; 33354f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen if (AFI->isThumb1OnlyFunction()) 33454f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen return false; 33554f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen // Stack realignment requires a frame pointer. If we already started 33654f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen // register allocation with frame pointer elimination, it is too late now. 3374c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar if (!MRI->canReserveReg(getFramePointerReg(MF.getSubtarget<ARMSubtarget>()))) 33854f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen return false; 339aaa1e2f820e61a2f4b878d97599b3ca093bc96edBob Wilson // We may also need a base pointer if there are dynamic allocas or stack 340aaa1e2f820e61a2f4b878d97599b3ca093bc96edBob Wilson // pointer adjustments around calls. 341ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines if (MF.getSubtarget().getFrameLowering()->hasReservedCallFrame(MF)) 34254f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen return true; 34354f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen // A base pointer is required and allowed. Check that it isn't too late to 34454f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen // reserve it. 34554f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen return MRI->canReserveReg(BasePtr); 346e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3Jim Grosbach} 347e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3Jim Grosbach 3483dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbachbool ARMBaseRegisterInfo:: 3493dab2778571b5bb00b35a0adcb7011dc85158bebJim GrosbachneedsStackRealignment(const MachineFunction &MF) const { 3503dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach const MachineFrameInfo *MFI = MF.getFrameInfo(); 351d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher const Function *F = MF.getFunction(); 352ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines unsigned StackAlign = 353ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines MF.getSubtarget().getFrameLowering()->getStackAlignment(); 354ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) || 355ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines F->hasFnAttribute(Attribute::StackAlignment)); 3565c33f5bf67f61e3a1addda6de735d28d550dd0ebJim Grosbach 357d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher return requiresRealignment && canRealignStack(MF); 3583dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach} 3593dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach 3609631864688c593711f82bb8d21f8b724c628d786Jim Grosbachbool ARMBaseRegisterInfo:: 3619631864688c593711f82bb8d21f8b724c628d786Jim GrosbachcannotEliminateFrame(const MachineFunction &MF) const { 36298a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng const MachineFrameInfo *MFI = MF.getFrameInfo(); 3638a8d479214745c82ef00f08d4e4f1c173b5f9ce2Nick Lewycky if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack()) 36498a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng return true; 36531bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() 36631bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach || needsStackRealignment(MF); 36798a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng} 36898a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng 3695c33f5bf67f61e3a1addda6de735d28d550dd0ebJim Grosbachunsigned 3703f2bf85d14759cc4b28a86805f566ac805a54d00David GreeneARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 3714c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); 3724c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar const TargetFrameLowering *TFI = STI.getFrameLowering(); 373d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov 374d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov if (TFI->hasFP(MF)) 3754c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar return getFramePointerReg(STI); 376c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::SP; 377c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 378c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 379db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// emitLoadConstPool - Emits a load from constpool to materialize the 380db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// specified immediate. 381db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinvoid ARMBaseRegisterInfo:: 382db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinemitLoadConstPool(MachineBasicBlock &MBB, 383db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock::iterator &MBBI, 38477521f5232e679aa3de10aaaed2464aa91d7ff55David Goodwin DebugLoc dl, 385378445303b10b092a898a75131141a8259cff50bEvan Cheng unsigned DestReg, unsigned SubIdx, int Val, 386db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMCC::CondCodes Pred, 3873daccd82d3151fa3629de430b55698a81084fc9eAnton Korobeynikov unsigned PredReg, unsigned MIFlags) const { 388db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineFunction &MF = *MBB.getParent(); 38937ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 390db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineConstantPool *ConstantPool = MF.getConstantPool(); 39146510a73e977273ec67747eb34cbdb43f815e451Dan Gohman const Constant *C = 3921d0be15f89cb5056e20e2d24faa8d6afb1573bcaOwen Anderson ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); 393db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 394db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 395378445303b10b092a898a75131141a8259cff50bEvan Cheng BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 396378445303b10b092a898a75131141a8259cff50bEvan Cheng .addReg(DestReg, getDefRegState(true), SubIdx) 397db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin .addConstantPoolIndex(Idx) 3983daccd82d3151fa3629de430b55698a81084fc9eAnton Korobeynikov .addImm(0).addImm(Pred).addReg(PredReg) 3993daccd82d3151fa3629de430b55698a81084fc9eAnton Korobeynikov .setMIFlags(MIFlags); 400db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 401db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 402db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinbool ARMBaseRegisterInfo:: 403db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinrequiresRegisterScavenging(const MachineFunction &MF) const { 404db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return true; 405db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 40641fff8c19ab6d8e28f5362481c184ad628f8c704Jim Grosbach 4077e831db1d4f5dc51ca6526739cf41e59895c5c20Jim Grosbachbool ARMBaseRegisterInfo:: 4086a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston GurdtrackLivenessAfterRegAlloc(const MachineFunction &MF) const { 4096a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd return true; 4106a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd} 4116a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd 4126a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurdbool ARMBaseRegisterInfo:: 4137e831db1d4f5dc51ca6526739cf41e59895c5c20Jim GrosbachrequiresFrameIndexScavenging(const MachineFunction &MF) const { 414ca5dfb71ba4aa4a8392a021ec056cf0b70f74f1eJim Grosbach return true; 4157e831db1d4f5dc51ca6526739cf41e59895c5c20Jim Grosbach} 416db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 417a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbachbool ARMBaseRegisterInfo:: 418a273442891ae20fd8192526132e3819ea9e5eda9Jim GrosbachrequiresVirtualBaseRegisters(const MachineFunction &MF) const { 419c8cd8aa9d8582d2632db8fee8b2932efcdec34f1Jim Grosbach return true; 420a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach} 421a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach 422e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbachint64_t ARMBaseRegisterInfo:: 4231ab3f16f06698596716593a30545799688acccd7Jim GrosbachgetFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { 424e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = MI->getDesc(); 425e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 42690f20044ade3712c8b0c3f4ebe47d57ad15ae6ceChad Rosier int64_t InstrOffs = 0; 427e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach int Scale = 1; 428e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach unsigned ImmIdx = 0; 4291ab3f16f06698596716593a30545799688acccd7Jim Grosbach switch (AddrMode) { 430e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrModeT2_i8: 431e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrModeT2_i12: 4323e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARMII::AddrMode_i12: 433e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = MI->getOperand(Idx+1).getImm(); 434e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach Scale = 1; 435e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 436e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrMode5: { 437e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach // VFP address mode. 438e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach const MachineOperand &OffOp = MI->getOperand(Idx+1); 439f78ee6316bc755779920ac207edc27a89c0bd2f9Jim Grosbach InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); 440e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) 441e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = -InstrOffs; 442e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach Scale = 4; 443e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 444e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 445e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrMode2: { 446e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach ImmIdx = Idx+2; 447e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); 448e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 449e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = -InstrOffs; 450e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 451e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 452e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrMode3: { 453e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach ImmIdx = Idx+2; 454e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); 455e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 456e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = -InstrOffs; 457e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 458e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 459e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrModeT1_s: { 460e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach ImmIdx = Idx+1; 461e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = MI->getOperand(ImmIdx).getImm(); 462e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach Scale = 4; 463e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 464e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 465e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach default: 466e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach llvm_unreachable("Unsupported addressing mode!"); 467e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 468e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach 469e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach return InstrOffs * Scale; 470e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach} 471e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach 4728708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// needsFrameBaseReg - Returns true if the instruction's frame index 4738708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// reference would be better served by a base register other than FP 4748708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// or SP. Used by LocalStackFrameAllocation to determine which frame index 4758708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// references it should create new base registers for. 4768708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbachbool ARMBaseRegisterInfo:: 4773197380143cdc18837722129ac888528b9fbfc2bJim GrosbachneedsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 4783197380143cdc18837722129ac888528b9fbfc2bJim Grosbach for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) { 4793197380143cdc18837722129ac888528b9fbfc2bJim Grosbach assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 4803197380143cdc18837722129ac888528b9fbfc2bJim Grosbach } 4818708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 4828708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // It's the load/store FI references that cause issues, as it can be difficult 4838708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // to materialize the offset if it won't fit in the literal field. Estimate 4848708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // based on the size of the local frame and some conservative assumptions 4858708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // about the rest of the stack frame (note, this is pre-regalloc, so 4868708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // we don't know everything for certain yet) whether this offset is likely 4878708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // to be out of range of the immediate. Return true if so. 4888708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 489cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach // We only generate virtual base registers for loads and stores, so 490cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach // return false for everything else. 4918708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach unsigned Opc = MI->getOpcode(); 4928708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach switch (Opc) { 493cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12: 4947e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach case ARM::STRi12: case ARM::STRH: case ARM::STRBi12: 495cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRi12: case ARM::t2LDRi8: 496cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2STRi12: case ARM::t2STRi8: 4978708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach case ARM::VLDRS: case ARM::VLDRD: 4988708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach case ARM::VSTRS: case ARM::VSTRD: 49974d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach case ARM::tSTRspi: case ARM::tLDRspi: 500cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach break; 5018708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach default: 5028708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach return false; 5038708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach } 504cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach 505cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach // Without a virtual base register, if the function has variable sized 506cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach // objects, all fixed-size local references will be via the frame pointer, 5073197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Approximate the offset and see if it's legal for the instruction. 5083197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Note that the incoming offset is based on the SP value at function entry, 5093197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // so it'll be negative. 5103197380143cdc18837722129ac888528b9fbfc2bJim Grosbach MachineFunction &MF = *MI->getParent()->getParent(); 51137ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); 5123197380143cdc18837722129ac888528b9fbfc2bJim Grosbach MachineFrameInfo *MFI = MF.getFrameInfo(); 5133197380143cdc18837722129ac888528b9fbfc2bJim Grosbach ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 5143197380143cdc18837722129ac888528b9fbfc2bJim Grosbach 5153197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Estimate an offset from the frame pointer. 5163197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Conservatively assume all callee-saved registers get pushed. R4-R6 5173197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // will be earlier than the FP, so we ignore those. 5183197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // R7, LR 5193197380143cdc18837722129ac888528b9fbfc2bJim Grosbach int64_t FPOffset = Offset - 8; 5203197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15 5213197380143cdc18837722129ac888528b9fbfc2bJim Grosbach if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction()) 5223197380143cdc18837722129ac888528b9fbfc2bJim Grosbach FPOffset -= 80; 5233197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Estimate an offset from the stack pointer. 524c1dc78de762e8a65fe1edd0cced13d94ab5a971fJim Grosbach // The incoming offset is relating to the SP at the start of the function, 525c1dc78de762e8a65fe1edd0cced13d94ab5a971fJim Grosbach // but when we access the local it'll be relative to the SP after local 526c1dc78de762e8a65fe1edd0cced13d94ab5a971fJim Grosbach // allocation, so adjust our SP-relative offset by that allocation size. 527c1dc78de762e8a65fe1edd0cced13d94ab5a971fJim Grosbach Offset += MFI->getLocalFrameSize(); 5283197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Assume that we'll have at least some spill slots allocated. 5293197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // FIXME: This is a total SWAG number. We should run some statistics 5303197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // and pick a real one. 5313197380143cdc18837722129ac888528b9fbfc2bJim Grosbach Offset += 128; // 128 bytes of spill slots 5323197380143cdc18837722129ac888528b9fbfc2bJim Grosbach 533ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // If there's a frame pointer and the addressing mode allows it, try using it. 5343197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // The FP is only available if there is no dynamic realignment. We 5353197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // don't know for sure yet whether we'll need that, so we guess based 5363197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // on whether there are any local variables that would trigger it. 53716c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov unsigned StackAlign = TFI->getStackAlignment(); 538ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines if (TFI->hasFP(MF) && 5393197380143cdc18837722129ac888528b9fbfc2bJim Grosbach !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) { 5404c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar if (isFrameOffsetLegal(MI, getFrameRegister(MF), FPOffset)) 5413197380143cdc18837722129ac888528b9fbfc2bJim Grosbach return false; 5423197380143cdc18837722129ac888528b9fbfc2bJim Grosbach } 5433197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // If we can reference via the stack pointer, try that. 5443197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // FIXME: This (and the code that resolves the references) can be improved 5453197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // to only disallow SP relative references in the live range of 5463197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // the VLA(s). In practice, it's unclear how much difference that 5473197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // would make, but it may be worth doing. 5484c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, ARM::SP, Offset)) 5493197380143cdc18837722129ac888528b9fbfc2bJim Grosbach return false; 550cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach 5513197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // The offset likely isn't legal, we want to allocate a virtual base register. 552cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach return true; 5538708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach} 5548708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 555976ef86689ed065361a748f81c44ca3510af2202Bill Wendling/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to 556976ef86689ed065361a748f81c44ca3510af2202Bill Wendling/// be a pointer to FrameIdx at the beginning of the basic block. 557dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbachvoid ARMBaseRegisterInfo:: 558976ef86689ed065361a748f81c44ca3510af2202Bill WendlingmaterializeFrameBaseRegister(MachineBasicBlock *MBB, 559976ef86689ed065361a748f81c44ca3510af2202Bill Wendling unsigned BaseReg, int FrameIdx, 560976ef86689ed065361a748f81c44ca3510af2202Bill Wendling int64_t Offset) const { 561976ef86689ed065361a748f81c44ca3510af2202Bill Wendling ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>(); 56274d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : 56337ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines (AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri); 564dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 565976ef86689ed065361a748f81c44ca3510af2202Bill Wendling MachineBasicBlock::iterator Ins = MBB->begin(); 566976ef86689ed065361a748f81c44ca3510af2202Bill Wendling DebugLoc DL; // Defaults to "unknown" 567976ef86689ed065361a748f81c44ca3510af2202Bill Wendling if (Ins != MBB->end()) 568976ef86689ed065361a748f81c44ca3510af2202Bill Wendling DL = Ins->getDebugLoc(); 569976ef86689ed065361a748f81c44ca3510af2202Bill Wendling 570397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen const MachineFunction &MF = *MBB->getParent(); 57157148c166ab232191098492633c924fad9c44ef3Bill Wendling MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 57237ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 57357148c166ab232191098492633c924fad9c44ef3Bill Wendling const MCInstrDesc &MCID = TII.get(ADDriOpc); 574397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 57521803721d538255e4d223c29b6c8d3c9e93d4d86Cameron Zwarich 57637ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg) 57737ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines .addFrameIndex(FrameIdx).addImm(Offset); 578976ef86689ed065361a748f81c44ca3510af2202Bill Wendling 57974d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach if (!AFI->isThumb1OnlyFunction()) 58037ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines AddDefaultCC(AddDefaultPred(MIB)); 581dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach} 582dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 58336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hinesvoid ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 58436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines int64_t Offset) const { 585dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach MachineBasicBlock &MBB = *MI.getParent(); 586dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach MachineFunction &MF = *MBB.getParent(); 58757148c166ab232191098492633c924fad9c44ef3Bill Wendling const ARMBaseInstrInfo &TII = 58837ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); 589dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 590dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach int Off = Offset; // ARM doesn't need the general 64-bit offsets 591dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach unsigned i = 0; 592dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 593dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach assert(!AFI->isThumb1OnlyFunction() && 594dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach "This resolveFrameIndex does not support Thumb1!"); 595dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 596dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach while (!MI.getOperand(i).isFI()) { 597dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach ++i; 598dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 599dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach } 600dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach bool Done = false; 601dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach if (!AFI->isThumbFunction()) 602dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); 603dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach else { 604dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach assert(AFI->isThumb2Function()); 605dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII); 606dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach } 607dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach assert (Done && "Unable to resolve frame index!"); 6081f6a329f79b3568d379142f921f59c4143ddaa14Duncan Sands (void)Done; 609dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach} 6108708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 6114c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainarbool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, 612e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach int64_t Offset) const { 613e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = MI->getDesc(); 6142b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 6152b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned i = 0; 6162b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 6172b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach while (!MI->getOperand(i).isFI()) { 6182b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach ++i; 6192b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 6202b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach } 6212b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 6222b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach // AddrMode4 and AddrMode6 cannot handle any offset. 6232b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) 6242b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach return Offset == 0; 6252b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 6262b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned NumBits = 0; 6272b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned Scale = 1; 628e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach bool isSigned = true; 6291ab3f16f06698596716593a30545799688acccd7Jim Grosbach switch (AddrMode) { 6302b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach case ARMII::AddrModeT2_i8: 6312b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach case ARMII::AddrModeT2_i12: 6322b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach // i8 supports only negative, and i12 supports only positive, so 6332b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach // based on Offset sign, consider the appropriate instruction 63474d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach Scale = 1; 6352b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach if (Offset < 0) { 6362b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 8; 6372b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach Offset = -Offset; 6382b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach } else { 6392b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 12; 6402b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach } 6412b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach break; 6421ab3f16f06698596716593a30545799688acccd7Jim Grosbach case ARMII::AddrMode5: 6432b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach // VFP address mode. 6442b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 8; 6452b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach Scale = 4; 6462b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach break; 6473e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARMII::AddrMode_i12: 6481ab3f16f06698596716593a30545799688acccd7Jim Grosbach case ARMII::AddrMode2: 6492b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 12; 6502b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach break; 6511ab3f16f06698596716593a30545799688acccd7Jim Grosbach case ARMII::AddrMode3: 6522b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 8; 6532b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach break; 654e575499d830008784b11499dae290ad0480c8f9dBill Wendling case ARMII::AddrModeT1_s: 6554c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar NumBits = (BaseReg == ARM::SP ? 8 : 5); 65674d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach Scale = 4; 657e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach isSigned = false; 65874d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach break; 6592b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach default: 6602b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach llvm_unreachable("Unsupported addressing mode!"); 6612b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach } 6622b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 6631ab3f16f06698596716593a30545799688acccd7Jim Grosbach Offset += getFrameIndexInstrOffset(MI, i); 664d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach // Make sure the offset is encodable for instructions that scale the 665d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach // immediate. 666d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach if ((Offset & (Scale-1)) != 0) 667d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach return false; 668d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach 669e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach if (isSigned && Offset < 0) 6702b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach Offset = -Offset; 6712b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 6722b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned Mask = (1 << NumBits) - 1; 6732b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach if ((unsigned)Offset <= Mask * Scale) 6742b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach return true; 67574d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach 67674d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach return false; 67774d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach} 67874d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach 679fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbachvoid 6806495f63945e8dbde81f03a1dc2ab421993b9a495Evan ChengARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 681108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier int SPAdj, unsigned FIOperandNum, 682108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier RegScavenger *RS) const { 6835ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MachineInstr &MI = *II; 6845ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MachineBasicBlock &MBB = *MI.getParent(); 6855ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MachineFunction &MF = *MBB.getParent(); 68657148c166ab232191098492633c924fad9c44ef3Bill Wendling const ARMBaseInstrInfo &TII = 68737ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); 68837ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines const ARMFrameLowering *TFI = static_cast<const ARMFrameLowering *>( 68937ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines MF.getSubtarget().getFrameLowering()); 6905ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 6916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(!AFI->isThumb1OnlyFunction() && 692a15de00f8246f19180b26ee5fe7ff8f436e0de08Bob Wilson "This eliminateFrameIndex does not support Thumb1!"); 693108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 694a37aa546224ec03ba1f1a1598e0781af4b692673Jim Grosbach unsigned FrameReg; 6955ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 69682f58740c76b42af8370247b23677a0318f6dde8Anton Korobeynikov int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); 6975ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 6980f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the 6990f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // call frame setup/destroy instructions have already been eliminated. That 7000f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // means the stack pointer cannot be used to access the emergency spill slot 7010f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // when !hasReservedCallFrame(). 7020f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen#ifndef NDEBUG 703dc3beb90178fc316f63790812b22201884eaa017Hal Finkel if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){ 7040f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen assert(TFI->hasReservedCallFrame(MF) && 7050f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen "Cannot use SP to access the emergency spill slot in " 7060f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen "functions without a reserved call frame"); 7070f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen assert(!MF.getFrameInfo()->hasVarSizedObjects() && 7080f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen "Cannot use SP to access the emergency spill slot in " 7090f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen "functions with variable sized frame objects"); 7100f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen } 7110f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen#endif // NDEBUG 7120f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen 7136d9dbd5526e3161db884fc4fe99c278bb59ccc19David Blaikie assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code"); 71462b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng 71548d8afab73d72418cf9505a020f621014920463cEvan Cheng // Modify MI as necessary to handle as much of 'Offset' as possible 716cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng bool Done = false; 7176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (!AFI->isThumbFunction()) 718108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 7196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng else { 7206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(AFI->isThumb2Function()); 721108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 7226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 723cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng if (Done) 724fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach return; 7255ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 726db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // If we get here, the immediate doesn't fit into the instruction. We folded 727db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // as much as possible above, handle the rest, providing a register that is 728db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // SP+LargeImm. 72919bb87d0f80f3e6eed38a9fa267bf2b0474aeaabDaniel Dunbar assert((Offset || 730a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || 731a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && 732cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng "This code isn't needed if offset already handled!"); 733db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 7347e831db1d4f5dc51ca6526739cf41e59895c5c20Jim Grosbach unsigned ScratchReg = 0; 735db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin int PIdx = MI.findFirstPredOperandIdx(); 736db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMCC::CondCodes Pred = (PIdx == -1) 737db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 738db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 739cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng if (Offset == 0) 740a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach // Must be addrmode4/6. 741108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false); 7426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng else { 743420761a0f193e87d08ee1c51b26bba23ab4bac7fCraig Topper ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass); 744cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng if (!AFI->isThumbFunction()) 745cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 746cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset, Pred, PredReg, TII); 747cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng else { 748cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng assert(AFI->isThumb2Function()); 749cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 750cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset, Pred, PredReg, TII); 751cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng } 752cde31293d45f14ddff482d385429d256bd4e0820Jim Grosbach // Update the original instruction to use the scratch register. 753108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true); 7546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 755db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 75637ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines 75737ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hinesbool ARMBaseRegisterInfo::shouldCoalesce(MachineInstr *MI, 75837ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines const TargetRegisterClass *SrcRC, 75937ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines unsigned SubReg, 76037ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines const TargetRegisterClass *DstRC, 76137ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines unsigned DstSubReg, 76237ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines const TargetRegisterClass *NewRC) const { 76337ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines auto MBB = MI->getParent(); 76437ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines auto MF = MBB->getParent(); 76537ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines const MachineRegisterInfo &MRI = MF->getRegInfo(); 76637ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // If not copying into a sub-register this should be ok because we shouldn't 76737ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // need to split the reg. 76837ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines if (!DstSubReg) 76937ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines return true; 77037ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // Small registers don't frequently cause a problem, so we can coalesce them. 77137ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines if (NewRC->getSize() < 32 && DstRC->getSize() < 32 && SrcRC->getSize() < 32) 77237ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines return true; 77337ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines 77437ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines auto NewRCWeight = 77537ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC); 77637ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines auto SrcRCWeight = 77737ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC); 77837ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines auto DstRCWeight = 77937ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC); 78037ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // If the source register class is more expensive than the destination, the 78137ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // coalescing is probably profitable. 78237ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines if (SrcRCWeight.RegWeight > NewRCWeight.RegWeight) 78337ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines return true; 78437ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines if (DstRCWeight.RegWeight > NewRCWeight.RegWeight) 78537ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines return true; 78637ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines 78737ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // If the register allocator isn't constrained, we can always allow coalescing 78837ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // unfortunately we don't know yet if we will be constrained. 78937ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // The goal of this heuristic is to restrict how many expensive registers 79037ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // we allow to coalesce in a given basic block. 79137ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines auto AFI = MF->getInfo<ARMFunctionInfo>(); 79237ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines auto It = AFI->getCoalescedWeight(MBB); 79337ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines 79437ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: " 79537ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines << It->second << "\n"); 79637ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: " 79737ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines << NewRCWeight.RegWeight << "\n"); 79837ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines 79937ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // This number is the largest round number that which meets the criteria: 80037ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // (1) addresses PR18825 80137ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // (2) generates better code in some test cases (like vldm-shed-a9.ll) 80237ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC) 80337ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // In practice the SizeMultiplier will only factor in for straight line code 80437ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // that uses a lot of NEON vectors, which isn't terribly common. 80537ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines unsigned SizeMultiplier = MBB->size()/100; 80637ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1; 80737ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) { 80837ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines It->second += NewRCWeight.RegWeight; 80937ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines return true; 81037ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines } 81137ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines return false; 81237ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines} 813