ARMBaseRegisterInfo.cpp revision 62da588a2eb70166e1b6cc332d8084f03117dc12
131d157ae1ac2cd9c787dc3c1d28e64c682803844Jia Liu//===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===// 2c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 3c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// The LLVM Compiler Infrastructure 4c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 5c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// This file is distributed under the University of Illinois Open Source 6c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// License. See LICENSE.TXT for details. 7c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 8c140c4803dc3e10e08138670829bc0494986abe9David Goodwin//===----------------------------------------------------------------------===// 9c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 10c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// This file contains the base ARM implementation of TargetRegisterInfo class. 11c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 12c140c4803dc3e10e08138670829bc0494986abe9David Goodwin//===----------------------------------------------------------------------===// 13c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 14c1f6f42049696e7357fb4837e1b25dabbaed3fe6Craig Topper#include "ARMBaseRegisterInfo.h" 15c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARM.h" 16db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin#include "ARMBaseInstrInfo.h" 1716c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov#include "ARMFrameLowering.h" 18c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMMachineFunctionInfo.h" 19c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMSubtarget.h" 20ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "MCTargetDesc/ARMAddressingModes.h" 21d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/ADT/BitVector.h" 22d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/ADT/SmallVector.h" 23c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineConstantPool.h" 24c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 25c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineFunction.h" 26c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 27c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineRegisterInfo.h" 28c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/RegisterScavenging.h" 29303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen#include "llvm/CodeGen/VirtRegMap.h" 300b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/Constants.h" 310b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/DerivedTypes.h" 320b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/Function.h" 330b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/LLVMContext.h" 343dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach#include "llvm/Support/Debug.h" 35ab7c09b6b6f4516a631fd6788918c237c83939afTorok Edwin#include "llvm/Support/ErrorHandling.h" 36dac237e18209b697a8ba122d0ddd9cad4dfba1f8Torok Edwin#include "llvm/Support/raw_ostream.h" 3716c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov#include "llvm/Target/TargetFrameLowering.h" 38c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/Target/TargetMachine.h" 39c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/Target/TargetOptions.h" 4073f50d9bc3bd46cc0abeba9bb0d46977ba1aea42Evan Cheng 4173f50d9bc3bd46cc0abeba9bb0d46977ba1aea42Evan Cheng#define GET_REGINFO_TARGET_DESC 42a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng#include "ARMGenRegisterInfo.inc" 43c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 441b4886dd00578038c0ca70b3bab97382b89def26Evan Chengusing namespace llvm; 451b4886dd00578038c0ca70b3bab97382b89def26Evan Cheng 4657148c166ab232191098492633c924fad9c44ef3Bill WendlingARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMSubtarget &sti) 4757148c166ab232191098492633c924fad9c44ef3Bill Wendling : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), STI(sti), 4865482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), 4965482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach BasePtr(ARM::R6) { 50c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 51c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 52015f228861ef9b337366f92f637d4e8d624bb006Craig Topperconst uint16_t* 53c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 54e94ac8871a1ac79bece57335d2abece0feed9c02Eric Christopher bool ghcCall = false; 55e94ac8871a1ac79bece57335d2abece0feed9c02Eric Christopher 56e94ac8871a1ac79bece57335d2abece0feed9c02Eric Christopher if (MF) { 57e94ac8871a1ac79bece57335d2abece0feed9c02Eric Christopher const Function *F = MF->getFunction(); 58e94ac8871a1ac79bece57335d2abece0feed9c02Eric Christopher ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false); 59e94ac8871a1ac79bece57335d2abece0feed9c02Eric Christopher } 60e94ac8871a1ac79bece57335d2abece0feed9c02Eric Christopher 618b9962d514c1834c17254e53b169bf618079562cStephen Lin if (ghcCall) 6262da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin // GHC set of callee saved regs is empty as all those regs are 6362da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin // used for passing STG regs around 6462da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin return CSR_NoRegs_SaveList; 658b9962d514c1834c17254e53b169bf618079562cStephen Lin else 668b9962d514c1834c17254e53b169bf618079562cStephen Lin return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 678b9962d514c1834c17254e53b169bf618079562cStephen Lin ? CSR_iOS_SaveList : CSR_AAPCS_SaveList; 683ee7d15284f188672e9e429e9e5cf7b870698677Jakob Stoklund Olesen} 69c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 703ee7d15284f188672e9e429e9e5cf7b870698677Jakob Stoklund Olesenconst uint32_t* 7162da588a2eb70166e1b6cc332d8084f03117dc12Stephen LinARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { 7262da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin if (CC == CallingConv::GHC) 7362da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin // This is academic becase all GHC calls are (supposed to be) tail calls 7462da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin return CSR_NoRegs_RegMask; 75afb3b5ebe61b480527de86311d2a0770fc857d38Evan Cheng return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 76afb3b5ebe61b480527de86311d2a0770fc857d38Evan Cheng ? CSR_iOS_RegMask : CSR_AAPCS_RegMask; 77c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 78c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 79e7bd51980a1341fb60322e5922cfcc0c9b92b165Chad Rosierconst uint32_t* 80165a7a925d73286abfc826b3d6339843b02c09e0Stephen LinARMBaseRegisterInfo::getNoPreservedMask() const { 81165a7a925d73286abfc826b3d6339843b02c09e0Stephen Lin return CSR_NoRegs_RegMask; 82456ca048af35163b9f52187e92a23ee0a9f059e8Stephen Lin} 83456ca048af35163b9f52187e92a23ee0a9f059e8Stephen Lin 84456ca048af35163b9f52187e92a23ee0a9f059e8Stephen Linconst uint32_t* 8562da588a2eb70166e1b6cc332d8084f03117dc12Stephen LinARMBaseRegisterInfo::getThisReturnPreservedMask(CallingConv::ID CC) const { 86165a7a925d73286abfc826b3d6339843b02c09e0Stephen Lin // This should return a register mask that is the same as that returned by 87165a7a925d73286abfc826b3d6339843b02c09e0Stephen Lin // getCallPreservedMask but that additionally preserves the register used for 88165a7a925d73286abfc826b3d6339843b02c09e0Stephen Lin // the first i32 argument (which must also be the register used to return a 89165a7a925d73286abfc826b3d6339843b02c09e0Stephen Lin // single i32 return value) 90165a7a925d73286abfc826b3d6339843b02c09e0Stephen Lin // 91165a7a925d73286abfc826b3d6339843b02c09e0Stephen Lin // In case that the calling convention does not use the same register for 9262da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin // both or otherwise does not want to enable this optimization, the function 9362da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin // should return NULL 9462da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin if (CC == CallingConv::GHC) 9562da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin // This is academic becase all GHC calls are (supposed to be) tail calls 9662da588a2eb70166e1b6cc332d8084f03117dc12Stephen Lin return NULL; 97165a7a925d73286abfc826b3d6339843b02c09e0Stephen Lin return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 98165a7a925d73286abfc826b3d6339843b02c09e0Stephen Lin ? CSR_iOS_ThisReturn_RegMask : CSR_AAPCS_ThisReturn_RegMask; 99e7bd51980a1341fb60322e5922cfcc0c9b92b165Chad Rosier} 100e7bd51980a1341fb60322e5922cfcc0c9b92b165Chad Rosier 1019631864688c593711f82bb8d21f8b724c628d786Jim GrosbachBitVector ARMBaseRegisterInfo:: 1029631864688c593711f82bb8d21f8b724c628d786Jim GrosbachgetReservedRegs(const MachineFunction &MF) const { 10316c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 104d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov 1057a2bdde0a0eebcd2125055e0eacaca040f0b766cChris Lattner // FIXME: avoid re-calculating this every time. 106c140c4803dc3e10e08138670829bc0494986abe9David Goodwin BitVector Reserved(getNumRegs()); 107c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(ARM::SP); 108c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(ARM::PC); 1094f92b5e6163b16d63eb63269c2aec670b55ea19aLang Hames Reserved.set(ARM::FPSCR); 110f86e436fb95670ed110818fefa403f21ae104639Mihai Popa Reserved.set(ARM::APSR_NZCV); 111d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov if (TFI->hasFP(MF)) 112c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(FramePtr); 11365482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach if (hasBasePointer(MF)) 11465482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach Reserved.set(BasePtr); 115c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Some targets reserve R9. 116c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (STI.isR9Reserved()) 117c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(ARM::R9); 1183b6434e360315849a65b1ac85e16d160131a77a4Jakob Stoklund Olesen // Reserve D16-D31 if the subtarget doesn't support them. 1193b6434e360315849a65b1ac85e16d160131a77a4Jakob Stoklund Olesen if (!STI.hasVFP3() || STI.hasD16()) { 1203b6434e360315849a65b1ac85e16d160131a77a4Jakob Stoklund Olesen assert(ARM::D31 == ARM::D16 + 15); 1213b6434e360315849a65b1ac85e16d160131a77a4Jakob Stoklund Olesen for (unsigned i = 0; i != 16; ++i) 1223b6434e360315849a65b1ac85e16d160131a77a4Jakob Stoklund Olesen Reserved.set(ARM::D16 + i); 1233b6434e360315849a65b1ac85e16d160131a77a4Jakob Stoklund Olesen } 124cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen const TargetRegisterClass *RC = &ARM::GPRPairRegClass; 125cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I) 126cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI) 127cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen if (Reserved.test(*SI)) Reserved.set(*I); 128cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen 129c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return Reserved; 130c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 131c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 132c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesenconst TargetRegisterClass* 133c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund OlesenARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) 134c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen const { 135c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen const TargetRegisterClass *Super = RC; 136c8e2bb68bbc4a71cc10084c8f89565b9f05e12efJakob Stoklund Olesen TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); 137c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen do { 138c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen switch (Super->getID()) { 139c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::GPRRegClassID: 140c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::SPRRegClassID: 141c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::DPRRegClassID: 142c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::QPRRegClassID: 143c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::QQPRRegClassID: 144c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::QQQQPRRegClassID: 145cd275f5687799e63956beabe35fc1718dc022f70Jakob Stoklund Olesen case ARM::GPRPairRegClassID: 146c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen return Super; 147c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen } 148c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen Super = *I++; 149c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen } while (Super); 150c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen return RC; 151c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen} 152b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng 1534f54c1293af174a8002db20faf7b4f82ba4e8514Evan Chengconst TargetRegisterClass * 154397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund OlesenARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 155397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen const { 156420761a0f193e87d08ee1c51b26bba23ab4bac7fCraig Topper return &ARM::GPRRegClass; 157c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 158be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich 159342e3161d9dd4fa485b47788aa0266f9c91c3832Evan Chengconst TargetRegisterClass * 160342e3161d9dd4fa485b47788aa0266f9c91c3832Evan ChengARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { 161342e3161d9dd4fa485b47788aa0266f9c91c3832Evan Cheng if (RC == &ARM::CCRRegClass) 162342e3161d9dd4fa485b47788aa0266f9c91c3832Evan Cheng return 0; // Can't copy CCR registers. 163342e3161d9dd4fa485b47788aa0266f9c91c3832Evan Cheng return RC; 164342e3161d9dd4fa485b47788aa0266f9c91c3832Evan Cheng} 165342e3161d9dd4fa485b47788aa0266f9c91c3832Evan Cheng 166be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarichunsigned 167be2119e8e2bc7006cfd638a24367acbfda625d16Cameron ZwarichARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 168be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich MachineFunction &MF) const { 169be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 170be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich 171be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich switch (RC->getID()) { 172be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich default: 173be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich return 0; 174be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich case ARM::tGPRRegClassID: 175be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich return TFI->hasFP(MF) ? 4 : 5; 176be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich case ARM::GPRRegClassID: { 177be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich unsigned FP = TFI->hasFP(MF) ? 1 : 0; 178be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich return 10 - FP - (STI.isR9Reserved() ? 1 : 0); 179be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich } 180be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich case ARM::SPRRegClassID: // Currently not used as 'rep' register class. 181be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich case ARM::DPRRegClassID: 182be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich return 32 - 10; 183be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich } 184be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich} 185c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 186303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen// Get the other register in a GPRPair. 187303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesenstatic unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) { 188303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers) 189303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen if (ARM::GPRPairRegClass.contains(*Supers)) 190303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0); 191303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen return 0; 192303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen} 193303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen 194303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen// Resolve the RegPairEven / RegPairOdd register allocator hints. 195303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesenvoid 196303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund OlesenARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, 197303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen ArrayRef<MCPhysReg> Order, 198303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen SmallVectorImpl<MCPhysReg> &Hints, 199303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen const MachineFunction &MF, 200303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen const VirtRegMap *VRM) const { 201303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen const MachineRegisterInfo &MRI = MF.getRegInfo(); 202303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 203303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen 204303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen unsigned Odd; 205303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen switch (Hint.first) { 206303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen case ARMRI::RegPairEven: 207303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen Odd = 0; 208303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen break; 209303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen case ARMRI::RegPairOdd: 210303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen Odd = 1; 211303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen break; 212303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen default: 213303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM); 214303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen return; 215303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen } 216303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen 217303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen // This register should preferably be even (Odd == 0) or odd (Odd == 1). 218303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen // Check if the other part of the pair has already been assigned, and provide 219303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen // the paired register as the first hint. 220303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen unsigned PairedPhys = 0; 221303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen if (VRM && VRM->hasPhys(Hint.second)) { 222303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen PairedPhys = getPairedGPR(VRM->getPhys(Hint.second), Odd, this); 223303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen if (PairedPhys && MRI.isReserved(PairedPhys)) 224303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen PairedPhys = 0; 225303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen } 226303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen 227303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen // First prefer the paired physreg. 2284fd4c91c40fa40ae4cd671b03056de8c3c961046Jim Grosbach if (PairedPhys && 2294fd4c91c40fa40ae4cd671b03056de8c3c961046Jim Grosbach std::find(Order.begin(), Order.end(), PairedPhys) != Order.end()) 230303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen Hints.push_back(PairedPhys); 231303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen 232303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen // Then prefer even or odd registers. 233303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen for (unsigned I = 0, E = Order.size(); I != E; ++I) { 234303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen unsigned Reg = Order[I]; 235303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd) 236303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen continue; 237303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen // Don't provide hints that are paired to a reserved register. 238303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen unsigned Paired = getPairedGPR(Reg, !Odd, this); 239303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen if (!Paired || MRI.isReserved(Paired)) 240303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen continue; 241303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen Hints.push_back(Reg); 242303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen } 243303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen} 244303da1baf2a90d18a709f29f4f7cd0e1962be5f9Jakob Stoklund Olesen 245c140c4803dc3e10e08138670829bc0494986abe9David Goodwinvoid 246c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 247c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MachineFunction &MF) const { 248c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MachineRegisterInfo *MRI = &MF.getRegInfo(); 249c140c4803dc3e10e08138670829bc0494986abe9David Goodwin std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 250c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 251c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Hint.first == (unsigned)ARMRI::RegPairEven) && 252c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen TargetRegisterInfo::isVirtualRegister(Hint.second)) { 253c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // If 'Reg' is one of the even / odd register pair and it's now changed 254c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // (e.g. coalesced) into a different register. The other register of the 255c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // pair allocation hint must be updated to reflect the relationship 256c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // change. 257c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned OtherReg = Hint.second; 258c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Hint = MRI->getRegAllocationHint(OtherReg); 259c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (Hint.second == Reg) 260c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Make sure the pair has not already divorced. 261c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 262c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 263c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 264f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson 265f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilsonbool 266f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob WilsonARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 267f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson // CortexA9 has a Write-after-write hazard for NEON registers. 268616471d4bfe4717fa86259ff4534703357b3b723Silviu Baranga if (!STI.isLikeA9()) 269f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson return false; 270f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson 271f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson switch (RC->getID()) { 272f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson case ARM::DPRRegClassID: 273f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson case ARM::DPR_8RegClassID: 274f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson case ARM::DPR_VFP2RegClassID: 275f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson case ARM::QPRRegClassID: 276f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson case ARM::QPR_8RegClassID: 277f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson case ARM::QPR_VFP2RegClassID: 278f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson case ARM::SPRRegClassID: 279f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson case ARM::SPR_8RegClassID: 280f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson // Avoid reusing S, D, and Q registers. 281f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson // Don't increase register pressure for QQ and QQQQ. 282f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson return true; 283f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson default: 284f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson return false; 285f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson } 286f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson} 287c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 28865482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbachbool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 2896a8700301ca6f8f2f5f787c8d1f5206a7dfceed6Daniel Dunbar const MachineFrameInfo *MFI = MF.getFrameInfo(); 2901755b3964f931bdd6fa9b4c0138f666ccfa12acaJim Grosbach const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2910f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 29265482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach 2930f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // When outgoing call frames are so large that we adjust the stack pointer 2940f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // around the call, we can no longer use the stack pointer to reach the 2950f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // emergency spill slot. 296055a8127c9ffee287807fe7cc1b115d0f40162b0Bob Wilson if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF)) 29765482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach return true; 29865482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach 29965482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited 30065482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // negative range for ldr/str (255), and thumb1 is positive offsets only. 30165482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // It's going to be better to use the SP or Base Pointer instead. When there 30265482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // are variable sized objects, we can't reference off of the SP, so we 30365482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // reserve a Base Pointer. 30465482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) { 30565482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // Conservatively estimate whether the negative offset from the frame 30665482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // pointer will be sufficient to reach. If a function has a smallish 30765482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // frame, it's less likely to have lots of spills and callee saved 30865482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // space, so it's all more likely to be within range of the frame pointer. 30965482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // If it's wrong, the scavenger will still enable access to work, it just 31065482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // won't be optimal. 31165482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128) 31265482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach return false; 31365482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach return true; 31465482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach } 31565482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach 31665482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach return false; 31765482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach} 31865482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach 31965482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbachbool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { 32054f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen const MachineRegisterInfo *MRI = &MF.getRegInfo(); 3216690bca623d1f6405b95db5b1760f7ba8436e3fbChad Rosier const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 32230c93e1cd3e43e174994834900325fcff3322288Jim Grosbach // We can't realign the stack if: 32330c93e1cd3e43e174994834900325fcff3322288Jim Grosbach // 1. Dynamic stack realignment is explicitly disabled, 3246690bca623d1f6405b95db5b1760f7ba8436e3fbChad Rosier // 2. This is a Thumb1 function (it's not useful, so we don't bother), or 3256690bca623d1f6405b95db5b1760f7ba8436e3fbChad Rosier // 3. There are VLAs in the function and the base pointer is disabled. 32654f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen if (!MF.getTarget().Options.RealignStack) 32754f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen return false; 32854f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen if (AFI->isThumb1OnlyFunction()) 32954f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen return false; 33054f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen // Stack realignment requires a frame pointer. If we already started 33154f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen // register allocation with frame pointer elimination, it is too late now. 33254f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen if (!MRI->canReserveReg(FramePtr)) 33354f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen return false; 334aaa1e2f820e61a2f4b878d97599b3ca093bc96edBob Wilson // We may also need a base pointer if there are dynamic allocas or stack 335aaa1e2f820e61a2f4b878d97599b3ca093bc96edBob Wilson // pointer adjustments around calls. 336aaa1e2f820e61a2f4b878d97599b3ca093bc96edBob Wilson if (MF.getTarget().getFrameLowering()->hasReservedCallFrame(MF)) 33754f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen return true; 33854f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen // A base pointer is required and allowed. Check that it isn't too late to 33954f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen // reserve it. 34054f3b7a9109d1916cf25ffdb2ed5045f03121b5aJakob Stoklund Olesen return MRI->canReserveReg(BasePtr); 341e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3Jim Grosbach} 342e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3Jim Grosbach 3433dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbachbool ARMBaseRegisterInfo:: 3443dab2778571b5bb00b35a0adcb7011dc85158bebJim GrosbachneedsStackRealignment(const MachineFunction &MF) const { 3453dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach const MachineFrameInfo *MFI = MF.getFrameInfo(); 346d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher const Function *F = MF.getFunction(); 34716c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 3486765834754cbb3cb0f15b4b15e98c5e73fa50066Bill Wendling bool requiresRealignment = 3496765834754cbb3cb0f15b4b15e98c5e73fa50066Bill Wendling ((MFI->getMaxAlignment() > StackAlign) || 350831737d329a727f53a1fb0572f7b7a8127208881Bill Wendling F->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 351831737d329a727f53a1fb0572f7b7a8127208881Bill Wendling Attribute::StackAlignment)); 3525c33f5bf67f61e3a1addda6de735d28d550dd0ebJim Grosbach 353d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher return requiresRealignment && canRealignStack(MF); 3543dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach} 3553dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach 3569631864688c593711f82bb8d21f8b724c628d786Jim Grosbachbool ARMBaseRegisterInfo:: 3579631864688c593711f82bb8d21f8b724c628d786Jim GrosbachcannotEliminateFrame(const MachineFunction &MF) const { 35898a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng const MachineFrameInfo *MFI = MF.getFrameInfo(); 3598a8d479214745c82ef00f08d4e4f1c173b5f9ce2Nick Lewycky if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack()) 36098a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng return true; 36131bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() 36231bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach || needsStackRealignment(MF); 36398a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng} 36498a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng 3655c33f5bf67f61e3a1addda6de735d28d550dd0ebJim Grosbachunsigned 3663f2bf85d14759cc4b28a86805f566ac805a54d00David GreeneARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 36716c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 368d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov 369d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov if (TFI->hasFP(MF)) 370c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return FramePtr; 371c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::SP; 372c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 373c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 374c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { 375c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("What is the exception register"); 376c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 377c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 378c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { 379c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("What is the exception handler register"); 380c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 381c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 382db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// emitLoadConstPool - Emits a load from constpool to materialize the 383db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// specified immediate. 384db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinvoid ARMBaseRegisterInfo:: 385db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinemitLoadConstPool(MachineBasicBlock &MBB, 386db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock::iterator &MBBI, 38777521f5232e679aa3de10aaaed2464aa91d7ff55David Goodwin DebugLoc dl, 388378445303b10b092a898a75131141a8259cff50bEvan Cheng unsigned DestReg, unsigned SubIdx, int Val, 389db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMCC::CondCodes Pred, 3903daccd82d3151fa3629de430b55698a81084fc9eAnton Korobeynikov unsigned PredReg, unsigned MIFlags) const { 391db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineFunction &MF = *MBB.getParent(); 39257148c166ab232191098492633c924fad9c44ef3Bill Wendling const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 393db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineConstantPool *ConstantPool = MF.getConstantPool(); 39446510a73e977273ec67747eb34cbdb43f815e451Dan Gohman const Constant *C = 3951d0be15f89cb5056e20e2d24faa8d6afb1573bcaOwen Anderson ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); 396db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 397db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 398378445303b10b092a898a75131141a8259cff50bEvan Cheng BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 399378445303b10b092a898a75131141a8259cff50bEvan Cheng .addReg(DestReg, getDefRegState(true), SubIdx) 400db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin .addConstantPoolIndex(Idx) 4013daccd82d3151fa3629de430b55698a81084fc9eAnton Korobeynikov .addImm(0).addImm(Pred).addReg(PredReg) 4023daccd82d3151fa3629de430b55698a81084fc9eAnton Korobeynikov .setMIFlags(MIFlags); 403db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 404db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 405db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinbool ARMBaseRegisterInfo:: 406db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinrequiresRegisterScavenging(const MachineFunction &MF) const { 407db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return true; 408db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 40941fff8c19ab6d8e28f5362481c184ad628f8c704Jim Grosbach 4107e831db1d4f5dc51ca6526739cf41e59895c5c20Jim Grosbachbool ARMBaseRegisterInfo:: 4116a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston GurdtrackLivenessAfterRegAlloc(const MachineFunction &MF) const { 4126a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd return true; 4136a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd} 4146a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurd 4156a8c7bf8e72338e55f0f9583e1828f62da165d4aPreston Gurdbool ARMBaseRegisterInfo:: 4167e831db1d4f5dc51ca6526739cf41e59895c5c20Jim GrosbachrequiresFrameIndexScavenging(const MachineFunction &MF) const { 417ca5dfb71ba4aa4a8392a021ec056cf0b70f74f1eJim Grosbach return true; 4187e831db1d4f5dc51ca6526739cf41e59895c5c20Jim Grosbach} 419db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 420a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbachbool ARMBaseRegisterInfo:: 421a273442891ae20fd8192526132e3819ea9e5eda9Jim GrosbachrequiresVirtualBaseRegisters(const MachineFunction &MF) const { 422c8cd8aa9d8582d2632db8fee8b2932efcdec34f1Jim Grosbach return true; 423a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach} 424a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach 425e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbachint64_t ARMBaseRegisterInfo:: 4261ab3f16f06698596716593a30545799688acccd7Jim GrosbachgetFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { 427e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = MI->getDesc(); 428e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 42990f20044ade3712c8b0c3f4ebe47d57ad15ae6ceChad Rosier int64_t InstrOffs = 0; 430e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach int Scale = 1; 431e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach unsigned ImmIdx = 0; 4321ab3f16f06698596716593a30545799688acccd7Jim Grosbach switch (AddrMode) { 433e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrModeT2_i8: 434e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrModeT2_i12: 4353e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARMII::AddrMode_i12: 436e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = MI->getOperand(Idx+1).getImm(); 437e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach Scale = 1; 438e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 439e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrMode5: { 440e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach // VFP address mode. 441e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach const MachineOperand &OffOp = MI->getOperand(Idx+1); 442f78ee6316bc755779920ac207edc27a89c0bd2f9Jim Grosbach InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); 443e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) 444e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = -InstrOffs; 445e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach Scale = 4; 446e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 447e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 448e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrMode2: { 449e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach ImmIdx = Idx+2; 450e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); 451e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 452e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = -InstrOffs; 453e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 454e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 455e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrMode3: { 456e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach ImmIdx = Idx+2; 457e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); 458e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 459e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = -InstrOffs; 460e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 461e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 462e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrModeT1_s: { 463e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach ImmIdx = Idx+1; 464e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = MI->getOperand(ImmIdx).getImm(); 465e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach Scale = 4; 466e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 467e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 468e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach default: 469e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach llvm_unreachable("Unsupported addressing mode!"); 470e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 471e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach 472e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach return InstrOffs * Scale; 473e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach} 474e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach 4758708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// needsFrameBaseReg - Returns true if the instruction's frame index 4768708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// reference would be better served by a base register other than FP 4778708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// or SP. Used by LocalStackFrameAllocation to determine which frame index 4788708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// references it should create new base registers for. 4798708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbachbool ARMBaseRegisterInfo:: 4803197380143cdc18837722129ac888528b9fbfc2bJim GrosbachneedsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 4813197380143cdc18837722129ac888528b9fbfc2bJim Grosbach for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) { 4823197380143cdc18837722129ac888528b9fbfc2bJim Grosbach assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 4833197380143cdc18837722129ac888528b9fbfc2bJim Grosbach } 4848708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 4858708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // It's the load/store FI references that cause issues, as it can be difficult 4868708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // to materialize the offset if it won't fit in the literal field. Estimate 4878708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // based on the size of the local frame and some conservative assumptions 4888708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // about the rest of the stack frame (note, this is pre-regalloc, so 4898708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // we don't know everything for certain yet) whether this offset is likely 4908708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // to be out of range of the immediate. Return true if so. 4918708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 492cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach // We only generate virtual base registers for loads and stores, so 493cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach // return false for everything else. 4948708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach unsigned Opc = MI->getOpcode(); 4958708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach switch (Opc) { 496cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12: 4977e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach case ARM::STRi12: case ARM::STRH: case ARM::STRBi12: 498cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2LDRi12: case ARM::t2LDRi8: 499cff9baa95273bc279bf5fadb9e27afbd25cca20bJakob Stoklund Olesen case ARM::t2STRi12: case ARM::t2STRi8: 5008708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach case ARM::VLDRS: case ARM::VLDRD: 5018708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach case ARM::VSTRS: case ARM::VSTRD: 50274d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach case ARM::tSTRspi: case ARM::tLDRspi: 503cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach break; 5048708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach default: 5058708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach return false; 5068708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach } 507cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach 508cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach // Without a virtual base register, if the function has variable sized 509cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach // objects, all fixed-size local references will be via the frame pointer, 5103197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Approximate the offset and see if it's legal for the instruction. 5113197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Note that the incoming offset is based on the SP value at function entry, 5123197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // so it'll be negative. 5133197380143cdc18837722129ac888528b9fbfc2bJim Grosbach MachineFunction &MF = *MI->getParent()->getParent(); 51416c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 5153197380143cdc18837722129ac888528b9fbfc2bJim Grosbach MachineFrameInfo *MFI = MF.getFrameInfo(); 5163197380143cdc18837722129ac888528b9fbfc2bJim Grosbach ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 5173197380143cdc18837722129ac888528b9fbfc2bJim Grosbach 5183197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Estimate an offset from the frame pointer. 5193197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Conservatively assume all callee-saved registers get pushed. R4-R6 5203197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // will be earlier than the FP, so we ignore those. 5213197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // R7, LR 5223197380143cdc18837722129ac888528b9fbfc2bJim Grosbach int64_t FPOffset = Offset - 8; 5233197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15 5243197380143cdc18837722129ac888528b9fbfc2bJim Grosbach if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction()) 5253197380143cdc18837722129ac888528b9fbfc2bJim Grosbach FPOffset -= 80; 5263197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Estimate an offset from the stack pointer. 527c1dc78de762e8a65fe1edd0cced13d94ab5a971fJim Grosbach // The incoming offset is relating to the SP at the start of the function, 528c1dc78de762e8a65fe1edd0cced13d94ab5a971fJim Grosbach // but when we access the local it'll be relative to the SP after local 529c1dc78de762e8a65fe1edd0cced13d94ab5a971fJim Grosbach // allocation, so adjust our SP-relative offset by that allocation size. 5303197380143cdc18837722129ac888528b9fbfc2bJim Grosbach Offset = -Offset; 531c1dc78de762e8a65fe1edd0cced13d94ab5a971fJim Grosbach Offset += MFI->getLocalFrameSize(); 5323197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Assume that we'll have at least some spill slots allocated. 5333197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // FIXME: This is a total SWAG number. We should run some statistics 5343197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // and pick a real one. 5353197380143cdc18837722129ac888528b9fbfc2bJim Grosbach Offset += 128; // 128 bytes of spill slots 5363197380143cdc18837722129ac888528b9fbfc2bJim Grosbach 5373197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // If there is a frame pointer, try using it. 5383197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // The FP is only available if there is no dynamic realignment. We 5393197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // don't know for sure yet whether we'll need that, so we guess based 5403197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // on whether there are any local variables that would trigger it. 54116c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov unsigned StackAlign = TFI->getStackAlignment(); 542d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov if (TFI->hasFP(MF) && 5433197380143cdc18837722129ac888528b9fbfc2bJim Grosbach !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) { 5443197380143cdc18837722129ac888528b9fbfc2bJim Grosbach if (isFrameOffsetLegal(MI, FPOffset)) 5453197380143cdc18837722129ac888528b9fbfc2bJim Grosbach return false; 5463197380143cdc18837722129ac888528b9fbfc2bJim Grosbach } 5473197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // If we can reference via the stack pointer, try that. 5483197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // FIXME: This (and the code that resolves the references) can be improved 5493197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // to only disallow SP relative references in the live range of 5503197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // the VLA(s). In practice, it's unclear how much difference that 5513197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // would make, but it may be worth doing. 5523197380143cdc18837722129ac888528b9fbfc2bJim Grosbach if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset)) 5533197380143cdc18837722129ac888528b9fbfc2bJim Grosbach return false; 554cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach 5553197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // The offset likely isn't legal, we want to allocate a virtual base register. 556cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach return true; 5578708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach} 5588708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 559976ef86689ed065361a748f81c44ca3510af2202Bill Wendling/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to 560976ef86689ed065361a748f81c44ca3510af2202Bill Wendling/// be a pointer to FrameIdx at the beginning of the basic block. 561dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbachvoid ARMBaseRegisterInfo:: 562976ef86689ed065361a748f81c44ca3510af2202Bill WendlingmaterializeFrameBaseRegister(MachineBasicBlock *MBB, 563976ef86689ed065361a748f81c44ca3510af2202Bill Wendling unsigned BaseReg, int FrameIdx, 564976ef86689ed065361a748f81c44ca3510af2202Bill Wendling int64_t Offset) const { 565976ef86689ed065361a748f81c44ca3510af2202Bill Wendling ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>(); 56674d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : 56774d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri); 568dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 569976ef86689ed065361a748f81c44ca3510af2202Bill Wendling MachineBasicBlock::iterator Ins = MBB->begin(); 570976ef86689ed065361a748f81c44ca3510af2202Bill Wendling DebugLoc DL; // Defaults to "unknown" 571976ef86689ed065361a748f81c44ca3510af2202Bill Wendling if (Ins != MBB->end()) 572976ef86689ed065361a748f81c44ca3510af2202Bill Wendling DL = Ins->getDebugLoc(); 573976ef86689ed065361a748f81c44ca3510af2202Bill Wendling 574397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen const MachineFunction &MF = *MBB->getParent(); 57557148c166ab232191098492633c924fad9c44ef3Bill Wendling MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 57657148c166ab232191098492633c924fad9c44ef3Bill Wendling const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 57757148c166ab232191098492633c924fad9c44ef3Bill Wendling const MCInstrDesc &MCID = TII.get(ADDriOpc); 578397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 57921803721d538255e4d223c29b6c8d3c9e93d4d86Cameron Zwarich 5805b81584f7403ffdb9cc6babaaeb0411c080e0f81Jim Grosbach MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg) 5815b81584f7403ffdb9cc6babaaeb0411c080e0f81Jim Grosbach .addFrameIndex(FrameIdx).addImm(Offset)); 582976ef86689ed065361a748f81c44ca3510af2202Bill Wendling 58374d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach if (!AFI->isThumb1OnlyFunction()) 5845b81584f7403ffdb9cc6babaaeb0411c080e0f81Jim Grosbach AddDefaultCC(MIB); 585dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach} 586dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 587dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbachvoid 588dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim GrosbachARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I, 589dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach unsigned BaseReg, int64_t Offset) const { 590dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach MachineInstr &MI = *I; 591dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach MachineBasicBlock &MBB = *MI.getParent(); 592dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach MachineFunction &MF = *MBB.getParent(); 59357148c166ab232191098492633c924fad9c44ef3Bill Wendling const ARMBaseInstrInfo &TII = 59457148c166ab232191098492633c924fad9c44ef3Bill Wendling *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo()); 595dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 596dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach int Off = Offset; // ARM doesn't need the general 64-bit offsets 597dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach unsigned i = 0; 598dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 599dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach assert(!AFI->isThumb1OnlyFunction() && 600dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach "This resolveFrameIndex does not support Thumb1!"); 601dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 602dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach while (!MI.getOperand(i).isFI()) { 603dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach ++i; 604dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 605dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach } 606dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach bool Done = false; 607dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach if (!AFI->isThumbFunction()) 608dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); 609dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach else { 610dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach assert(AFI->isThumb2Function()); 611dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII); 612dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach } 613dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach assert (Done && "Unable to resolve frame index!"); 6141f6a329f79b3568d379142f921f59c4143ddaa14Duncan Sands (void)Done; 615dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach} 6168708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 617e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbachbool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 618e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach int64_t Offset) const { 619e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = MI->getDesc(); 6202b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 6212b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned i = 0; 6222b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 6232b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach while (!MI->getOperand(i).isFI()) { 6242b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach ++i; 6252b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 6262b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach } 6272b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 6282b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach // AddrMode4 and AddrMode6 cannot handle any offset. 6292b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) 6302b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach return Offset == 0; 6312b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 6322b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned NumBits = 0; 6332b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned Scale = 1; 634e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach bool isSigned = true; 6351ab3f16f06698596716593a30545799688acccd7Jim Grosbach switch (AddrMode) { 6362b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach case ARMII::AddrModeT2_i8: 6372b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach case ARMII::AddrModeT2_i12: 6382b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach // i8 supports only negative, and i12 supports only positive, so 6392b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach // based on Offset sign, consider the appropriate instruction 64074d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach Scale = 1; 6412b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach if (Offset < 0) { 6422b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 8; 6432b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach Offset = -Offset; 6442b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach } else { 6452b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 12; 6462b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach } 6472b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach break; 6481ab3f16f06698596716593a30545799688acccd7Jim Grosbach case ARMII::AddrMode5: 6492b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach // VFP address mode. 6502b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 8; 6512b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach Scale = 4; 6522b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach break; 6533e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARMII::AddrMode_i12: 6541ab3f16f06698596716593a30545799688acccd7Jim Grosbach case ARMII::AddrMode2: 6552b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 12; 6562b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach break; 6571ab3f16f06698596716593a30545799688acccd7Jim Grosbach case ARMII::AddrMode3: 6582b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 8; 6592b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach break; 660e575499d830008784b11499dae290ad0480c8f9dBill Wendling case ARMII::AddrModeT1_s: 661e575499d830008784b11499dae290ad0480c8f9dBill Wendling NumBits = 5; 66274d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach Scale = 4; 663e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach isSigned = false; 66474d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach break; 6652b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach default: 6662b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach llvm_unreachable("Unsupported addressing mode!"); 6672b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach } 6682b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 6691ab3f16f06698596716593a30545799688acccd7Jim Grosbach Offset += getFrameIndexInstrOffset(MI, i); 670d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach // Make sure the offset is encodable for instructions that scale the 671d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach // immediate. 672d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach if ((Offset & (Scale-1)) != 0) 673d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach return false; 674d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach 675e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach if (isSigned && Offset < 0) 6762b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach Offset = -Offset; 6772b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 6782b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned Mask = (1 << NumBits) - 1; 6792b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach if ((unsigned)Offset <= Mask * Scale) 6802b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach return true; 68174d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach 68274d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach return false; 68374d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach} 68474d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach 685fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbachvoid 6866495f63945e8dbde81f03a1dc2ab421993b9a495Evan ChengARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 687108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier int SPAdj, unsigned FIOperandNum, 688108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier RegScavenger *RS) const { 6895ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MachineInstr &MI = *II; 6905ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MachineBasicBlock &MBB = *MI.getParent(); 6915ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MachineFunction &MF = *MBB.getParent(); 69257148c166ab232191098492633c924fad9c44ef3Bill Wendling const ARMBaseInstrInfo &TII = 69357148c166ab232191098492633c924fad9c44ef3Bill Wendling *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo()); 69416c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov const ARMFrameLowering *TFI = 69516c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering()); 6965ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 6976495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(!AFI->isThumb1OnlyFunction() && 698a15de00f8246f19180b26ee5fe7ff8f436e0de08Bob Wilson "This eliminateFrameIndex does not support Thumb1!"); 699108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 700a37aa546224ec03ba1f1a1598e0781af4b692673Jim Grosbach unsigned FrameReg; 7015ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 70282f58740c76b42af8370247b23677a0318f6dde8Anton Korobeynikov int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); 7035ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 7040f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the 7050f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // call frame setup/destroy instructions have already been eliminated. That 7060f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // means the stack pointer cannot be used to access the emergency spill slot 7070f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen // when !hasReservedCallFrame(). 7080f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen#ifndef NDEBUG 709dc3beb90178fc316f63790812b22201884eaa017Hal Finkel if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){ 7100f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen assert(TFI->hasReservedCallFrame(MF) && 7110f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen "Cannot use SP to access the emergency spill slot in " 7120f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen "functions without a reserved call frame"); 7130f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen assert(!MF.getFrameInfo()->hasVarSizedObjects() && 7140f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen "Cannot use SP to access the emergency spill slot in " 7150f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen "functions with variable sized frame objects"); 7160f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen } 7170f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen#endif // NDEBUG 7180f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9Jakob Stoklund Olesen 7196d9dbd5526e3161db884fc4fe99c278bb59ccc19David Blaikie assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code"); 72062b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng 72148d8afab73d72418cf9505a020f621014920463cEvan Cheng // Modify MI as necessary to handle as much of 'Offset' as possible 722cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng bool Done = false; 7236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (!AFI->isThumbFunction()) 724108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 7256495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng else { 7266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(AFI->isThumb2Function()); 727108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 7286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 729cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng if (Done) 730fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach return; 7315ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 732db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // If we get here, the immediate doesn't fit into the instruction. We folded 733db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // as much as possible above, handle the rest, providing a register that is 734db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // SP+LargeImm. 73519bb87d0f80f3e6eed38a9fa267bf2b0474aeaabDaniel Dunbar assert((Offset || 736a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || 737a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && 738cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng "This code isn't needed if offset already handled!"); 739db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 7407e831db1d4f5dc51ca6526739cf41e59895c5c20Jim Grosbach unsigned ScratchReg = 0; 741db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin int PIdx = MI.findFirstPredOperandIdx(); 742db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMCC::CondCodes Pred = (PIdx == -1) 743db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 744db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 745cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng if (Offset == 0) 746a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach // Must be addrmode4/6. 747108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false); 7486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng else { 749420761a0f193e87d08ee1c51b26bba23ab4bac7fCraig Topper ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass); 750cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng if (!AFI->isThumbFunction()) 751cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 752cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset, Pred, PredReg, TII); 753cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng else { 754cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng assert(AFI->isThumb2Function()); 755cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 756cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset, Pred, PredReg, TII); 757cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng } 758cde31293d45f14ddff482d385429d256bd4e0820Jim Grosbach // Update the original instruction to use the scratch register. 759108fb3202af6f500073cdbb7be32c25d7a273a2eChad Rosier MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true); 7606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 761db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 762