ARMBaseRegisterInfo.cpp revision 8708ead5a46f4ec8f2d5f832be23381924d72b8d
12cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattner//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===// 2c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 3c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// The LLVM Compiler Infrastructure 4c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 5c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// This file is distributed under the University of Illinois Open Source 6c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// License. See LICENSE.TXT for details. 7c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 8c140c4803dc3e10e08138670829bc0494986abe9David Goodwin//===----------------------------------------------------------------------===// 9c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 10c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// This file contains the base ARM implementation of TargetRegisterInfo class. 11c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 12c140c4803dc3e10e08138670829bc0494986abe9David Goodwin//===----------------------------------------------------------------------===// 13c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 14c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARM.h" 15c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMAddressingModes.h" 16db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin#include "ARMBaseInstrInfo.h" 17c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMBaseRegisterInfo.h" 18c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMInstrInfo.h" 19c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMMachineFunctionInfo.h" 20c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMSubtarget.h" 21c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/Constants.h" 22c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/DerivedTypes.h" 239adc0abad3c3ed40a268ccbcee0c74cb9e1359feOwen Anderson#include "llvm/Function.h" 249adc0abad3c3ed40a268ccbcee0c74cb9e1359feOwen Anderson#include "llvm/LLVMContext.h" 25c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineConstantPool.h" 26c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 27c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineFunction.h" 28c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 29c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineLocation.h" 30c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineRegisterInfo.h" 31c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/RegisterScavenging.h" 323dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach#include "llvm/Support/Debug.h" 33ab7c09b6b6f4516a631fd6788918c237c83939afTorok Edwin#include "llvm/Support/ErrorHandling.h" 34dac237e18209b697a8ba122d0ddd9cad4dfba1f8Torok Edwin#include "llvm/Support/raw_ostream.h" 35c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/Target/TargetFrameInfo.h" 36c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/Target/TargetMachine.h" 37c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/Target/TargetOptions.h" 38c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/ADT/BitVector.h" 39c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/ADT/SmallVector.h" 4018ed9c9a2bd7f1f56129495b499264c58b5cc4f4Jim Grosbach#include "llvm/Support/CommandLine.h" 41c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 428c407d45964fbba19719be555324f247e4fb14e1Dan Gohmannamespace llvm { 438c407d45964fbba19719be555324f247e4fb14e1Dan Gohmancl::opt<bool> 44a6a99b4e160eea0060b25fbdeadc3437cd67d617Jim GrosbachReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(true), 4518ed9c9a2bd7f1f56129495b499264c58b5cc4f4Jim Grosbach cl::desc("Reuse repeated frame index values")); 468c407d45964fbba19719be555324f247e4fb14e1Dan Gohman} 478c407d45964fbba19719be555324f247e4fb14e1Dan Gohman 488c407d45964fbba19719be555324f247e4fb14e1Dan Gohmanusing namespace llvm; 4918ed9c9a2bd7f1f56129495b499264c58b5cc4f4Jim Grosbach 50c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum, 518295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng bool *isSPVFP) { 528295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng if (isSPVFP) 538295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng *isSPVFP = false; 54c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 55c140c4803dc3e10e08138670829bc0494986abe9David Goodwin using namespace ARM; 56c140c4803dc3e10e08138670829bc0494986abe9David Goodwin switch (RegEnum) { 57c140c4803dc3e10e08138670829bc0494986abe9David Goodwin default: 58c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Unknown ARM register!"); 598295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R0: case D0: case Q0: return 0; 608295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R1: case D1: case Q1: return 1; 618295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R2: case D2: case Q2: return 2; 628295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R3: case D3: case Q3: return 3; 638295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R4: case D4: case Q4: return 4; 648295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R5: case D5: case Q5: return 5; 658295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R6: case D6: case Q6: return 6; 668295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R7: case D7: case Q7: return 7; 678295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R8: case D8: case Q8: return 8; 688295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R9: case D9: case Q9: return 9; 698295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R10: case D10: case Q10: return 10; 708295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R11: case D11: case Q11: return 11; 718295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R12: case D12: case Q12: return 12; 728295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case SP: case D13: case Q13: return 13; 738295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case LR: case D14: case Q14: return 14; 748295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case PC: case D15: case Q15: return 15; 758295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng 768295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D16: return 16; 778295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D17: return 17; 788295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D18: return 18; 798295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D19: return 19; 808295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D20: return 20; 818295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D21: return 21; 828295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D22: return 22; 838295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D23: return 23; 848295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D24: return 24; 858295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D25: return 25; 8698330ff8e344d2e88c0a2166901d394e813e8162Bob Wilson case D26: return 26; 878295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D27: return 27; 888295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D28: return 28; 898295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D29: return 29; 908295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D30: return 30; 918295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D31: return 31; 92c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 93c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S0: case S1: case S2: case S3: 94c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S4: case S5: case S6: case S7: 95c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S8: case S9: case S10: case S11: 96c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S12: case S13: case S14: case S15: 97c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S16: case S17: case S18: case S19: 98c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S20: case S21: case S22: case S23: 99c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S24: case S25: case S26: case S27: 1008295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case S28: case S29: case S30: case S31: { 1018295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng if (isSPVFP) 1028295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng *isSPVFP = true; 103c140c4803dc3e10e08138670829bc0494986abe9David Goodwin switch (RegEnum) { 104c140c4803dc3e10e08138670829bc0494986abe9David Goodwin default: return 0; // Avoid compile time warning. 105c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S0: return 0; 106c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S1: return 1; 107c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S2: return 2; 108c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S3: return 3; 109c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S4: return 4; 110c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S5: return 5; 111c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S6: return 6; 112c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S7: return 7; 113c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S8: return 8; 114c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S9: return 9; 115c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S10: return 10; 116c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S11: return 11; 117c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S12: return 12; 118c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S13: return 13; 119c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S14: return 14; 120c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S15: return 15; 121c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S16: return 16; 122c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S17: return 17; 123c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S18: return 18; 124c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S19: return 19; 125c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S20: return 20; 126c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S21: return 21; 127c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S22: return 22; 128c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S23: return 23; 129c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S24: return 24; 130c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S25: return 25; 131c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S26: return 26; 132c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S27: return 27; 133c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S28: return 28; 134c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S29: return 29; 135c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S30: return 30; 136c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S31: return 31; 137c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 138c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 139c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 140c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 141c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 142db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, 143c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const ARMSubtarget &sti) 144c140c4803dc3e10e08138670829bc0494986abe9David Goodwin : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 145c140c4803dc3e10e08138670829bc0494986abe9David Goodwin TII(tii), STI(sti), 146c140c4803dc3e10e08138670829bc0494986abe9David Goodwin FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) { 147c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 148c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 149c140c4803dc3e10e08138670829bc0494986abe9David Goodwinconst unsigned* 150c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 151c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned CalleeSavedRegs[] = { 152c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 153c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R7, ARM::R6, ARM::R5, ARM::R4, 154c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 155c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::D15, ARM::D14, ARM::D13, ARM::D12, 156c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::D11, ARM::D10, ARM::D9, ARM::D8, 157c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 0 158c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 159c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 160c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned DarwinCalleeSavedRegs[] = { 161c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved 162c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // register. 163c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 164c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R11, ARM::R10, ARM::R8, 165c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 166c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::D15, ARM::D14, ARM::D13, ARM::D12, 167c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::D11, ARM::D10, ARM::D9, ARM::D8, 168c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 0 169c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 170c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 171c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 172c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1739631864688c593711f82bb8d21f8b724c628d786Jim GrosbachBitVector ARMBaseRegisterInfo:: 1749631864688c593711f82bb8d21f8b724c628d786Jim GrosbachgetReservedRegs(const MachineFunction &MF) const { 175c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // FIXME: avoid re-calculating this everytime. 176c140c4803dc3e10e08138670829bc0494986abe9David Goodwin BitVector Reserved(getNumRegs()); 177c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(ARM::SP); 178c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(ARM::PC); 179d1fb583128c6682bb8a7c74eafa810a9270cc8dfNate Begeman Reserved.set(ARM::FPSCR); 180ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (hasFP(MF)) 181c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(FramePtr); 182c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Some targets reserve R9. 183c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (STI.isR9Reserved()) 184c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(ARM::R9); 185c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return Reserved; 186c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 187c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1882cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattnerbool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF, 1892cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattner unsigned Reg) const { 190c140c4803dc3e10e08138670829bc0494986abe9David Goodwin switch (Reg) { 191c140c4803dc3e10e08138670829bc0494986abe9David Goodwin default: break; 192c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::SP: 193c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::PC: 194c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return true; 195c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R7: 196c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R11: 197ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (FramePtr == Reg && hasFP(MF)) 198c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return true; 199c140c4803dc3e10e08138670829bc0494986abe9David Goodwin break; 200c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R9: 201c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return STI.isR9Reserved(); 202c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 203c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 204c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return false; 205c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 206c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 2072cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattnerconst TargetRegisterClass * 2084f54c1293af174a8002db20faf7b4f82ba4e8514Evan ChengARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, 2094f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng const TargetRegisterClass *B, 2104f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng unsigned SubIdx) const { 2114f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng switch (SubIdx) { 2124f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng default: return 0; 213e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::ssub_0: 214e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::ssub_1: 215e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::ssub_2: 216e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::ssub_3: { 2174f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng // S sub-registers. 2184f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng if (A->getSize() == 8) { 219ba908640b3e0c1218748776e244d4b7234451155Evan Cheng if (B == &ARM::SPR_8RegClass) 220ba908640b3e0c1218748776e244d4b7234451155Evan Cheng return &ARM::DPR_8RegClass; 221ba908640b3e0c1218748776e244d4b7234451155Evan Cheng assert(B == &ARM::SPRRegClass && "Expecting SPR register class!"); 2224f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng if (A == &ARM::DPR_8RegClass) 2234f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng return A; 2244f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng return &ARM::DPR_VFP2RegClass; 2254f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng } 2264f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng 227b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng if (A->getSize() == 16) { 228b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng if (B == &ARM::SPR_8RegClass) 229b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng return &ARM::QPR_8RegClass; 230b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng return &ARM::QPR_VFP2RegClass; 231b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng } 232b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng 23322c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (A->getSize() == 32) { 23422c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (B == &ARM::SPR_8RegClass) 23522c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return 0; // Do not allow coalescing! 23622c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return &ARM::QQPR_VFP2RegClass; 23722c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng } 23822c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng 23922c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng assert(A->getSize() == 64 && "Expecting a QQQQ register class!"); 24022c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return 0; // Do not allow coalescing! 241b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng } 242e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::dsub_0: 243e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::dsub_1: 244e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::dsub_2: 245e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::dsub_3: { 2464f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng // D sub-registers. 247b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng if (A->getSize() == 16) { 248b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng if (B == &ARM::DPR_VFP2RegClass) 249b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng return &ARM::QPR_VFP2RegClass; 250b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng if (B == &ARM::DPR_8RegClass) 25122c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return 0; // Do not allow coalescing! 252b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng return A; 253b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng } 254b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng 25522c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (A->getSize() == 32) { 25622c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (B == &ARM::DPR_VFP2RegClass) 25722c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return &ARM::QQPR_VFP2RegClass; 25822c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (B == &ARM::DPR_8RegClass) 25922c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return 0; // Do not allow coalescing! 26022c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return A; 26122c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng } 26222c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng 26322c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng assert(A->getSize() == 64 && "Expecting a QQQQ register class!"); 26422c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (B != &ARM::DPRRegClass) 26522c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return 0; // Do not allow coalescing! 2664f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng return A; 2674f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng } 268e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::dsub_4: 269e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::dsub_5: 270e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::dsub_6: 271e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::dsub_7: { 27222c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // D sub-registers of QQQQ registers. 27322c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (A->getSize() == 64 && B == &ARM::DPRRegClass) 27422c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return A; 27522c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return 0; // Do not allow coalescing! 27622c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng } 27722c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng 278e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::qsub_0: 279e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::qsub_1: { 280b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng // Q sub-registers. 28122c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (A->getSize() == 32) { 28222c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (B == &ARM::QPR_VFP2RegClass) 28322c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return &ARM::QQPR_VFP2RegClass; 28422c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (B == &ARM::QPR_8RegClass) 28522c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return 0; // Do not allow coalescing! 28622c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return A; 28722c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng } 28822c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng 28922c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng assert(A->getSize() == 64 && "Expecting a QQQQ register class!"); 29022c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (B == &ARM::QPRRegClass) 29122c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return A; 29222c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return 0; // Do not allow coalescing! 29322c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng } 294e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::qsub_2: 295e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::qsub_3: { 29622c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // Q sub-registers of QQQQ registers. 29722c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (A->getSize() == 64 && B == &ARM::QPRRegClass) 29822c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return A; 29922c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return 0; // Do not allow coalescing! 300b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng } 301b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng } 3024f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng return 0; 3034f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng} 3044f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng 305b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Chengbool 30691a74da036d3a9442953ae1de3e797a50da4ccf0Bob WilsonARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC, 307b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng SmallVectorImpl<unsigned> &SubIndices, 308b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng unsigned &NewSubIdx) const { 309b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng 310b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng unsigned Size = RC->getSize() * 8; 311b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (Size < 6) 312b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return 0; 313b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng 314b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng NewSubIdx = 0; // Whole register. 315b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng unsigned NumRegs = SubIndices.size(); 316b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (NumRegs == 8) { 317b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 8 D registers -> 1 QQQQ register. 318b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return (Size == 512 && 319558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[0] == ARM::dsub_0 && 320558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[1] == ARM::dsub_1 && 321558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[2] == ARM::dsub_2 && 322558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[3] == ARM::dsub_3 && 323558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[4] == ARM::dsub_4 && 324558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[5] == ARM::dsub_5 && 325558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[6] == ARM::dsub_6 && 326558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[7] == ARM::dsub_7); 327b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } else if (NumRegs == 4) { 328558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (SubIndices[0] == ARM::qsub_0) { 329b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 4 Q registers -> 1 QQQQ register. 330b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return (Size == 512 && 331558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[1] == ARM::qsub_1 && 332558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[2] == ARM::qsub_2 && 333558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[3] == ARM::qsub_3); 334558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::dsub_0) { 335b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 4 D registers -> 1 QQ register. 336b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (Size >= 256 && 337558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[1] == ARM::dsub_1 && 338558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[2] == ARM::dsub_2 && 339558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[3] == ARM::dsub_3) { 340b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (Size == 512) 341558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::qqsub_0; 342b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 343b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 344558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::dsub_4) { 345b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 4 D registers -> 1 QQ register (2nd). 346b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (Size == 512 && 347558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[1] == ARM::dsub_5 && 348558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[2] == ARM::dsub_6 && 349558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[3] == ARM::dsub_7) { 350558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::qqsub_1; 351b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 352b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 353558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::ssub_0) { 354b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 4 S registers -> 1 Q register. 355b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (Size >= 128 && 356558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[1] == ARM::ssub_1 && 357558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[2] == ARM::ssub_2 && 358558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[3] == ARM::ssub_3) { 359b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (Size >= 256) 360558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::qsub_0; 361b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 362b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 363b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 364b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } else if (NumRegs == 2) { 365558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (SubIndices[0] == ARM::qsub_0) { 366b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 2 Q registers -> 1 QQ register. 367558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (Size >= 256 && SubIndices[1] == ARM::qsub_1) { 368b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (Size == 512) 369558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::qqsub_0; 370b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 371b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 372558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::qsub_2) { 373b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 2 Q registers -> 1 QQ register (2nd). 374558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (Size == 512 && SubIndices[1] == ARM::qsub_3) { 375558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::qqsub_1; 376b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 377b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 378558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::dsub_0) { 379b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 2 D registers -> 1 Q register. 380558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (Size >= 128 && SubIndices[1] == ARM::dsub_1) { 381b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (Size >= 256) 382558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::qsub_0; 383b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 384b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 385558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::dsub_2) { 386b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 2 D registers -> 1 Q register (2nd). 387558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (Size >= 256 && SubIndices[1] == ARM::dsub_3) { 388558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::qsub_1; 389b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 390b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 391558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::dsub_4) { 392b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 2 D registers -> 1 Q register (3rd). 393558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (Size == 512 && SubIndices[1] == ARM::dsub_5) { 394558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::qsub_2; 395b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 396b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 397558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::dsub_6) { 398b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 2 D registers -> 1 Q register (3rd). 399558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (Size == 512 && SubIndices[1] == ARM::dsub_7) { 400558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::qsub_3; 401b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 402b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 403558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::ssub_0) { 404b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 2 S registers -> 1 D register. 405558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (SubIndices[1] == ARM::ssub_1) { 406b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (Size >= 128) 407558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::dsub_0; 408b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 409b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 410558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::ssub_2) { 411b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 2 S registers -> 1 D register (2nd). 412558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (Size >= 128 && SubIndices[1] == ARM::ssub_3) { 413558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::dsub_1; 414b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 415b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 416b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 417b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 418b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return false; 419b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng} 420b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng 421b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng 4224f54c1293af174a8002db20faf7b4f82ba4e8514Evan Chengconst TargetRegisterClass * 4232cfd52c507bd5790457a171eb9bcb39019cc6860Chris LattnerARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const { 424e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach return ARM::GPRRegisterClass; 425c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 426c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 427c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// getAllocationOrder - Returns the register allocation order for a specified 428c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// register class in the form of a pair of TargetRegisterClass iterators. 429c140c4803dc3e10e08138670829bc0494986abe9David Goodwinstd::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator> 430c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC, 431c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned HintType, unsigned HintReg, 432c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const MachineFunction &MF) const { 433c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Alternative register allocation orders when favoring even / odd registers 434c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // of register pairs. 435c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 436c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // No FP, R9 is available. 437c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven1[] = { 438c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, 439c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, 440c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R9, ARM::R11 441c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 442c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd1[] = { 443c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11, 444c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 445c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R8, ARM::R10 446c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 447c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 448c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // FP is R7, R9 is available. 449c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven2[] = { 450c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10, 451c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, 452c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R9, ARM::R11 453c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 454c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd2[] = { 455c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11, 456c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 457c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R8, ARM::R10 458c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 459c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 460c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // FP is R11, R9 is available. 461c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven3[] = { 462c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, 463c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, 464c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R9 465c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 466c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd3[] = { 467c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9, 468c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7, 469c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R8 470c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 471c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 472c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // No FP, R9 is not available. 473c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven4[] = { 474c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10, 475c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8, 476c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R11 477c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 478c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd4[] = { 479c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11, 480c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 481c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R10 482c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 483c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 484c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // FP is R7, R9 is not available. 485c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven5[] = { 486c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R10, 487c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8, 488c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R11 489c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 490c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd5[] = { 491c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R11, 492c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 493c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R10 494c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 495c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 496c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // FP is R11, R9 is not available. 497c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven6[] = { 498c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R6, 499c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8 500c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 501c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd6[] = { 502c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R7, 503c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8 504c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 505c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 506c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 507c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (HintType == ARMRI::RegPairEven) { 508c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0) 509c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // It's no longer possible to fulfill this hint. Return the default 510c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // allocation order. 511c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(RC->allocation_order_begin(MF), 512c140c4803dc3e10e08138670829bc0494986abe9David Goodwin RC->allocation_order_end(MF)); 513c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 514ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (!hasFP(MF)) { 515c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 516c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPREven1, 517c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPREven1 + (sizeof(GPREven1)/sizeof(unsigned))); 518c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 519c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPREven4, 520c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPREven4 + (sizeof(GPREven4)/sizeof(unsigned))); 521c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else if (FramePtr == ARM::R7) { 522c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 523c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPREven2, 524c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPREven2 + (sizeof(GPREven2)/sizeof(unsigned))); 525c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 526c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPREven5, 527c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPREven5 + (sizeof(GPREven5)/sizeof(unsigned))); 528c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else { // FramePtr == ARM::R11 529c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 530c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPREven3, 531c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPREven3 + (sizeof(GPREven3)/sizeof(unsigned))); 532c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 533c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPREven6, 534c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPREven6 + (sizeof(GPREven6)/sizeof(unsigned))); 535c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 536c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else if (HintType == ARMRI::RegPairOdd) { 537c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0) 538c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // It's no longer possible to fulfill this hint. Return the default 539c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // allocation order. 540c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(RC->allocation_order_begin(MF), 541c140c4803dc3e10e08138670829bc0494986abe9David Goodwin RC->allocation_order_end(MF)); 542c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 543ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (!hasFP(MF)) { 544c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 545c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPROdd1, 546c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned))); 547c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 548c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPROdd4, 549c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned))); 550c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else if (FramePtr == ARM::R7) { 551c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 552c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPROdd2, 553c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned))); 554c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 555c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPROdd5, 556c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned))); 557c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else { // FramePtr == ARM::R11 558c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 559c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPROdd3, 560c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned))); 561c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 562c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPROdd6, 563c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned))); 564c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 565c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 566c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(RC->allocation_order_begin(MF), 567c140c4803dc3e10e08138670829bc0494986abe9David Goodwin RC->allocation_order_end(MF)); 568c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 569c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 570c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// ResolveRegAllocHint - Resolves the specified register allocation hint 571c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// to a physical register. Returns the physical register if it is successful. 572c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned 573c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg, 574c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const MachineFunction &MF) const { 575c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (Reg == 0 || !isPhysicalRegister(Reg)) 576c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 577c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (Type == 0) 578c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return Reg; 579c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else if (Type == (unsigned)ARMRI::RegPairOdd) 580c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Odd register. 581c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return getRegisterPairOdd(Reg, MF); 582c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else if (Type == (unsigned)ARMRI::RegPairEven) 583c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Even register. 584c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return getRegisterPairEven(Reg, MF); 585c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 586c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 587c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 588c140c4803dc3e10e08138670829bc0494986abe9David Goodwinvoid 589c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 590c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MachineFunction &MF) const { 591c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MachineRegisterInfo *MRI = &MF.getRegInfo(); 592c140c4803dc3e10e08138670829bc0494986abe9David Goodwin std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 593c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 594c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Hint.first == (unsigned)ARMRI::RegPairEven) && 595c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) { 596c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // If 'Reg' is one of the even / odd register pair and it's now changed 597c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // (e.g. coalesced) into a different register. The other register of the 598c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // pair allocation hint must be updated to reflect the relationship 599c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // change. 600c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned OtherReg = Hint.second; 601c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Hint = MRI->getRegAllocationHint(OtherReg); 602c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (Hint.second == Reg) 603c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Make sure the pair has not already divorced. 604c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 605c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 606c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 607c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 608c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// hasFP - Return true if the specified function should have a dedicated frame 609c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// pointer register. This is true if the function has variable sized allocas 610c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// or if frame pointer elimination is disabled. 611c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// 612c140c4803dc3e10e08138670829bc0494986abe9David Goodwinbool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const { 613ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng // Mac OS X requires FP not to be clobbered for backtracing purpose. 614ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (STI.isTargetDarwin()) 615ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng return true; 616ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng 617c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const MachineFrameInfo *MFI = MF.getFrameInfo(); 618b000d683c822bab7bed608937048b24b4b6db551Evan Cheng // Always eliminate non-leaf frame pointers. 619b000d683c822bab7bed608937048b24b4b6db551Evan Cheng return ((DisableFramePointerElim(MF) && MFI->hasCalls()) || 6203dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach needsStackRealignment(MF) || 621c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MFI->hasVarSizedObjects() || 622c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MFI->isFrameAddressTaken()); 623c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 624c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 625e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3Jim Grosbachbool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { 626e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3Jim Grosbach const MachineFrameInfo *MFI = MF.getFrameInfo(); 627e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3Jim Grosbach const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 628e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3Jim Grosbach return (RealignStack && 629e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3Jim Grosbach !AFI->isThumb1OnlyFunction() && 630e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3Jim Grosbach !MFI->hasVarSizedObjects()); 631e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3Jim Grosbach} 632e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3Jim Grosbach 6333dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbachbool ARMBaseRegisterInfo:: 6343dab2778571b5bb00b35a0adcb7011dc85158bebJim GrosbachneedsStackRealignment(const MachineFunction &MF) const { 6353dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach const MachineFrameInfo *MFI = MF.getFrameInfo(); 636d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher const Function *F = MF.getFunction(); 6373dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 638ad353c74adda55556f7a3969721c3e49ac16d570Jim Grosbach unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 639697cba8ec2b3f5160175fd5b4a641dbd48606e17Eric Christopher bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) || 640697cba8ec2b3f5160175fd5b4a641dbd48606e17Eric Christopher F->hasFnAttr(Attribute::StackAlignment)); 641d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher 642d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher // FIXME: Currently we don't support stack realignment for functions with 643d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher // variable-sized allocas. 644d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher // FIXME: It's more complicated than this... 645d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher if (0 && requiresRealignment && MFI->hasVarSizedObjects()) 646d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher report_fatal_error( 647d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher "Stack realignment in presense of dynamic allocas is not supported"); 648d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher 649d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher // FIXME: This probably isn't the right place for this. 650d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher if (0 && requiresRealignment && AFI->isThumb1OnlyFunction()) 651d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher report_fatal_error( 652d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher "Stack realignment in thumb1 functions is not supported"); 653d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher 654d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher return requiresRealignment && canRealignStack(MF); 6553dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach} 6563dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach 6579631864688c593711f82bb8d21f8b724c628d786Jim Grosbachbool ARMBaseRegisterInfo:: 6589631864688c593711f82bb8d21f8b724c628d786Jim GrosbachcannotEliminateFrame(const MachineFunction &MF) const { 65998a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng const MachineFrameInfo *MFI = MF.getFrameInfo(); 660b92187a4103dca24c3767c380f63593d1f6161a7Bill Wendling if (DisableFramePointerElim(MF) && MFI->adjustsStack()) 66198a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng return true; 66231bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() 66331bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach || needsStackRealignment(MF); 66498a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng} 66598a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng 666542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng/// estimateStackSize - Estimate and return the size of the frame. 667657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesenstatic unsigned estimateStackSize(MachineFunction &MF) { 668c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const MachineFrameInfo *FFI = MF.getFrameInfo(); 669c140c4803dc3e10e08138670829bc0494986abe9David Goodwin int Offset = 0; 670c140c4803dc3e10e08138670829bc0494986abe9David Goodwin for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) { 671c140c4803dc3e10e08138670829bc0494986abe9David Goodwin int FixedOff = -FFI->getObjectOffset(i); 672c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (FixedOff > Offset) Offset = FixedOff; 673c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 674c140c4803dc3e10e08138670829bc0494986abe9David Goodwin for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) { 675c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (FFI->isDeadObjectIndex(i)) 676c140c4803dc3e10e08138670829bc0494986abe9David Goodwin continue; 677c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Offset += FFI->getObjectSize(i); 678c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned Align = FFI->getObjectAlignment(i); 679c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Adjust to alignment boundary 680c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Offset = (Offset+Align-1)/Align*Align; 681c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 682c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return (unsigned)Offset; 683c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 684c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 685542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng/// estimateRSStackSizeLimit - Look at each instruction that references stack 686542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng/// frames and return the stack size limit beyond which some of these 687ce3e769c15be90463abf14bb71b5a8e1205d3661Jim Grosbach/// instructions will require a scratch register during their expansion later. 688ee42fd309ee6a8febfafb97c2f3b6f2069758c5eEvan Chengunsigned 689ee42fd309ee6a8febfafb97c2f3b6f2069758c5eEvan ChengARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const { 690ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 691542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng unsigned Limit = (1 << 12) - 1; 692b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) { 693b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); 694b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner I != E; ++I) { 695b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { 696b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner if (!I->getOperand(i).isFI()) continue; 69752c61ec1640a9fa1cf8c2fde97a14dfbf5e702b7Jakob Stoklund Olesen 69852c61ec1640a9fa1cf8c2fde97a14dfbf5e702b7Jakob Stoklund Olesen // When using ADDri to get the address of a stack object, 255 is the 69952c61ec1640a9fa1cf8c2fde97a14dfbf5e702b7Jakob Stoklund Olesen // largest offset guaranteed to fit in the immediate offset. 70052c61ec1640a9fa1cf8c2fde97a14dfbf5e702b7Jakob Stoklund Olesen if (I->getOpcode() == ARM::ADDri) { 70152c61ec1640a9fa1cf8c2fde97a14dfbf5e702b7Jakob Stoklund Olesen Limit = std::min(Limit, (1U << 8) - 1); 70252c61ec1640a9fa1cf8c2fde97a14dfbf5e702b7Jakob Stoklund Olesen break; 70352c61ec1640a9fa1cf8c2fde97a14dfbf5e702b7Jakob Stoklund Olesen } 70452c61ec1640a9fa1cf8c2fde97a14dfbf5e702b7Jakob Stoklund Olesen 70552c61ec1640a9fa1cf8c2fde97a14dfbf5e702b7Jakob Stoklund Olesen // Otherwise check the addressing mode. 706535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen switch (I->getDesc().TSFlags & ARMII::AddrModeMask) { 707535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen case ARMII::AddrMode3: 708535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen case ARMII::AddrModeT2_i8: 709535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen Limit = std::min(Limit, (1U << 8) - 1); 710535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen break; 711535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen case ARMII::AddrMode5: 712535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen case ARMII::AddrModeT2_i8s4: 713b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner Limit = std::min(Limit, ((1U << 8) - 1) * 4); 714535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen break; 715535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen case ARMII::AddrModeT2_i12: 716ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng // i12 supports only positive offset so these will be converted to 717ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng // i8 opcodes. See llvm::rewriteT2FrameIndex. 718ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (hasFP(MF) && AFI->hasStackFrame()) 719ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng Limit = std::min(Limit, (1U << 8) - 1); 720535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen break; 721535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen case ARMII::AddrMode6: 722535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen // Addressing mode 6 (load/store) instructions can't encode an 723535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen // immediate offset for stack references. 724ce3e769c15be90463abf14bb71b5a8e1205d3661Jim Grosbach return 0; 725535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen default: 726535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen break; 727535af4a320ba169342c87433841dc64fbdcd72b3Jakob Stoklund Olesen } 728b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner break; // At most one FI per instruction 729b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner } 730542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng } 731542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng } 732542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng 733542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng return Limit; 734542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng} 735542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng 7361c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattnerstatic unsigned GetFunctionSizeInBytes(const MachineFunction &MF, 7371c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattner const ARMBaseInstrInfo &TII) { 7381c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattner unsigned FnSize = 0; 7391c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattner for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end(); 7401c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattner MBBI != E; ++MBBI) { 7411c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattner const MachineBasicBlock &MBB = *MBBI; 7421c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattner for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end(); 7431c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattner I != E; ++I) 7441c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattner FnSize += TII.GetInstSizeInBytes(I); 7451c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattner } 7461c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattner return FnSize; 7471c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattner} 7481c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattner 749c140c4803dc3e10e08138670829bc0494986abe9David Goodwinvoid 750c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 7519631864688c593711f82bb8d21f8b724c628d786Jim Grosbach RegScavenger *RS) const { 752c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // This tells PEI to spill the FP as if it is any other callee-save register 753c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // to take advantage the eliminateFrameIndex machinery. This also ensures it 754c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // is spilled in the order specified by getCalleeSavedRegs() to make it easier 755c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // to combine multiple loads / stores. 756c140c4803dc3e10e08138670829bc0494986abe9David Goodwin bool CanEliminateFrame = true; 757c140c4803dc3e10e08138670829bc0494986abe9David Goodwin bool CS1Spilled = false; 758c140c4803dc3e10e08138670829bc0494986abe9David Goodwin bool LRSpilled = false; 759c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned NumGPRSpills = 0; 760c140c4803dc3e10e08138670829bc0494986abe9David Goodwin SmallVector<unsigned, 4> UnspilledCS1GPRs; 761c140c4803dc3e10e08138670829bc0494986abe9David Goodwin SmallVector<unsigned, 4> UnspilledCS2GPRs; 762c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 7636c7d3a16b3321c527e35322e869c73d47dba719dJim Grosbach MachineFrameInfo *MFI = MF.getFrameInfo(); 764c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 7657cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov // Spill R4 if Thumb2 function requires stack realignment - it will be used as 7667cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov // scratch register. 7677cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov // FIXME: It will be better just to find spare register here. 7687cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov if (needsStackRealignment(MF) && 7697cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov AFI->isThumb2Function()) 7707cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov MF.getRegInfo().setPhysRegUsed(ARM::R4); 7717cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov 772f49be7c96f5a57ba67e6b1dc4362273b5f7cbd81Jim Grosbach // Spill LR if Thumb1 function uses variable length argument lists. 773f49be7c96f5a57ba67e6b1dc4362273b5f7cbd81Jim Grosbach if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0) 774f49be7c96f5a57ba67e6b1dc4362273b5f7cbd81Jim Grosbach MF.getRegInfo().setPhysRegUsed(ARM::LR); 775f49be7c96f5a57ba67e6b1dc4362273b5f7cbd81Jim Grosbach 776c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Don't spill FP if the frame can be eliminated. This is determined 777c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // by scanning the callee-save registers to see if any is used. 778c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const unsigned *CSRegs = getCalleeSavedRegs(); 779c140c4803dc3e10e08138670829bc0494986abe9David Goodwin for (unsigned i = 0; CSRegs[i]; ++i) { 780c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned Reg = CSRegs[i]; 781c140c4803dc3e10e08138670829bc0494986abe9David Goodwin bool Spilled = false; 782c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (MF.getRegInfo().isPhysRegUsed(Reg)) { 783c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setCSRegisterIsSpilled(Reg); 784c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Spilled = true; 785c140c4803dc3e10e08138670829bc0494986abe9David Goodwin CanEliminateFrame = false; 786c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else { 787c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Check alias registers too. 788c140c4803dc3e10e08138670829bc0494986abe9David Goodwin for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { 789c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (MF.getRegInfo().isPhysRegUsed(*Aliases)) { 790c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Spilled = true; 791c140c4803dc3e10e08138670829bc0494986abe9David Goodwin CanEliminateFrame = false; 792c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 793c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 794c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 795c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 79620fae651816916000c47b78843f22fd259ba4216Rafael Espindola if (!ARM::GPRRegisterClass->contains(Reg)) 79720fae651816916000c47b78843f22fd259ba4216Rafael Espindola continue; 798c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 79920fae651816916000c47b78843f22fd259ba4216Rafael Espindola if (Spilled) { 80020fae651816916000c47b78843f22fd259ba4216Rafael Espindola NumGPRSpills++; 801c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 80220fae651816916000c47b78843f22fd259ba4216Rafael Espindola if (!STI.isTargetDarwin()) { 80320fae651816916000c47b78843f22fd259ba4216Rafael Espindola if (Reg == ARM::LR) 804c140c4803dc3e10e08138670829bc0494986abe9David Goodwin LRSpilled = true; 80520fae651816916000c47b78843f22fd259ba4216Rafael Espindola CS1Spilled = true; 80620fae651816916000c47b78843f22fd259ba4216Rafael Espindola continue; 80720fae651816916000c47b78843f22fd259ba4216Rafael Espindola } 808c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 80920fae651816916000c47b78843f22fd259ba4216Rafael Espindola // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 81020fae651816916000c47b78843f22fd259ba4216Rafael Espindola switch (Reg) { 81120fae651816916000c47b78843f22fd259ba4216Rafael Espindola case ARM::LR: 81220fae651816916000c47b78843f22fd259ba4216Rafael Espindola LRSpilled = true; 81320fae651816916000c47b78843f22fd259ba4216Rafael Espindola // Fallthrough 81420fae651816916000c47b78843f22fd259ba4216Rafael Espindola case ARM::R4: 81520fae651816916000c47b78843f22fd259ba4216Rafael Espindola case ARM::R5: 81620fae651816916000c47b78843f22fd259ba4216Rafael Espindola case ARM::R6: 81720fae651816916000c47b78843f22fd259ba4216Rafael Espindola case ARM::R7: 81820fae651816916000c47b78843f22fd259ba4216Rafael Espindola CS1Spilled = true; 81920fae651816916000c47b78843f22fd259ba4216Rafael Espindola break; 82020fae651816916000c47b78843f22fd259ba4216Rafael Espindola default: 82120fae651816916000c47b78843f22fd259ba4216Rafael Espindola break; 82220fae651816916000c47b78843f22fd259ba4216Rafael Espindola } 82320fae651816916000c47b78843f22fd259ba4216Rafael Espindola } else { 82420fae651816916000c47b78843f22fd259ba4216Rafael Espindola if (!STI.isTargetDarwin()) { 82520fae651816916000c47b78843f22fd259ba4216Rafael Espindola UnspilledCS1GPRs.push_back(Reg); 82620fae651816916000c47b78843f22fd259ba4216Rafael Espindola continue; 82720fae651816916000c47b78843f22fd259ba4216Rafael Espindola } 82820fae651816916000c47b78843f22fd259ba4216Rafael Espindola 82920fae651816916000c47b78843f22fd259ba4216Rafael Espindola switch (Reg) { 83020fae651816916000c47b78843f22fd259ba4216Rafael Espindola case ARM::R4: 83120fae651816916000c47b78843f22fd259ba4216Rafael Espindola case ARM::R5: 83220fae651816916000c47b78843f22fd259ba4216Rafael Espindola case ARM::R6: 83320fae651816916000c47b78843f22fd259ba4216Rafael Espindola case ARM::R7: 83420fae651816916000c47b78843f22fd259ba4216Rafael Espindola case ARM::LR: 83520fae651816916000c47b78843f22fd259ba4216Rafael Espindola UnspilledCS1GPRs.push_back(Reg); 83620fae651816916000c47b78843f22fd259ba4216Rafael Espindola break; 83720fae651816916000c47b78843f22fd259ba4216Rafael Espindola default: 83820fae651816916000c47b78843f22fd259ba4216Rafael Espindola UnspilledCS2GPRs.push_back(Reg); 83920fae651816916000c47b78843f22fd259ba4216Rafael Espindola break; 840c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 841c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 842c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 843c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 844c140c4803dc3e10e08138670829bc0494986abe9David Goodwin bool ForceLRSpill = false; 845f1daf7d8abebd6e0104a6b41a774ccbb19a51c60David Goodwin if (!LRSpilled && AFI->isThumb1OnlyFunction()) { 8461c55386dae428d076bd7d054ed8bbb59c4ba954eChris Lattner unsigned FnSize = GetFunctionSizeInBytes(MF, TII); 847c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Force LR to be spilled if the Thumb function size is > 2048. This enables 848c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // use of BL to implement far jump. If it turns out that it's not needed 849c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // then the branch fix up path will undo it. 850c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (FnSize >= (1 << 11)) { 851c140c4803dc3e10e08138670829bc0494986abe9David Goodwin CanEliminateFrame = false; 852c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ForceLRSpill = true; 853c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 854c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 855c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 856657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen // If any of the stack slot references may be out of range of an immediate 857657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen // offset, make sure a register (or a spill slot) is available for the 858657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen // register scavenger. Note that if we're indexing off the frame pointer, the 859657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen // effective stack size is 4 bytes larger since the FP points to the stack 8606c7d3a16b3321c527e35322e869c73d47dba719dJim Grosbach // slot of the previous FP. Also, if we have variable sized objects in the 8616c7d3a16b3321c527e35322e869c73d47dba719dJim Grosbach // function, stack slot references will often be negative, and some of 8626c7d3a16b3321c527e35322e869c73d47dba719dJim Grosbach // our instructions are positive-offset only, so conservatively consider 863abf7bdffd67689781a5104b13fa806b92f3e96e1Jim Grosbach // that case to want a spill slot (or register) as well. Similarly, if 864abf7bdffd67689781a5104b13fa806b92f3e96e1Jim Grosbach // the function adjusts the stack pointer during execution and the 865abf7bdffd67689781a5104b13fa806b92f3e96e1Jim Grosbach // adjustments aren't already part of our stack size estimate, our offset 866abf7bdffd67689781a5104b13fa806b92f3e96e1Jim Grosbach // calculations may be off, so be conservative. 8676c7d3a16b3321c527e35322e869c73d47dba719dJim Grosbach // FIXME: We could add logic to be more precise about negative offsets 8686c7d3a16b3321c527e35322e869c73d47dba719dJim Grosbach // and which instructions will need a scratch register for them. Is it 8696c7d3a16b3321c527e35322e869c73d47dba719dJim Grosbach // worth the effort and added fragility? 87068eec39bca280f98bef1256a5e89531ac1a77d1aChandler Carruth bool BigStack = 871ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng (RS && 872ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng (estimateStackSize(MF) + ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >= 873ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng estimateRSStackSizeLimit(MF))) 874a7da3ac14ab1ca6da52547baf572d29c066559ccChandler Carruth || MFI->hasVarSizedObjects() 875a7da3ac14ab1ca6da52547baf572d29c066559ccChandler Carruth || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF)); 876657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen 877c140c4803dc3e10e08138670829bc0494986abe9David Goodwin bool ExtraCSSpill = false; 878657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) { 879c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setHasStackFrame(true); 880c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 881c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 882c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 883c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!LRSpilled && CS1Spilled) { 884c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MF.getRegInfo().setPhysRegUsed(ARM::LR); 885c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setCSRegisterIsSpilled(ARM::LR); 886c140c4803dc3e10e08138670829bc0494986abe9David Goodwin NumGPRSpills++; 887c140c4803dc3e10e08138670829bc0494986abe9David Goodwin UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 888c140c4803dc3e10e08138670829bc0494986abe9David Goodwin UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 889c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ForceLRSpill = false; 890c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ExtraCSSpill = true; 891c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 892c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 893ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (hasFP(MF)) { 894c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MF.getRegInfo().setPhysRegUsed(FramePtr); 895c140c4803dc3e10e08138670829bc0494986abe9David Goodwin NumGPRSpills++; 896c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 897c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 898c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // If stack and double are 8-byte aligned and we are spilling an odd number 899c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // of GPRs. Spill one extra callee save GPR so we won't have to pad between 900c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // the integer and double callee save areas. 901c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 902c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (TargetAlign == 8 && (NumGPRSpills & 1)) { 903c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (CS1Spilled && !UnspilledCS1GPRs.empty()) { 904c140c4803dc3e10e08138670829bc0494986abe9David Goodwin for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { 905c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned Reg = UnspilledCS1GPRs[i]; 906f1daf7d8abebd6e0104a6b41a774ccbb19a51c60David Goodwin // Don't spill high register if the function is thumb1 907f1daf7d8abebd6e0104a6b41a774ccbb19a51c60David Goodwin if (!AFI->isThumb1OnlyFunction() || 908c140c4803dc3e10e08138670829bc0494986abe9David Goodwin isARMLowRegister(Reg) || Reg == ARM::LR) { 909c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MF.getRegInfo().setPhysRegUsed(Reg); 910c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setCSRegisterIsSpilled(Reg); 911c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!isReservedReg(MF, Reg)) 912c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ExtraCSSpill = true; 913c140c4803dc3e10e08138670829bc0494986abe9David Goodwin break; 914c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 915c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 916c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else if (!UnspilledCS2GPRs.empty() && 917f1daf7d8abebd6e0104a6b41a774ccbb19a51c60David Goodwin !AFI->isThumb1OnlyFunction()) { 918c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned Reg = UnspilledCS2GPRs.front(); 919c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MF.getRegInfo().setPhysRegUsed(Reg); 920c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setCSRegisterIsSpilled(Reg); 921c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!isReservedReg(MF, Reg)) 922c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ExtraCSSpill = true; 923c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 924c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 925c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 926c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Estimate if we might need to scavenge a register at some point in order 927c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // to materialize a stack offset. If so, either spill one additional 928c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // callee-saved register or reserve a special spill slot to facilitate 9293d6cb88a64fe67064de206405951eb326d86fc0cJim Grosbach // register scavenging. Thumb1 needs a spill slot for stack pointer 9303d6cb88a64fe67064de206405951eb326d86fc0cJim Grosbach // adjustments also, even when the frame itself is small. 931657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen if (BigStack && !ExtraCSSpill) { 932657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen // If any non-reserved CS register isn't spilled, just spill one or two 933657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen // extra. That should take care of it! 934657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen unsigned NumExtras = TargetAlign / 4; 935657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen SmallVector<unsigned, 2> Extras; 936657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen while (NumExtras && !UnspilledCS1GPRs.empty()) { 937657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen unsigned Reg = UnspilledCS1GPRs.back(); 938657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen UnspilledCS1GPRs.pop_back(); 9391190c14b547a1e275e80e43a6ad52178312adbd7Bob Wilson if (!isReservedReg(MF, Reg) && 9401190c14b547a1e275e80e43a6ad52178312adbd7Bob Wilson (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) || 9411190c14b547a1e275e80e43a6ad52178312adbd7Bob Wilson Reg == ARM::LR)) { 942657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen Extras.push_back(Reg); 943657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen NumExtras--; 944657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen } 945657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen } 946657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen // For non-Thumb1 functions, also check for hi-reg CS registers 947657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen if (!AFI->isThumb1OnlyFunction()) { 948657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen while (NumExtras && !UnspilledCS2GPRs.empty()) { 949657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen unsigned Reg = UnspilledCS2GPRs.back(); 950657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen UnspilledCS2GPRs.pop_back(); 951c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!isReservedReg(MF, Reg)) { 952c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Extras.push_back(Reg); 953c140c4803dc3e10e08138670829bc0494986abe9David Goodwin NumExtras--; 954c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 955c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 956657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen } 957657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen if (Extras.size() && NumExtras == 0) { 958657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen for (unsigned i = 0, e = Extras.size(); i != e; ++i) { 959657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen MF.getRegInfo().setPhysRegUsed(Extras[i]); 960657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen AFI->setCSRegisterIsSpilled(Extras[i]); 961c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 962657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen } else if (!AFI->isThumb1OnlyFunction()) { 963657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen // note: Thumb1 functions spill to R12, not the stack. Reserve a slot 964657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen // closest to SP or frame pointer. 965657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen const TargetRegisterClass *RC = ARM::GPRRegisterClass; 966657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 967657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen RC->getAlignment(), 968657baec0af38d84e24e4738b0696bb99d1517179Jakob Stoklund Olesen false)); 969c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 970c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 971c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 972c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 973c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (ForceLRSpill) { 974c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MF.getRegInfo().setPhysRegUsed(ARM::LR); 975c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setCSRegisterIsSpilled(ARM::LR); 976c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setLRIsSpilledForFarJump(true); 977c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 978c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 979c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 980c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getRARegister() const { 981c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::LR; 982c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 983c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 9843f2bf85d14759cc4b28a86805f566ac805a54d00David Greeneunsigned 9853f2bf85d14759cc4b28a86805f566ac805a54d00David GreeneARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 986ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (hasFP(MF)) 987c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return FramePtr; 988c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::SP; 989c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 990c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 991e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach// Provide a base+offset reference to an FI slot for debug info. It's the 992e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach// same as what we use for resolving the code-gen references for now. 993e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach// FIXME: This can go wrong when references are SP-relative and simple call 994e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach// frames aren't used. 99550f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbachint 99630c6b75ac2eef548c18110a38c9798ea5314cabaChris LattnerARMBaseRegisterInfo::getFrameIndexReference(const MachineFunction &MF, int FI, 99750f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach unsigned &FrameReg) const { 998e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach return ResolveFrameIndexReference(MF, FI, FrameReg, 0); 999e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach} 1000e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach 1001e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbachint 1002e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim GrosbachARMBaseRegisterInfo::ResolveFrameIndexReference(const MachineFunction &MF, 1003e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach int FI, 1004e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach unsigned &FrameReg, 1005e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach int SPAdj) const { 100650f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach const MachineFrameInfo *MFI = MF.getFrameInfo(); 100730c6b75ac2eef548c18110a38c9798ea5314cabaChris Lattner const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 100850f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize(); 1009e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach int FPOffset = Offset - AFI->getFramePtrSpillOffset(); 101050f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach bool isFixed = MFI->isFixedObjectIndex(FI); 101150f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach 1012a37aa546224ec03ba1f1a1598e0781af4b692673Jim Grosbach FrameReg = ARM::SP; 1013e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach Offset += SPAdj; 101450f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach if (AFI->isGPRCalleeSavedArea1Frame(FI)) 1015e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach return Offset - AFI->getGPRCalleeSavedArea1Offset(); 101650f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach else if (AFI->isGPRCalleeSavedArea2Frame(FI)) 1017e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach return Offset - AFI->getGPRCalleeSavedArea2Offset(); 101850f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach else if (AFI->isDPRCalleeSavedAreaFrame(FI)) 1019e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach return Offset - AFI->getDPRCalleeSavedAreaOffset(); 1020e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach 1021e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach // When dynamically realigning the stack, use the frame pointer for 1022e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach // parameters, and the stack pointer for locals. 1023e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach if (needsStackRealignment(MF)) { 102450f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach assert (hasFP(MF) && "dynamic stack realignment without a FP!"); 102550f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach if (isFixed) { 102650f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach FrameReg = getFrameRegister(MF); 1027e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach Offset = FPOffset; 102850f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach } 1029e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach return Offset; 1030e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach } 1031e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach 1032e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach // If there is a frame pointer, use it when we can. 1033e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach if (hasFP(MF) && AFI->hasStackFrame()) { 1034e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach // Use frame pointer to reference fixed objects. Use it for locals if 1035e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach // there are VLAs (and thus the SP isn't reliable as a base). 103650f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach if (isFixed || MFI->hasVarSizedObjects()) { 103750f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach FrameReg = getFrameRegister(MF); 1038e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach Offset = FPOffset; 103950f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach } else if (AFI->isThumb2Function()) { 1040e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach // In Thumb2 mode, the negative offset is very limited. Try to avoid 1041e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach // out of range references. 104250f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach if (FPOffset >= -255 && FPOffset < 0) { 104350f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach FrameReg = getFrameRegister(MF); 104450f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach Offset = FPOffset; 104550f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach } 1046e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) { 1047e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach // Otherwise, use SP or FP, whichever is closer to the stack slot. 1048e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach FrameReg = getFrameRegister(MF); 1049e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach Offset = FPOffset; 105050f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach } 105150f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach } 105250f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach return Offset; 105350f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach} 105450f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach 105550f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbachint 105630c6b75ac2eef548c18110a38c9798ea5314cabaChris LattnerARMBaseRegisterInfo::getFrameIndexOffset(const MachineFunction &MF, 105730c6b75ac2eef548c18110a38c9798ea5314cabaChris Lattner int FI) const { 105850f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach unsigned FrameReg; 105950f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach return getFrameIndexReference(MF, FI, FrameReg); 106050f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach} 106150f8516d2dd87e6c02a46fa349b75101f9db8619Jim Grosbach 1062c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { 1063c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("What is the exception register"); 1064c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 1065c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 1066c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1067c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { 1068c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("What is the exception handler register"); 1069c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 1070c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 1071c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1072c140c4803dc3e10e08138670829bc0494986abe9David Goodwinint ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 1073c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 1074c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 1075c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1076c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg, 10779631864688c593711f82bb8d21f8b724c628d786Jim Grosbach const MachineFunction &MF) const { 1078c140c4803dc3e10e08138670829bc0494986abe9David Goodwin switch (Reg) { 1079c140c4803dc3e10e08138670829bc0494986abe9David Goodwin default: break; 1080c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Return 0 if either register of the pair is a special register. 1081c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // So no R12, etc. 1082c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R1: 1083c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::R0; 1084c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R3: 10856009751244909c277e6cee8e74a4ccf1846953bcJim Grosbach return ARM::R2; 1086c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R5: 1087c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::R4; 1088c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R7: 1089c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6; 1090c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R9: 1091c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8; 1092c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R11: 1093c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10; 1094c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1095c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S1: 1096c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S0; 1097c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S3: 1098c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S2; 1099c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S5: 1100c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S4; 1101c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S7: 1102c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S6; 1103c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S9: 1104c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S8; 1105c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S11: 1106c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S10; 1107c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S13: 1108c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S12; 1109c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S15: 1110c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S14; 1111c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S17: 1112c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S16; 1113c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S19: 1114c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S18; 1115c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S21: 1116c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S20; 1117c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S23: 1118c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S22; 1119c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S25: 1120c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S24; 1121c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S27: 1122c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S26; 1123c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S29: 1124c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S28; 1125c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S31: 1126c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S30; 1127c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1128c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D1: 1129c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D0; 1130c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D3: 1131c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D2; 1132c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D5: 1133c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D4; 1134c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D7: 1135c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D6; 1136c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D9: 1137c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D8; 1138c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D11: 1139c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D10; 1140c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D13: 1141c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D12; 1142c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D15: 1143c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D14; 11448295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D17: 11458295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D16; 11468295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D19: 11478295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D18; 11488295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D21: 11498295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D20; 11508295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D23: 11518295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D22; 11528295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D25: 11538295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D24; 11548295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D27: 11558295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D26; 11568295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D29: 11578295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D28; 11588295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D31: 11598295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D30; 1160c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 1161c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1162c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 1163c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 1164c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1165c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg, 1166c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const MachineFunction &MF) const { 1167c140c4803dc3e10e08138670829bc0494986abe9David Goodwin switch (Reg) { 1168c140c4803dc3e10e08138670829bc0494986abe9David Goodwin default: break; 1169c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Return 0 if either register of the pair is a special register. 1170c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // So no R12, etc. 1171c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R0: 1172c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::R1; 1173c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R2: 11746009751244909c277e6cee8e74a4ccf1846953bcJim Grosbach return ARM::R3; 1175c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R4: 1176c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::R5; 1177c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R6: 1178c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7; 1179c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R8: 1180c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9; 1181c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R10: 1182c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11; 1183c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1184c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S0: 1185c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S1; 1186c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S2: 1187c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S3; 1188c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S4: 1189c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S5; 1190c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S6: 1191c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S7; 1192c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S8: 1193c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S9; 1194c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S10: 1195c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S11; 1196c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S12: 1197c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S13; 1198c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S14: 1199c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S15; 1200c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S16: 1201c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S17; 1202c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S18: 1203c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S19; 1204c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S20: 1205c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S21; 1206c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S22: 1207c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S23; 1208c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S24: 1209c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S25; 1210c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S26: 1211c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S27; 1212c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S28: 1213c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S29; 1214c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S30: 1215c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S31; 1216c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1217c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D0: 1218c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D1; 1219c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D2: 1220c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D3; 1221c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D4: 1222c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D5; 1223c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D6: 1224c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D7; 1225c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D8: 1226c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D9; 1227c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D10: 1228c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D11; 1229c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D12: 1230c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D13; 1231c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D14: 1232c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D15; 12338295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D16: 12348295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D17; 12358295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D18: 12368295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D19; 12378295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D20: 12388295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D21; 12398295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D22: 12408295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D23; 12418295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D24: 12428295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D25; 12438295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D26: 12448295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D27; 12458295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D28: 12468295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D29; 12478295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D30: 12488295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D31; 1249c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 1250c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1251c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 1252c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 1253c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1254db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// emitLoadConstPool - Emits a load from constpool to materialize the 1255db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// specified immediate. 1256db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinvoid ARMBaseRegisterInfo:: 1257db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinemitLoadConstPool(MachineBasicBlock &MBB, 1258db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock::iterator &MBBI, 125977521f5232e679aa3de10aaaed2464aa91d7ff55David Goodwin DebugLoc dl, 1260378445303b10b092a898a75131141a8259cff50bEvan Cheng unsigned DestReg, unsigned SubIdx, int Val, 1261db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMCC::CondCodes Pred, 1262db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned PredReg) const { 1263db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineFunction &MF = *MBB.getParent(); 1264db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineConstantPool *ConstantPool = MF.getConstantPool(); 126546510a73e977273ec67747eb34cbdb43f815e451Dan Gohman const Constant *C = 12661d0be15f89cb5056e20e2d24faa8d6afb1573bcaOwen Anderson ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); 1267db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 1268db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1269378445303b10b092a898a75131141a8259cff50bEvan Cheng BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 1270378445303b10b092a898a75131141a8259cff50bEvan Cheng .addReg(DestReg, getDefRegState(true), SubIdx) 1271db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin .addConstantPoolIndex(Idx) 1272db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin .addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 1273db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1274db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1275db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinbool ARMBaseRegisterInfo:: 1276db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinrequiresRegisterScavenging(const MachineFunction &MF) const { 1277db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return true; 1278db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 127941fff8c19ab6d8e28f5362481c184ad628f8c704Jim Grosbach 12807e831db1d4f5dc51ca6526739cf41e59895c5c20Jim Grosbachbool ARMBaseRegisterInfo:: 12817e831db1d4f5dc51ca6526739cf41e59895c5c20Jim GrosbachrequiresFrameIndexScavenging(const MachineFunction &MF) const { 1282ca5dfb71ba4aa4a8392a021ec056cf0b70f74f1eJim Grosbach return true; 12837e831db1d4f5dc51ca6526739cf41e59895c5c20Jim Grosbach} 1284db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1285db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin// hasReservedCallFrame - Under normal circumstances, when a frame pointer is 1286db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin// not required, we reserve argument space for call sites in the function 1287db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin// immediately on entry to the current function. This eliminates the need for 1288db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin// add/sub sp brackets around call sites. Returns true if the call frame is 1289db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin// included as part of the stack frame. 1290db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinbool ARMBaseRegisterInfo:: 129172852a8cfb605056d87b644d2e36b1346051413dEric ChristopherhasReservedCallFrame(const MachineFunction &MF) const { 1292db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin const MachineFrameInfo *FFI = MF.getFrameInfo(); 1293db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned CFSize = FFI->getMaxCallFrameSize(); 1294db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // It's not always a good idea to include the call frame as part of the 1295db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // stack frame. ARM (especially Thumb) has small immediate offset to 1296db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // address the stack frame. So a large call frame can cause poor codegen 1297db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // and may even makes it impossible to scavenge a register. 1298db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12 1299db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return false; 1300db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1301db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return !MF.getFrameInfo()->hasVarSizedObjects(); 1302db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1303db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 13044642ad3af1cf508ac320b9afd25b065f08b36574Jim Grosbach// canSimplifyCallFramePseudos - If there is a reserved call frame, the 13054642ad3af1cf508ac320b9afd25b065f08b36574Jim Grosbach// call frame pseudos can be simplified. Unlike most targets, having a FP 13064642ad3af1cf508ac320b9afd25b065f08b36574Jim Grosbach// is not sufficient here since we still may reference some objects via SP 13074642ad3af1cf508ac320b9afd25b065f08b36574Jim Grosbach// even when FP is available in Thumb2 mode. 13084642ad3af1cf508ac320b9afd25b065f08b36574Jim Grosbachbool ARMBaseRegisterInfo:: 130972852a8cfb605056d87b644d2e36b1346051413dEric ChristophercanSimplifyCallFramePseudos(const MachineFunction &MF) const { 13105f366af2ff36cc65fe4964194b07bf1455828ff0Jim Grosbach return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects(); 13114642ad3af1cf508ac320b9afd25b065f08b36574Jim Grosbach} 13124642ad3af1cf508ac320b9afd25b065f08b36574Jim Grosbach 1313db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinstatic void 13146495f63945e8dbde81f03a1dc2ab421993b9a495Evan ChengemitSPUpdate(bool isARM, 13156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 13166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng DebugLoc dl, const ARMBaseInstrInfo &TII, 1317db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin int NumBytes, 1318db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { 13196495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isARM) 13206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 13216495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Pred, PredReg, TII); 13226495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng else 13236495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 13246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Pred, PredReg, TII); 1325db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1326db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 13276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1328db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinvoid ARMBaseRegisterInfo:: 1329db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwineliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 1330db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock::iterator I) const { 1331db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (!hasReservedCallFrame(MF)) { 1332db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // If we have alloca, convert as follows: 1333db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // ADJCALLSTACKDOWN -> sub, sp, sp, amount 1334db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // ADJCALLSTACKUP -> add, sp, sp, amount 1335db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineInstr *Old = I; 1336db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin DebugLoc dl = Old->getDebugLoc(); 1337db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Amount = Old->getOperand(0).getImm(); 1338db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Amount != 0) { 1339db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // We need to keep the stack aligned properly. To do this, we round the 1340db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // amount of space needed for the outgoing arguments up to the next 1341db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // alignment boundary. 1342db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 1343db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin Amount = (Amount+Align-1)/Align*Align; 1344db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 13456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 13466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(!AFI->isThumb1OnlyFunction() && 1347cf453ee70a1ae03cc641686fd5db0f8a7d8ce250Jim Grosbach "This eliminateCallFramePseudoInstr does not support Thumb1!"); 13486495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isARM = !AFI->isThumbFunction(); 13496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1350db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Replace the pseudo instruction with a new instruction... 1351db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Opc = Old->getOpcode(); 13524c7628e43d8468f215ea345545479b6d728cee92Jim Grosbach int PIdx = Old->findFirstPredOperandIdx(); 13534c7628e43d8468f215ea345545479b6d728cee92Jim Grosbach ARMCC::CondCodes Pred = (PIdx == -1) 13544c7628e43d8468f215ea345545479b6d728cee92Jim Grosbach ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm(); 1355db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 1356db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. 1357db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned PredReg = Old->getOperand(2).getReg(); 13586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg); 1359db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } else { 1360db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Note: PredReg is operand 3 for ADJCALLSTACKUP. 1361db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned PredReg = Old->getOperand(3).getReg(); 1362db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 13636495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg); 1364db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1365db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1366db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1367db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MBB.erase(I); 1368db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1369db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 13708708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// needsFrameBaseReg - Returns true if the instruction's frame index 13718708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// reference would be better served by a base register other than FP 13728708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// or SP. Used by LocalStackFrameAllocation to determine which frame index 13738708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// references it should create new base registers for. 13748708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbachbool ARMBaseRegisterInfo:: 13758708ead5a46f4ec8f2d5f832be23381924d72b8dJim GrosbachneedsFrameBaseReg(MachineInstr *MI, unsigned operand) const { 13768708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach assert (MI->getOperand(operand).isFI() && 13778708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach "needsFrameBaseReg() called on non Frame Index operand!"); 13788708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 13798708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // It's the load/store FI references that cause issues, as it can be difficult 13808708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // to materialize the offset if it won't fit in the literal field. Estimate 13818708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // based on the size of the local frame and some conservative assumptions 13828708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // about the rest of the stack frame (note, this is pre-regalloc, so 13838708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // we don't know everything for certain yet) whether this offset is likely 13848708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // to be out of range of the immediate. Return true if so. 13858708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 13868708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // FIXME: For testing, return true for all loads/stores and false for 13878708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // everything else. We want to create lots of base regs to shake out bugs. 13888708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // 13898708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // FIXME: This is Thumb2/ARM only for now to keep it simpler. 13908708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach ARMFunctionInfo *AFI = 13918708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach MI->getParent()->getParent()->getInfo<ARMFunctionInfo>(); 13928708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach if (AFI->isThumb1OnlyFunction()) 13938708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach return false; 13948708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 13958708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach unsigned Opc = MI->getOpcode(); 13968708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 13978708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach switch (Opc) { 13988708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach case ARM::LDR: case ARM::LDRH: case ARM::LDRB: 13998708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach case ARM::STR: case ARM::STRH: case ARM::STRB: 14008708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach case ARM::t2LDRi12: case ARM::t2LDRi8: 14018708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach case ARM::t2STRi12: case ARM::t2STRi8: 14028708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach case ARM::VLDRS: case ARM::VLDRD: 14038708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach case ARM::VSTRS: case ARM::VSTRD: 14048708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach return true; 14058708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach default: 14068708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach return false; 14078708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach } 14088708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach} 14098708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 14108708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 1411b58f498f7502e7e1833decbbbb4df771367c7341Jim Grosbachunsigned 14126495f63945e8dbde81f03a1dc2ab421993b9a495Evan ChengARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 1413dff4b4c5a7cc894d3b4b6c6e779ea8f47fa50630Jim Grosbach int SPAdj, FrameIndexValue *Value, 1414b58f498f7502e7e1833decbbbb4df771367c7341Jim Grosbach RegScavenger *RS) const { 14155ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin unsigned i = 0; 14165ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MachineInstr &MI = *II; 14175ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MachineBasicBlock &MBB = *MI.getParent(); 14185ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MachineFunction &MF = *MBB.getParent(); 14195ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 14206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(!AFI->isThumb1OnlyFunction() && 1421a15de00f8246f19180b26ee5fe7ff8f436e0de08Bob Wilson "This eliminateFrameIndex does not support Thumb1!"); 14225ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 14235ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin while (!MI.getOperand(i).isFI()) { 14245ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin ++i; 14255ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 14265ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin } 14275ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 14285ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin int FrameIndex = MI.getOperand(i).getIndex(); 1429a37aa546224ec03ba1f1a1598e0781af4b692673Jim Grosbach unsigned FrameReg; 14305ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 1431e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09Jim Grosbach int Offset = ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); 14325ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 143362b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng // Special handling of dbg_value instructions. 143462b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng if (MI.isDebugValue()) { 143562b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/); 143662b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng MI.getOperand(i+1).ChangeToImmediate(Offset); 143762b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng return 0; 143862b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng } 143962b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng 144048d8afab73d72418cf9505a020f621014920463cEvan Cheng // Modify MI as necessary to handle as much of 'Offset' as possible 1441cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng bool Done = false; 14426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (!AFI->isThumbFunction()) 1443cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII); 14446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng else { 14456495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(AFI->isThumb2Function()); 1446cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII); 14476495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1448cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng if (Done) 1449b58f498f7502e7e1833decbbbb4df771367c7341Jim Grosbach return 0; 14505ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 1451db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // If we get here, the immediate doesn't fit into the instruction. We folded 1452db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // as much as possible above, handle the rest, providing a register that is 1453db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // SP+LargeImm. 145419bb87d0f80f3e6eed38a9fa267bf2b0474aeaabDaniel Dunbar assert((Offset || 1455a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || 1456a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && 1457cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng "This code isn't needed if offset already handled!"); 1458db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 14597e831db1d4f5dc51ca6526739cf41e59895c5c20Jim Grosbach unsigned ScratchReg = 0; 1460db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin int PIdx = MI.findFirstPredOperandIdx(); 1461db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMCC::CondCodes Pred = (PIdx == -1) 1462db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 1463db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 1464cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng if (Offset == 0) 1465a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach // Must be addrmode4/6. 1466cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false); 14676495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng else { 1468ca5dfb71ba4aa4a8392a021ec056cf0b70f74f1eJim Grosbach ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass); 1469dff4b4c5a7cc894d3b4b6c6e779ea8f47fa50630Jim Grosbach if (Value) { 1470dff4b4c5a7cc894d3b4b6c6e779ea8f47fa50630Jim Grosbach Value->first = FrameReg; // use the frame register as a kind indicator 1471dff4b4c5a7cc894d3b4b6c6e779ea8f47fa50630Jim Grosbach Value->second = Offset; 1472dff4b4c5a7cc894d3b4b6c6e779ea8f47fa50630Jim Grosbach } 1473cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng if (!AFI->isThumbFunction()) 1474cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1475cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset, Pred, PredReg, TII); 1476cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng else { 1477cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng assert(AFI->isThumb2Function()); 1478cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1479cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset, Pred, PredReg, TII); 1480cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng } 1481cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); 1482ca5dfb71ba4aa4a8392a021ec056cf0b70f74f1eJim Grosbach if (!ReuseFrameIndexVals) 148318ed9c9a2bd7f1f56129495b499264c58b5cc4f4Jim Grosbach ScratchReg = 0; 14846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 14857e831db1d4f5dc51ca6526739cf41e59895c5c20Jim Grosbach return ScratchReg; 1486db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1487db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 14884371cda7f8fc21fc3192ead122ba48b0152fb0e4Jim Grosbach/// Move iterator past the next bunch of callee save load / store ops for 1489db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// the particular spill area (1: integer area 1, 2: integer area 2, 1490db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// 3: fp area, 0: don't care). 1491db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinstatic void movePastCSLoadStoreOps(MachineBasicBlock &MBB, 1492db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock::iterator &MBBI, 14935ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin int Opc1, int Opc2, unsigned Area, 1494db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin const ARMSubtarget &STI) { 1495db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin while (MBBI != MBB.end() && 14965ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) && 14975ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MBBI->getOperand(1).isFI()) { 1498db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Area != 0) { 1499db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin bool Done = false; 1500db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Category = 0; 1501db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin switch (MBBI->getOperand(0).getReg()) { 1502db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: 1503db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::LR: 1504db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin Category = 1; 1505db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1506db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 1507db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin Category = STI.isTargetDarwin() ? 2 : 1; 1508db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1509db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: 1510db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: 1511db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin Category = 3; 1512db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1513db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin default: 1514db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin Done = true; 1515db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1516db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1517db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Done || Category != Area) 1518db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1519db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1520db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1521db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ++MBBI; 1522db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1523db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1524db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1525db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinvoid ARMBaseRegisterInfo:: 1526db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinemitPrologue(MachineFunction &MF) const { 1527db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock &MBB = MF.front(); 1528db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock::iterator MBBI = MBB.begin(); 1529db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineFrameInfo *MFI = MF.getFrameInfo(); 1530db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 15316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(!AFI->isThumb1OnlyFunction() && 1532cf453ee70a1ae03cc641686fd5db0f8a7d8ce250Jim Grosbach "This emitPrologue does not support Thumb1!"); 15336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isARM = !AFI->isThumbFunction(); 1534db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1535db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned NumBytes = MFI->getStackSize(); 1536db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1537c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 1538db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1539db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Determine the sizes of each callee-save spill areas and record which frame 1540db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // belongs to which callee-save spill areas. 1541db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 1542db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin int FramePtrSpillFI = 0; 1543db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1544c8ce2d4cb9ef5ff8b3c574e522c870741d88ba58Bob Wilson // Allocate the vararg register save area. This is not counted in NumBytes. 1545db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (VARegSaveSize) 15466495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize); 1547db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1548db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (!AFI->hasStackFrame()) { 1549db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (NumBytes != 0) 15506495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes); 1551db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return; 1552db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1553db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1554db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1555db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Reg = CSI[i].getReg(); 1556db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin int FI = CSI[i].getFrameIdx(); 1557db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin switch (Reg) { 1558db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R4: 1559db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R5: 1560db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R6: 1561db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R7: 1562db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::LR: 1563db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Reg == FramePtr) 1564db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin FramePtrSpillFI = FI; 1565db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->addGPRCalleeSavedArea1Frame(FI); 1566db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin GPRCS1Size += 4; 1567db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1568db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R8: 1569db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R9: 1570db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R10: 1571db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R11: 1572db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Reg == FramePtr) 1573db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin FramePtrSpillFI = FI; 1574db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (STI.isTargetDarwin()) { 1575db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->addGPRCalleeSavedArea2Frame(FI); 1576db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin GPRCS2Size += 4; 1577db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } else { 1578db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->addGPRCalleeSavedArea1Frame(FI); 1579db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin GPRCS1Size += 4; 1580db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1581db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1582db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin default: 1583db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->addDPRCalleeSavedAreaFrame(FI); 1584db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin DPRCSSize += 8; 1585db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1586db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1587db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1588db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Build the new SUBri to adjust SP for integer callee-save spill area 1. 15896495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size); 15905732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI); 1591db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1592c8ce2d4cb9ef5ff8b3c574e522c870741d88ba58Bob Wilson // Set FP to point to the stack slot that contains the previous FP. 1593c8ce2d4cb9ef5ff8b3c574e522c870741d88ba58Bob Wilson // For Darwin, FP is R7, which has now been stored in spill area 1. 1594c8ce2d4cb9ef5ff8b3c574e522c870741d88ba58Bob Wilson // Otherwise, if this is not Darwin, all the callee-saved registers go 1595c8ce2d4cb9ef5ff8b3c574e522c870741d88ba58Bob Wilson // into spill area 1, including the FP in R11. In either case, it is 1596c8ce2d4cb9ef5ff8b3c574e522c870741d88ba58Bob Wilson // now safe to emit this assignment. 1597ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng bool HasFP = hasFP(MF); 1598ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (HasFP) { 15996495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri; 1600db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineInstrBuilder MIB = 16016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr) 1602db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin .addFrameIndex(FramePtrSpillFI).addImm(0); 1603db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AddDefaultCC(AddDefaultPred(MIB)); 1604db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1605db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1606db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Build the new SUBri to adjust SP for integer callee-save spill area 2. 16076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size); 1608db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1609db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Build the new SUBri to adjust SP for FP callee-save spill area. 16105732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI); 16116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize); 1612db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1613db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Determine starting offsets of spill areas. 1614db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 1615db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 1616db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 1617ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (HasFP) 1618436e6e7b5c85f12b7c2e41b7fd5c48e5d4d72912Bob Wilson AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + 1619436e6e7b5c85f12b7c2e41b7fd5c48e5d4d72912Bob Wilson NumBytes); 1620db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 1621db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 1622db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 1623db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1624e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI); 1625db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin NumBytes = DPRCSOffset; 1626db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (NumBytes) { 1627c5848f4ced8f9174e7141c0d2589acaafa13ff35Jim Grosbach // Adjust SP after all the callee-save spills. 16286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes); 1629ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (HasFP) 1630ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng AFI->setShouldRestoreSPFromFP(true); 1631db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1632db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1633db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (STI.isTargetELF() && hasFP(MF)) { 1634db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 1635db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->getFramePtrSpillOffset()); 1636ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng AFI->setShouldRestoreSPFromFP(true); 1637db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1638db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1639db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 1640db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 1641db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 16423dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach 16433dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach // If we need dynamic stack realignment, do it here. 16443dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach if (needsStackRealignment(MF)) { 16453dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach unsigned MaxAlign = MFI->getMaxAlignment(); 16463dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach assert (!AFI->isThumb1OnlyFunction()); 16477cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov if (!AFI->isThumbFunction()) { 16487cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov // Emit bic sp, sp, MaxAlign 16497cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, 16507cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov TII.get(ARM::BICri), ARM::SP) 16513dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach .addReg(ARM::SP, RegState::Kill) 16523dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach .addImm(MaxAlign-1))); 16537cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov } else { 16547cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov // We cannot use sp as source/dest register here, thus we're emitting the 16557cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov // following sequence: 16567cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov // mov r4, sp 16577cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov // bic r4, r4, MaxAlign 16587cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov // mov sp, r4 16597cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov // FIXME: It will be better just to find spare register here. 1660e9912dc553bf7e37494eb9b07e8ff880f0481a56Jakob Stoklund Olesen BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4) 16617cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov .addReg(ARM::SP, RegState::Kill); 16627cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, 16637cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov TII.get(ARM::t2BICri), ARM::R4) 16647cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov .addReg(ARM::R4, RegState::Kill) 16657cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov .addImm(MaxAlign-1))); 16667cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP) 16677cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov .addReg(ARM::R4, RegState::Kill); 16687cca606aaa6fee6ff4f548aa3686608b6be1f208Anton Korobeynikov } 1669ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng 1670ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng AFI->setShouldRestoreSPFromFP(true); 16713dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach } 1672ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng 1673ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng // If the frame has variable sized objects then the epilogue must restore 1674ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng // the sp from fp. 1675ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (!AFI->shouldRestoreSPFromFP() && MFI->hasVarSizedObjects()) 1676ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng AFI->setShouldRestoreSPFromFP(true); 1677db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1678db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1679db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinstatic bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 1680db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin for (unsigned i = 0; CSRegs[i]; ++i) 1681db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Reg == CSRegs[i]) 1682db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return true; 1683db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return false; 1684db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1685db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 168677521f5232e679aa3de10aaaed2464aa91d7ff55David Goodwinstatic bool isCSRestore(MachineInstr *MI, 1687764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach const ARMBaseInstrInfo &TII, 168877521f5232e679aa3de10aaaed2464aa91d7ff55David Goodwin const unsigned *CSRegs) { 1689e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach return ((MI->getOpcode() == (int)ARM::VLDRD || 16905732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng MI->getOpcode() == (int)ARM::LDR || 16915732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng MI->getOpcode() == (int)ARM::t2LDRi12) && 1692db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MI->getOperand(1).isFI() && 1693db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 1694db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1695db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1696db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinvoid ARMBaseRegisterInfo:: 1697293f8d9b8800ab68c64b67f38a7f76e00126715dEvan ChengemitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { 1698db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock::iterator MBBI = prior(MBB.end()); 16995ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng assert(MBBI->getDesc().isReturn() && 1700db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin "Can only insert epilog into returning blocks"); 170151e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen unsigned RetOpcode = MBBI->getOpcode(); 1702db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin DebugLoc dl = MBBI->getDebugLoc(); 1703db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineFrameInfo *MFI = MF.getFrameInfo(); 1704db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 17056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(!AFI->isThumb1OnlyFunction() && 1706cf453ee70a1ae03cc641686fd5db0f8a7d8ce250Jim Grosbach "This emitEpilogue does not support Thumb1!"); 17076495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isARM = !AFI->isThumbFunction(); 17086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1709db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1710db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin int NumBytes = (int)MFI->getStackSize(); 1711db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1712db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (!AFI->hasStackFrame()) { 1713db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (NumBytes != 0) 17146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 1715db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } else { 1716e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach // Unwind MBBI to point to first LDR / VLDRD. 1717db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin const unsigned *CSRegs = getCalleeSavedRegs(); 1718db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (MBBI != MBB.begin()) { 1719db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin do 1720db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin --MBBI; 172177521f5232e679aa3de10aaaed2464aa91d7ff55David Goodwin while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs)); 172277521f5232e679aa3de10aaaed2464aa91d7ff55David Goodwin if (!isCSRestore(MBBI, TII, CSRegs)) 1723db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ++MBBI; 1724db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1725db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1726db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Move SP to start of FP callee save spill area. 1727db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 1728db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->getGPRCalleeSavedArea2Size() + 1729db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->getDPRCalleeSavedAreaSize()); 1730db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1731ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng // Reset SP based on frame pointer only if the stack frame extends beyond 1732ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng // frame pointer stack slot or target is ELF and the function has FP. 1733ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (AFI->shouldRestoreSPFromFP()) { 1734db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1735ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (NumBytes) { 1736ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (isARM) 1737ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, 1738ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng ARMCC::AL, 0, TII); 1739ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng else 1740ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, 1741ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng ARMCC::AL, 0, TII); 1742ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng } else { 1743ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng // Thumb2 or ARM. 1744ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng if (isARM) 1745ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) 1746ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 1747ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng else 1748ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP) 1749ac096808a3accc516ae7c193c9a2c1392bf3301aEvan Cheng .addReg(FramePtr); 1750db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 17516495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else if (NumBytes) 17526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 1753db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1754db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Move SP to start of integer callee save spill area 2. 1755e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI); 17566495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize()); 1757db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1758db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Move SP to start of integer callee save spill area 1. 17595732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI); 17606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size()); 1761db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1762db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Move SP to SP upon entry to the function. 17635732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI); 17646495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size()); 1765db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1766db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 176751e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND || 176851e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) { 176951e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen // Tail call return: adjust the stack pointer and jump to callee. 177051e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen MBBI = prior(MBB.end()); 177151e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen MachineOperand &JumpTarget = MBBI->getOperand(0); 177251e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen 177351e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen // Jump to label or value in register. 177451e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen if (RetOpcode == ARM::TCRETURNdi) { 17757835f1fcdbb58093377c9e3476f45a2638565762Dale Johannesen BuildMI(MBB, MBBI, dl, 17767835f1fcdbb58093377c9e3476f45a2638565762Dale Johannesen TII.get(STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)). 177751e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), 177851e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen JumpTarget.getTargetFlags()); 177951e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen } else if (RetOpcode == ARM::TCRETURNdiND) { 178010416803c1370fe1e52a7f1c431fe506be9c1ef5Dale Johannesen BuildMI(MBB, MBBI, dl, 178110416803c1370fe1e52a7f1c431fe506be9c1ef5Dale Johannesen TII.get(STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND)). 178251e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), 178351e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen JumpTarget.getTargetFlags()); 178451e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen } else if (RetOpcode == ARM::TCRETURNri) { 17856470a116f17b70aba0c2e7ee751551a5ac9797f6Dale Johannesen BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)). 17866470a116f17b70aba0c2e7ee751551a5ac9797f6Dale Johannesen addReg(JumpTarget.getReg(), RegState::Kill); 178751e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen } else if (RetOpcode == ARM::TCRETURNriND) { 17886470a116f17b70aba0c2e7ee751551a5ac9797f6Dale Johannesen BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)). 17896470a116f17b70aba0c2e7ee751551a5ac9797f6Dale Johannesen addReg(JumpTarget.getReg(), RegState::Kill); 179051e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen } 179151e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen 179251e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen MachineInstr *NewMI = prior(MBBI); 17936470a116f17b70aba0c2e7ee751551a5ac9797f6Dale Johannesen for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i) 179451e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen NewMI->addOperand(MBBI->getOperand(i)); 179551e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen 179651e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen // Delete the pseudo instruction TCRETURN. 179751e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen MBB.erase(MBBI); 179851e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen } 179951e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen 1800db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (VARegSaveSize) 18016495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize); 1802db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1803db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1804c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMGenRegisterInfo.inc" 1805