ARMBaseRegisterInfo.cpp revision e11a8f565c6a019ddc54667227be9c4d8f117473
12cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattner//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===// 2c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 3c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// The LLVM Compiler Infrastructure 4c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 5c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// This file is distributed under the University of Illinois Open Source 6c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// License. See LICENSE.TXT for details. 7c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 8c140c4803dc3e10e08138670829bc0494986abe9David Goodwin//===----------------------------------------------------------------------===// 9c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 10c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// This file contains the base ARM implementation of TargetRegisterInfo class. 11c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 12c140c4803dc3e10e08138670829bc0494986abe9David Goodwin//===----------------------------------------------------------------------===// 13c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 14c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARM.h" 15c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMAddressingModes.h" 16db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin#include "ARMBaseInstrInfo.h" 17c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMBaseRegisterInfo.h" 18c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMInstrInfo.h" 19c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMMachineFunctionInfo.h" 20c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMSubtarget.h" 21c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/Constants.h" 22c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/DerivedTypes.h" 239adc0abad3c3ed40a268ccbcee0c74cb9e1359feOwen Anderson#include "llvm/Function.h" 249adc0abad3c3ed40a268ccbcee0c74cb9e1359feOwen Anderson#include "llvm/LLVMContext.h" 25c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineConstantPool.h" 26c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 27c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineFunction.h" 28c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 29c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineLocation.h" 30c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineRegisterInfo.h" 31c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/RegisterScavenging.h" 32ab7c09b6b6f4516a631fd6788918c237c83939afTorok Edwin#include "llvm/Support/ErrorHandling.h" 33dac237e18209b697a8ba122d0ddd9cad4dfba1f8Torok Edwin#include "llvm/Support/raw_ostream.h" 34c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/Target/TargetFrameInfo.h" 35c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/Target/TargetMachine.h" 36c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/Target/TargetOptions.h" 37c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/ADT/BitVector.h" 38c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/ADT/SmallVector.h" 39c140c4803dc3e10e08138670829bc0494986abe9David Goodwinusing namespace llvm; 40c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 41c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum, 428295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng bool *isSPVFP) { 438295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng if (isSPVFP) 448295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng *isSPVFP = false; 45c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 46c140c4803dc3e10e08138670829bc0494986abe9David Goodwin using namespace ARM; 47c140c4803dc3e10e08138670829bc0494986abe9David Goodwin switch (RegEnum) { 48c140c4803dc3e10e08138670829bc0494986abe9David Goodwin default: 49c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Unknown ARM register!"); 508295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R0: case D0: case Q0: return 0; 518295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R1: case D1: case Q1: return 1; 528295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R2: case D2: case Q2: return 2; 538295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R3: case D3: case Q3: return 3; 548295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R4: case D4: case Q4: return 4; 558295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R5: case D5: case Q5: return 5; 568295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R6: case D6: case Q6: return 6; 578295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R7: case D7: case Q7: return 7; 588295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R8: case D8: case Q8: return 8; 598295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R9: case D9: case Q9: return 9; 608295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R10: case D10: case Q10: return 10; 618295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R11: case D11: case Q11: return 11; 628295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case R12: case D12: case Q12: return 12; 638295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case SP: case D13: case Q13: return 13; 648295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case LR: case D14: case Q14: return 14; 658295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case PC: case D15: case Q15: return 15; 668295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng 678295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D16: return 16; 688295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D17: return 17; 698295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D18: return 18; 708295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D19: return 19; 718295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D20: return 20; 728295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D21: return 21; 738295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D22: return 22; 748295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D23: return 23; 758295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D24: return 24; 768295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D25: return 25; 778295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D26: return 27; 788295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D27: return 27; 798295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D28: return 28; 808295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D29: return 29; 818295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D30: return 30; 828295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case D31: return 31; 83c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 84c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S0: case S1: case S2: case S3: 85c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S4: case S5: case S6: case S7: 86c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S8: case S9: case S10: case S11: 87c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S12: case S13: case S14: case S15: 88c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S16: case S17: case S18: case S19: 89c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S20: case S21: case S22: case S23: 90c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S24: case S25: case S26: case S27: 918295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case S28: case S29: case S30: case S31: { 928295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng if (isSPVFP) 938295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng *isSPVFP = true; 94c140c4803dc3e10e08138670829bc0494986abe9David Goodwin switch (RegEnum) { 95c140c4803dc3e10e08138670829bc0494986abe9David Goodwin default: return 0; // Avoid compile time warning. 96c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S0: return 0; 97c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S1: return 1; 98c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S2: return 2; 99c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S3: return 3; 100c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S4: return 4; 101c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S5: return 5; 102c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S6: return 6; 103c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S7: return 7; 104c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S8: return 8; 105c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S9: return 9; 106c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S10: return 10; 107c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S11: return 11; 108c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S12: return 12; 109c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S13: return 13; 110c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S14: return 14; 111c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S15: return 15; 112c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S16: return 16; 113c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S17: return 17; 114c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S18: return 18; 115c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S19: return 19; 116c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S20: return 20; 117c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S21: return 21; 118c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S22: return 22; 119c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S23: return 23; 120c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S24: return 24; 121c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S25: return 25; 122c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S26: return 26; 123c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S27: return 27; 124c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S28: return 28; 125c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S29: return 29; 126c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S30: return 30; 127c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case S31: return 31; 128c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 129c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 130c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 131c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 132c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 133db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, 134c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const ARMSubtarget &sti) 135c140c4803dc3e10e08138670829bc0494986abe9David Goodwin : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 136c140c4803dc3e10e08138670829bc0494986abe9David Goodwin TII(tii), STI(sti), 137c140c4803dc3e10e08138670829bc0494986abe9David Goodwin FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) { 138c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 139c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 140c140c4803dc3e10e08138670829bc0494986abe9David Goodwinconst unsigned* 141c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 142c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned CalleeSavedRegs[] = { 143c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 144c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R7, ARM::R6, ARM::R5, ARM::R4, 145c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 146c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::D15, ARM::D14, ARM::D13, ARM::D12, 147c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::D11, ARM::D10, ARM::D9, ARM::D8, 148c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 0 149c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 150c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 151c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned DarwinCalleeSavedRegs[] = { 152c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved 153c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // register. 154c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 155c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R11, ARM::R10, ARM::R8, 156c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 157c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::D15, ARM::D14, ARM::D13, ARM::D12, 158c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::D11, ARM::D10, ARM::D9, ARM::D8, 159c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 0 160c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 161c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 162c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 163c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 164c140c4803dc3e10e08138670829bc0494986abe9David Goodwinconst TargetRegisterClass* const * 165c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { 166c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 167e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass, 168e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass, 169e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass, 170c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 171e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass, 172e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass, 173e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach ARM::DPRRegisterClass, ARM::DPRRegisterClass, 174c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 0 175c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 176c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 177c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = { 178e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass, 179e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::tGPRRegisterClass, 180e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach ARM::tGPRRegisterClass,ARM::tGPRRegisterClass,ARM::tGPRRegisterClass, 181c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 182e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass, 183e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass, 184e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach ARM::DPRRegisterClass, ARM::DPRRegisterClass, 185c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 0 186c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 187c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 188c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = { 189e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass, 190e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass, 191e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach ARM::GPRRegisterClass, ARM::GPRRegisterClass, 192c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 193e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass, 194e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass, 195e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach ARM::DPRRegisterClass, ARM::DPRRegisterClass, 196c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 0 197c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 198c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 199c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={ 200e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach ARM::GPRRegisterClass, ARM::tGPRRegisterClass, ARM::tGPRRegisterClass, 201e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach ARM::tGPRRegisterClass, ARM::tGPRRegisterClass, ARM::GPRRegisterClass, 202e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach ARM::GPRRegisterClass, ARM::GPRRegisterClass, 203c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 204e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass, 205e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass, 206e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach ARM::DPRRegisterClass, ARM::DPRRegisterClass, 207c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 0 208c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 209c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 210f1daf7d8abebd6e0104a6b41a774ccbb19a51c60David Goodwin if (STI.isThumb1Only()) { 211c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return STI.isTargetDarwin() 212c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses; 213c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 214c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return STI.isTargetDarwin() 215c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses; 216c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 217c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 218c140c4803dc3e10e08138670829bc0494986abe9David GoodwinBitVector ARMBaseRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 219c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // FIXME: avoid re-calculating this everytime. 220c140c4803dc3e10e08138670829bc0494986abe9David Goodwin BitVector Reserved(getNumRegs()); 221c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(ARM::SP); 222c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(ARM::PC); 223c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (STI.isTargetDarwin() || hasFP(MF)) 224c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(FramePtr); 225c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Some targets reserve R9. 226c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (STI.isR9Reserved()) 227c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(ARM::R9); 228c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return Reserved; 229c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 230c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 2312cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattnerbool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF, 2322cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattner unsigned Reg) const { 233c140c4803dc3e10e08138670829bc0494986abe9David Goodwin switch (Reg) { 234c140c4803dc3e10e08138670829bc0494986abe9David Goodwin default: break; 235c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::SP: 236c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::PC: 237c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return true; 238c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R7: 239c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R11: 240c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF))) 241c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return true; 242c140c4803dc3e10e08138670829bc0494986abe9David Goodwin break; 243c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R9: 244c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return STI.isR9Reserved(); 245c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 246c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 247c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return false; 248c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 249c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 2502cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattnerconst TargetRegisterClass * 2512cfd52c507bd5790457a171eb9bcb39019cc6860Chris LattnerARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const { 252e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach return ARM::GPRRegisterClass; 253c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 254c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 255c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// getAllocationOrder - Returns the register allocation order for a specified 256c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// register class in the form of a pair of TargetRegisterClass iterators. 257c140c4803dc3e10e08138670829bc0494986abe9David Goodwinstd::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator> 258c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC, 259c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned HintType, unsigned HintReg, 260c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const MachineFunction &MF) const { 261c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Alternative register allocation orders when favoring even / odd registers 262c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // of register pairs. 263c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 264c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // No FP, R9 is available. 265c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven1[] = { 266c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, 267c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, 268c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R9, ARM::R11 269c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 270c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd1[] = { 271c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11, 272c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 273c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R8, ARM::R10 274c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 275c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 276c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // FP is R7, R9 is available. 277c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven2[] = { 278c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10, 279c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, 280c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R9, ARM::R11 281c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 282c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd2[] = { 283c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11, 284c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 285c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R8, ARM::R10 286c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 287c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 288c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // FP is R11, R9 is available. 289c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven3[] = { 290c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, 291c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, 292c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R9 293c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 294c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd3[] = { 295c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9, 296c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7, 297c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R8 298c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 299c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 300c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // No FP, R9 is not available. 301c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven4[] = { 302c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10, 303c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8, 304c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R11 305c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 306c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd4[] = { 307c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11, 308c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 309c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R10 310c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 311c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 312c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // FP is R7, R9 is not available. 313c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven5[] = { 314c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R10, 315c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8, 316c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R11 317c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 318c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd5[] = { 319c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R11, 320c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 321c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R10 322c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 323c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 324c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // FP is R11, R9 is not available. 325c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven6[] = { 326c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R6, 327c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8 328c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 329c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd6[] = { 330c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R7, 331c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8 332c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 333c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 334c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 335c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (HintType == ARMRI::RegPairEven) { 336c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0) 337c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // It's no longer possible to fulfill this hint. Return the default 338c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // allocation order. 339c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(RC->allocation_order_begin(MF), 340c140c4803dc3e10e08138670829bc0494986abe9David Goodwin RC->allocation_order_end(MF)); 341c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 342c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isTargetDarwin() && !hasFP(MF)) { 343c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 344c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPREven1, 345c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPREven1 + (sizeof(GPREven1)/sizeof(unsigned))); 346c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 347c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPREven4, 348c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPREven4 + (sizeof(GPREven4)/sizeof(unsigned))); 349c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else if (FramePtr == ARM::R7) { 350c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 351c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPREven2, 352c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPREven2 + (sizeof(GPREven2)/sizeof(unsigned))); 353c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 354c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPREven5, 355c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPREven5 + (sizeof(GPREven5)/sizeof(unsigned))); 356c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else { // FramePtr == ARM::R11 357c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 358c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPREven3, 359c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPREven3 + (sizeof(GPREven3)/sizeof(unsigned))); 360c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 361c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPREven6, 362c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPREven6 + (sizeof(GPREven6)/sizeof(unsigned))); 363c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 364c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else if (HintType == ARMRI::RegPairOdd) { 365c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0) 366c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // It's no longer possible to fulfill this hint. Return the default 367c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // allocation order. 368c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(RC->allocation_order_begin(MF), 369c140c4803dc3e10e08138670829bc0494986abe9David Goodwin RC->allocation_order_end(MF)); 370c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 371c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isTargetDarwin() && !hasFP(MF)) { 372c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 373c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPROdd1, 374c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned))); 375c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 376c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPROdd4, 377c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned))); 378c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else if (FramePtr == ARM::R7) { 379c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 380c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPROdd2, 381c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned))); 382c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 383c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPROdd5, 384c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned))); 385c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else { // FramePtr == ARM::R11 386c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 387c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPROdd3, 388c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned))); 389c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 390c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(GPROdd6, 391c140c4803dc3e10e08138670829bc0494986abe9David Goodwin GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned))); 392c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 393c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 394c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return std::make_pair(RC->allocation_order_begin(MF), 395c140c4803dc3e10e08138670829bc0494986abe9David Goodwin RC->allocation_order_end(MF)); 396c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 397c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 398c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// ResolveRegAllocHint - Resolves the specified register allocation hint 399c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// to a physical register. Returns the physical register if it is successful. 400c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned 401c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg, 402c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const MachineFunction &MF) const { 403c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (Reg == 0 || !isPhysicalRegister(Reg)) 404c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 405c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (Type == 0) 406c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return Reg; 407c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else if (Type == (unsigned)ARMRI::RegPairOdd) 408c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Odd register. 409c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return getRegisterPairOdd(Reg, MF); 410c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else if (Type == (unsigned)ARMRI::RegPairEven) 411c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Even register. 412c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return getRegisterPairEven(Reg, MF); 413c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 414c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 415c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 416c140c4803dc3e10e08138670829bc0494986abe9David Goodwinvoid 417c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 418c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MachineFunction &MF) const { 419c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MachineRegisterInfo *MRI = &MF.getRegInfo(); 420c140c4803dc3e10e08138670829bc0494986abe9David Goodwin std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 421c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 422c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Hint.first == (unsigned)ARMRI::RegPairEven) && 423c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) { 424c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // If 'Reg' is one of the even / odd register pair and it's now changed 425c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // (e.g. coalesced) into a different register. The other register of the 426c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // pair allocation hint must be updated to reflect the relationship 427c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // change. 428c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned OtherReg = Hint.second; 429c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Hint = MRI->getRegAllocationHint(OtherReg); 430c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (Hint.second == Reg) 431c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Make sure the pair has not already divorced. 432c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 433c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 434c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 435c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 436c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// hasFP - Return true if the specified function should have a dedicated frame 437c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// pointer register. This is true if the function has variable sized allocas 438c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// or if frame pointer elimination is disabled. 439c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// 440c140c4803dc3e10e08138670829bc0494986abe9David Goodwinbool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const { 441c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const MachineFrameInfo *MFI = MF.getFrameInfo(); 442c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return (NoFramePointerElim || 443c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MFI->hasVarSizedObjects() || 444c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MFI->isFrameAddressTaken()); 445c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 446c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 447010b1b9e7b11bced0b277a4d808226ba2af3044aEvan Chengbool ARMBaseRegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const { 44898a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng const MachineFrameInfo *MFI = MF.getFrameInfo(); 44998a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng if (NoFramePointerElim && MFI->hasCalls()) 45098a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng return true; 45198a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken(); 45298a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng} 45398a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng 454542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng/// estimateStackSize - Estimate and return the size of the frame. 455c140c4803dc3e10e08138670829bc0494986abe9David Goodwinstatic unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) { 456c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const MachineFrameInfo *FFI = MF.getFrameInfo(); 457c140c4803dc3e10e08138670829bc0494986abe9David Goodwin int Offset = 0; 458c140c4803dc3e10e08138670829bc0494986abe9David Goodwin for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) { 459c140c4803dc3e10e08138670829bc0494986abe9David Goodwin int FixedOff = -FFI->getObjectOffset(i); 460c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (FixedOff > Offset) Offset = FixedOff; 461c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 462c140c4803dc3e10e08138670829bc0494986abe9David Goodwin for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) { 463c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (FFI->isDeadObjectIndex(i)) 464c140c4803dc3e10e08138670829bc0494986abe9David Goodwin continue; 465c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Offset += FFI->getObjectSize(i); 466c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned Align = FFI->getObjectAlignment(i); 467c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Adjust to alignment boundary 468c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Offset = (Offset+Align-1)/Align*Align; 469c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 470c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return (unsigned)Offset; 471c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 472c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 473542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng/// estimateRSStackSizeLimit - Look at each instruction that references stack 474542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng/// frames and return the stack size limit beyond which some of these 475542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng/// instructions will require scratch register during their expansion later. 476ee42fd309ee6a8febfafb97c2f3b6f2069758c5eEvan Chengunsigned 477ee42fd309ee6a8febfafb97c2f3b6f2069758c5eEvan ChengARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const { 478542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng unsigned Limit = (1 << 12) - 1; 479b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) { 480b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); 481b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner I != E; ++I) { 482b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { 483b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner if (!I->getOperand(i).isFI()) continue; 484764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 485b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner const TargetInstrDesc &Desc = TII.get(I->getOpcode()); 486b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 487b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner if (AddrMode == ARMII::AddrMode3 || 488b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner AddrMode == ARMII::AddrModeT2_i8) 489b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner return (1 << 8) - 1; 490764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 491b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner if (AddrMode == ARMII::AddrMode5 || 492b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner AddrMode == ARMII::AddrModeT2_i8s4) 493b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner Limit = std::min(Limit, ((1U << 8) - 1) * 4); 494ee42fd309ee6a8febfafb97c2f3b6f2069758c5eEvan Cheng 495ee42fd309ee6a8febfafb97c2f3b6f2069758c5eEvan Cheng if (AddrMode == ARMII::AddrModeT2_i12 && hasFP(MF)) 496ee42fd309ee6a8febfafb97c2f3b6f2069758c5eEvan Cheng // When the stack offset is negative, we will end up using 497ee42fd309ee6a8febfafb97c2f3b6f2069758c5eEvan Cheng // the i8 instructions instead. 498ee42fd309ee6a8febfafb97c2f3b6f2069758c5eEvan Cheng return (1 << 8) - 1; 499b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner break; // At most one FI per instruction 500b180d992d81f97862af6089dfe899d0363cac6f5Chris Lattner } 501542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng } 502542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng } 503542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng 504542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng return Limit; 505542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng} 506542383d93b146e11a1d70c01f8afea8ea9f08effEvan Cheng 507c140c4803dc3e10e08138670829bc0494986abe9David Goodwinvoid 508c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 509c140c4803dc3e10e08138670829bc0494986abe9David Goodwin RegScavenger *RS) const { 510c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // This tells PEI to spill the FP as if it is any other callee-save register 511c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // to take advantage the eliminateFrameIndex machinery. This also ensures it 512c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // is spilled in the order specified by getCalleeSavedRegs() to make it easier 513c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // to combine multiple loads / stores. 514c140c4803dc3e10e08138670829bc0494986abe9David Goodwin bool CanEliminateFrame = true; 515c140c4803dc3e10e08138670829bc0494986abe9David Goodwin bool CS1Spilled = false; 516c140c4803dc3e10e08138670829bc0494986abe9David Goodwin bool LRSpilled = false; 517c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned NumGPRSpills = 0; 518c140c4803dc3e10e08138670829bc0494986abe9David Goodwin SmallVector<unsigned, 4> UnspilledCS1GPRs; 519c140c4803dc3e10e08138670829bc0494986abe9David Goodwin SmallVector<unsigned, 4> UnspilledCS2GPRs; 520c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 521c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 522c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Don't spill FP if the frame can be eliminated. This is determined 523c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // by scanning the callee-save registers to see if any is used. 524c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const unsigned *CSRegs = getCalleeSavedRegs(); 525c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses(); 526c140c4803dc3e10e08138670829bc0494986abe9David Goodwin for (unsigned i = 0; CSRegs[i]; ++i) { 527c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned Reg = CSRegs[i]; 528c140c4803dc3e10e08138670829bc0494986abe9David Goodwin bool Spilled = false; 529c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (MF.getRegInfo().isPhysRegUsed(Reg)) { 530c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setCSRegisterIsSpilled(Reg); 531c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Spilled = true; 532c140c4803dc3e10e08138670829bc0494986abe9David Goodwin CanEliminateFrame = false; 533c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else { 534c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Check alias registers too. 535c140c4803dc3e10e08138670829bc0494986abe9David Goodwin for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { 536c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (MF.getRegInfo().isPhysRegUsed(*Aliases)) { 537c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Spilled = true; 538c140c4803dc3e10e08138670829bc0494986abe9David Goodwin CanEliminateFrame = false; 539c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 540c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 541c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 542c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 543e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach if (CSRegClasses[i] == ARM::GPRRegisterClass) { 544c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (Spilled) { 545c140c4803dc3e10e08138670829bc0494986abe9David Goodwin NumGPRSpills++; 546c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 547c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isTargetDarwin()) { 548c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (Reg == ARM::LR) 549c140c4803dc3e10e08138670829bc0494986abe9David Goodwin LRSpilled = true; 550c140c4803dc3e10e08138670829bc0494986abe9David Goodwin CS1Spilled = true; 551c140c4803dc3e10e08138670829bc0494986abe9David Goodwin continue; 552c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 553c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 554c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 555c140c4803dc3e10e08138670829bc0494986abe9David Goodwin switch (Reg) { 556c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::LR: 557c140c4803dc3e10e08138670829bc0494986abe9David Goodwin LRSpilled = true; 558c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Fallthrough 559c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R4: 560c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R5: 561c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R6: 562c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R7: 563c140c4803dc3e10e08138670829bc0494986abe9David Goodwin CS1Spilled = true; 564c140c4803dc3e10e08138670829bc0494986abe9David Goodwin break; 565c140c4803dc3e10e08138670829bc0494986abe9David Goodwin default: 566c140c4803dc3e10e08138670829bc0494986abe9David Goodwin break; 567c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 568c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else { 569c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isTargetDarwin()) { 570c140c4803dc3e10e08138670829bc0494986abe9David Goodwin UnspilledCS1GPRs.push_back(Reg); 571c140c4803dc3e10e08138670829bc0494986abe9David Goodwin continue; 572c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 573c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 574c140c4803dc3e10e08138670829bc0494986abe9David Goodwin switch (Reg) { 575c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R4: 576c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R5: 577c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R6: 578c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R7: 579c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::LR: 580c140c4803dc3e10e08138670829bc0494986abe9David Goodwin UnspilledCS1GPRs.push_back(Reg); 581c140c4803dc3e10e08138670829bc0494986abe9David Goodwin break; 582c140c4803dc3e10e08138670829bc0494986abe9David Goodwin default: 583c140c4803dc3e10e08138670829bc0494986abe9David Goodwin UnspilledCS2GPRs.push_back(Reg); 584c140c4803dc3e10e08138670829bc0494986abe9David Goodwin break; 585c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 586c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 587c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 588c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 589c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 590c140c4803dc3e10e08138670829bc0494986abe9David Goodwin bool ForceLRSpill = false; 591f1daf7d8abebd6e0104a6b41a774ccbb19a51c60David Goodwin if (!LRSpilled && AFI->isThumb1OnlyFunction()) { 592c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned FnSize = TII.GetFunctionSizeInBytes(MF); 593c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Force LR to be spilled if the Thumb function size is > 2048. This enables 594c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // use of BL to implement far jump. If it turns out that it's not needed 595c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // then the branch fix up path will undo it. 596c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (FnSize >= (1 << 11)) { 597c140c4803dc3e10e08138670829bc0494986abe9David Goodwin CanEliminateFrame = false; 598c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ForceLRSpill = true; 599c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 600c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 601c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 602c140c4803dc3e10e08138670829bc0494986abe9David Goodwin bool ExtraCSSpill = false; 603010b1b9e7b11bced0b277a4d808226ba2af3044aEvan Cheng if (!CanEliminateFrame || cannotEliminateFrame(MF)) { 604c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setHasStackFrame(true); 605c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 606c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 607c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 608c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!LRSpilled && CS1Spilled) { 609c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MF.getRegInfo().setPhysRegUsed(ARM::LR); 610c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setCSRegisterIsSpilled(ARM::LR); 611c140c4803dc3e10e08138670829bc0494986abe9David Goodwin NumGPRSpills++; 612c140c4803dc3e10e08138670829bc0494986abe9David Goodwin UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 613c140c4803dc3e10e08138670829bc0494986abe9David Goodwin UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 614c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ForceLRSpill = false; 615c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ExtraCSSpill = true; 616c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 617c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 618c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Darwin ABI requires FP to point to the stack slot that contains the 619c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // previous FP. 620c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (STI.isTargetDarwin() || hasFP(MF)) { 621c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MF.getRegInfo().setPhysRegUsed(FramePtr); 622c140c4803dc3e10e08138670829bc0494986abe9David Goodwin NumGPRSpills++; 623c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 624c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 625c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // If stack and double are 8-byte aligned and we are spilling an odd number 626c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // of GPRs. Spill one extra callee save GPR so we won't have to pad between 627c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // the integer and double callee save areas. 628c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); 629c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (TargetAlign == 8 && (NumGPRSpills & 1)) { 630c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (CS1Spilled && !UnspilledCS1GPRs.empty()) { 631c140c4803dc3e10e08138670829bc0494986abe9David Goodwin for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { 632c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned Reg = UnspilledCS1GPRs[i]; 633f1daf7d8abebd6e0104a6b41a774ccbb19a51c60David Goodwin // Don't spill high register if the function is thumb1 634f1daf7d8abebd6e0104a6b41a774ccbb19a51c60David Goodwin if (!AFI->isThumb1OnlyFunction() || 635c140c4803dc3e10e08138670829bc0494986abe9David Goodwin isARMLowRegister(Reg) || Reg == ARM::LR) { 636c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MF.getRegInfo().setPhysRegUsed(Reg); 637c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setCSRegisterIsSpilled(Reg); 638c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!isReservedReg(MF, Reg)) 639c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ExtraCSSpill = true; 640c140c4803dc3e10e08138670829bc0494986abe9David Goodwin break; 641c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 642c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 643c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else if (!UnspilledCS2GPRs.empty() && 644f1daf7d8abebd6e0104a6b41a774ccbb19a51c60David Goodwin !AFI->isThumb1OnlyFunction()) { 645c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned Reg = UnspilledCS2GPRs.front(); 646c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MF.getRegInfo().setPhysRegUsed(Reg); 647c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setCSRegisterIsSpilled(Reg); 648c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!isReservedReg(MF, Reg)) 649c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ExtraCSSpill = true; 650c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 651c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 652c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 653c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Estimate if we might need to scavenge a register at some point in order 654c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // to materialize a stack offset. If so, either spill one additional 655c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // callee-saved register or reserve a special spill slot to facilitate 656c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // register scavenging. 657f1daf7d8abebd6e0104a6b41a774ccbb19a51c60David Goodwin if (RS && !ExtraCSSpill && !AFI->isThumb1OnlyFunction()) { 658c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MachineFrameInfo *MFI = MF.getFrameInfo(); 659ee42fd309ee6a8febfafb97c2f3b6f2069758c5eEvan Cheng if (estimateStackSize(MF, MFI) >= estimateRSStackSizeLimit(MF)) { 660c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // If any non-reserved CS register isn't spilled, just spill one or two 661c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // extra. That should take care of it! 662c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned NumExtras = TargetAlign / 4; 663c140c4803dc3e10e08138670829bc0494986abe9David Goodwin SmallVector<unsigned, 2> Extras; 664c140c4803dc3e10e08138670829bc0494986abe9David Goodwin while (NumExtras && !UnspilledCS1GPRs.empty()) { 665c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned Reg = UnspilledCS1GPRs.back(); 666c140c4803dc3e10e08138670829bc0494986abe9David Goodwin UnspilledCS1GPRs.pop_back(); 667c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!isReservedReg(MF, Reg)) { 668c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Extras.push_back(Reg); 669c140c4803dc3e10e08138670829bc0494986abe9David Goodwin NumExtras--; 670c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 671c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 672c140c4803dc3e10e08138670829bc0494986abe9David Goodwin while (NumExtras && !UnspilledCS2GPRs.empty()) { 673c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned Reg = UnspilledCS2GPRs.back(); 674c140c4803dc3e10e08138670829bc0494986abe9David Goodwin UnspilledCS2GPRs.pop_back(); 675c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!isReservedReg(MF, Reg)) { 676c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Extras.push_back(Reg); 677c140c4803dc3e10e08138670829bc0494986abe9David Goodwin NumExtras--; 678c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 679c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 680c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (Extras.size() && NumExtras == 0) { 681c140c4803dc3e10e08138670829bc0494986abe9David Goodwin for (unsigned i = 0, e = Extras.size(); i != e; ++i) { 682c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MF.getRegInfo().setPhysRegUsed(Extras[i]); 683c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setCSRegisterIsSpilled(Extras[i]); 684c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 685c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else { 686c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Reserve a slot closest to SP or frame pointer. 687e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach const TargetRegisterClass *RC = ARM::GPRRegisterClass; 688c140c4803dc3e10e08138670829bc0494986abe9David Goodwin RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 689c140c4803dc3e10e08138670829bc0494986abe9David Goodwin RC->getAlignment())); 690c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 691c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 692c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 693c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 694c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 695c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (ForceLRSpill) { 696c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MF.getRegInfo().setPhysRegUsed(ARM::LR); 697c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setCSRegisterIsSpilled(ARM::LR); 698c140c4803dc3e10e08138670829bc0494986abe9David Goodwin AFI->setLRIsSpilledForFarJump(true); 699c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 700c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 701c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 702c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getRARegister() const { 703c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::LR; 704c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 705c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 706c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getFrameRegister(MachineFunction &MF) const { 707c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (STI.isTargetDarwin() || hasFP(MF)) 708c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return FramePtr; 709c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::SP; 710c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 711c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 712c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { 713c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("What is the exception register"); 714c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 715c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 716c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 717c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { 718c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("What is the exception handler register"); 719c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 720c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 721c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 722c140c4803dc3e10e08138670829bc0494986abe9David Goodwinint ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 723c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 724c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 725c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 726c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg, 727c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const MachineFunction &MF) const { 728c140c4803dc3e10e08138670829bc0494986abe9David Goodwin switch (Reg) { 729c140c4803dc3e10e08138670829bc0494986abe9David Goodwin default: break; 730c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Return 0 if either register of the pair is a special register. 731c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // So no R12, etc. 732c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R1: 733c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::R0; 734c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R3: 735c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // FIXME! 736f1daf7d8abebd6e0104a6b41a774ccbb19a51c60David Goodwin return STI.isThumb1Only() ? 0 : ARM::R2; 737c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R5: 738c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::R4; 739c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R7: 740c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6; 741c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R9: 742c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8; 743c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R11: 744c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10; 745c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 746c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S1: 747c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S0; 748c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S3: 749c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S2; 750c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S5: 751c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S4; 752c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S7: 753c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S6; 754c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S9: 755c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S8; 756c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S11: 757c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S10; 758c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S13: 759c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S12; 760c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S15: 761c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S14; 762c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S17: 763c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S16; 764c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S19: 765c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S18; 766c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S21: 767c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S20; 768c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S23: 769c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S22; 770c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S25: 771c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S24; 772c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S27: 773c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S26; 774c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S29: 775c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S28; 776c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S31: 777c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S30; 778c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 779c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D1: 780c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D0; 781c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D3: 782c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D2; 783c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D5: 784c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D4; 785c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D7: 786c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D6; 787c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D9: 788c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D8; 789c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D11: 790c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D10; 791c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D13: 792c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D12; 793c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D15: 794c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D14; 7958295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D17: 7968295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D16; 7978295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D19: 7988295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D18; 7998295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D21: 8008295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D20; 8018295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D23: 8028295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D22; 8038295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D25: 8048295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D24; 8058295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D27: 8068295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D26; 8078295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D29: 8088295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D28; 8098295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D31: 8108295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D30; 811c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 812c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 813c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 814c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 815c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 816c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg, 817c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const MachineFunction &MF) const { 818c140c4803dc3e10e08138670829bc0494986abe9David Goodwin switch (Reg) { 819c140c4803dc3e10e08138670829bc0494986abe9David Goodwin default: break; 820c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Return 0 if either register of the pair is a special register. 821c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // So no R12, etc. 822c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R0: 823c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::R1; 824c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R2: 825c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // FIXME! 826f1daf7d8abebd6e0104a6b41a774ccbb19a51c60David Goodwin return STI.isThumb1Only() ? 0 : ARM::R3; 827c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R4: 828c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::R5; 829c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R6: 830c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7; 831c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R8: 832c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9; 833c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R10: 834c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11; 835c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 836c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S0: 837c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S1; 838c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S2: 839c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S3; 840c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S4: 841c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S5; 842c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S6: 843c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S7; 844c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S8: 845c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S9; 846c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S10: 847c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S11; 848c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S12: 849c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S13; 850c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S14: 851c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S15; 852c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S16: 853c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S17; 854c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S18: 855c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S19; 856c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S20: 857c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S21; 858c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S22: 859c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S23; 860c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S24: 861c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S25; 862c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S26: 863c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S27; 864c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S28: 865c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S29; 866c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S30: 867c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S31; 868c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 869c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D0: 870c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D1; 871c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D2: 872c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D3; 873c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D4: 874c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D5; 875c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D6: 876c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D7; 877c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D8: 878c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D9; 879c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D10: 880c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D11; 881c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D12: 882c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D13; 883c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D14: 884c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D15; 8858295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D16: 8868295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D17; 8878295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D18: 8888295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D19; 8898295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D20: 8908295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D21; 8918295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D22: 8928295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D23; 8938295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D24: 8948295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D25; 8958295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D26: 8968295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D27; 8978295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D28: 8988295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D29; 8998295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D30: 9008295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D31; 901c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 902c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 903c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 904c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 905c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 906db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// emitLoadConstPool - Emits a load from constpool to materialize the 907db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// specified immediate. 908db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinvoid ARMBaseRegisterInfo:: 909db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinemitLoadConstPool(MachineBasicBlock &MBB, 910db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock::iterator &MBBI, 91177521f5232e679aa3de10aaaed2464aa91d7ff55David Goodwin DebugLoc dl, 912378445303b10b092a898a75131141a8259cff50bEvan Cheng unsigned DestReg, unsigned SubIdx, int Val, 913db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMCC::CondCodes Pred, 914db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned PredReg) const { 915db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineFunction &MF = *MBB.getParent(); 916db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineConstantPool *ConstantPool = MF.getConstantPool(); 9171d0be15f89cb5056e20e2d24faa8d6afb1573bcaOwen Anderson Constant *C = 9181d0be15f89cb5056e20e2d24faa8d6afb1573bcaOwen Anderson ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); 919db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 920db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 921378445303b10b092a898a75131141a8259cff50bEvan Cheng BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 922378445303b10b092a898a75131141a8259cff50bEvan Cheng .addReg(DestReg, getDefRegState(true), SubIdx) 923db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin .addConstantPoolIndex(Idx) 924db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin .addReg(0).addImm(0).addImm(Pred).addReg(PredReg); 925db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 926db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 927db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinbool ARMBaseRegisterInfo:: 928db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinrequiresRegisterScavenging(const MachineFunction &MF) const { 929db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return true; 930db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 931db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 932db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin// hasReservedCallFrame - Under normal circumstances, when a frame pointer is 933db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin// not required, we reserve argument space for call sites in the function 934db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin// immediately on entry to the current function. This eliminates the need for 935db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin// add/sub sp brackets around call sites. Returns true if the call frame is 936db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin// included as part of the stack frame. 937db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinbool ARMBaseRegisterInfo:: 938db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinhasReservedCallFrame(MachineFunction &MF) const { 939db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin const MachineFrameInfo *FFI = MF.getFrameInfo(); 940db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned CFSize = FFI->getMaxCallFrameSize(); 941db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // It's not always a good idea to include the call frame as part of the 942db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // stack frame. ARM (especially Thumb) has small immediate offset to 943db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // address the stack frame. So a large call frame can cause poor codegen 944db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // and may even makes it impossible to scavenge a register. 945db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12 946db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return false; 947db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 948db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return !MF.getFrameInfo()->hasVarSizedObjects(); 949db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 950db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 951db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinstatic void 9526495f63945e8dbde81f03a1dc2ab421993b9a495Evan ChengemitSPUpdate(bool isARM, 9536495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 9546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng DebugLoc dl, const ARMBaseInstrInfo &TII, 955db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin int NumBytes, 956db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { 9576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isARM) 9586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 9596495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Pred, PredReg, TII); 9606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng else 9616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 9626495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Pred, PredReg, TII); 963db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 964db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 9656495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 966db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinvoid ARMBaseRegisterInfo:: 967db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwineliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 968db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock::iterator I) const { 969db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (!hasReservedCallFrame(MF)) { 970db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // If we have alloca, convert as follows: 971db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // ADJCALLSTACKDOWN -> sub, sp, sp, amount 972db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // ADJCALLSTACKUP -> add, sp, sp, amount 973db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineInstr *Old = I; 974db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin DebugLoc dl = Old->getDebugLoc(); 975db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Amount = Old->getOperand(0).getImm(); 976db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Amount != 0) { 977db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // We need to keep the stack aligned properly. To do this, we round the 978db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // amount of space needed for the outgoing arguments up to the next 979db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // alignment boundary. 980db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 981db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin Amount = (Amount+Align-1)/Align*Align; 982db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 9836495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 9846495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(!AFI->isThumb1OnlyFunction() && 9856495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "This eliminateCallFramePseudoInstr does not suppor Thumb1!"); 9866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isARM = !AFI->isThumbFunction(); 9876495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 988db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Replace the pseudo instruction with a new instruction... 989db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Opc = Old->getOpcode(); 990db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm(); 9916495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // FIXME: Thumb2 version of ADJCALLSTACKUP and ADJCALLSTACKDOWN? 992db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 993db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. 994db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned PredReg = Old->getOperand(2).getReg(); 9956495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg); 996db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } else { 997db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Note: PredReg is operand 3 for ADJCALLSTACKUP. 998db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned PredReg = Old->getOperand(3).getReg(); 999db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 10006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg); 1001db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1002db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1003db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1004db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MBB.erase(I); 1005db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1006db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1007db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// findScratchRegister - Find a 'free' ARM register. If register scavenger 1008db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// is not being used, R12 is available. Otherwise, try for a call-clobbered 1009db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// register first and then a spilled callee-saved register if that fails. 1010db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinstatic 1011db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinunsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC, 1012db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMFunctionInfo *AFI) { 1013c0823fe7c679ca8f7d1667a310c2fca97b9402d5Jakob Stoklund Olesen unsigned Reg = RS ? RS->FindUnusedReg(RC) : (unsigned) ARM::R12; 10146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(!AFI->isThumb1OnlyFunction()); 1015db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return Reg; 1016db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1017db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 10186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Chengvoid 10196495f63945e8dbde81f03a1dc2ab421993b9a495Evan ChengARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 10206495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int SPAdj, RegScavenger *RS) const { 10215ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin unsigned i = 0; 10225ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MachineInstr &MI = *II; 10235ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MachineBasicBlock &MBB = *MI.getParent(); 10245ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MachineFunction &MF = *MBB.getParent(); 1025010b1b9e7b11bced0b277a4d808226ba2af3044aEvan Cheng const MachineFrameInfo *MFI = MF.getFrameInfo(); 10265ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 10276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(!AFI->isThumb1OnlyFunction() && 10286495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "This eliminateFrameIndex does not suppor Thumb1!"); 10295ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 10305ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin while (!MI.getOperand(i).isFI()) { 10315ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin ++i; 10325ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 10335ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin } 10345ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 10355ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin unsigned FrameReg = ARM::SP; 10365ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin int FrameIndex = MI.getOperand(i).getIndex(); 1037010b1b9e7b11bced0b277a4d808226ba2af3044aEvan Cheng int Offset = MFI->getObjectOffset(FrameIndex) + MFI->getStackSize() + SPAdj; 10385ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 10395ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex)) 10405ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin Offset -= AFI->getGPRCalleeSavedArea1Offset(); 10415ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex)) 10425ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin Offset -= AFI->getGPRCalleeSavedArea2Offset(); 10435ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex)) 10445ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin Offset -= AFI->getDPRCalleeSavedAreaOffset(); 1045010b1b9e7b11bced0b277a4d808226ba2af3044aEvan Cheng else if (hasFP(MF) && AFI->hasStackFrame()) { 1046010b1b9e7b11bced0b277a4d808226ba2af3044aEvan Cheng assert(SPAdj == 0 && "Unexpected stack offset!"); 1047010b1b9e7b11bced0b277a4d808226ba2af3044aEvan Cheng // Use frame pointer to reference fixed objects unless this is a 1048010b1b9e7b11bced0b277a4d808226ba2af3044aEvan Cheng // frameless function, 10495ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin FrameReg = getFrameRegister(MF); 10505ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin Offset -= AFI->getFramePtrSpillOffset(); 10515ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin } 10525ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 10535ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin // modify MI as necessary to handle as much of 'Offset' as possible 1054cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng bool Done = false; 10556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (!AFI->isThumbFunction()) 1056cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII); 10576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng else { 10586495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(AFI->isThumb2Function()); 1059cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII); 10606495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1061cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng if (Done) 10625ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin return; 10635ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 1064db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // If we get here, the immediate doesn't fit into the instruction. We folded 1065db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // as much as possible above, handle the rest, providing a register that is 1066db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // SP+LargeImm. 106719bb87d0f80f3e6eed38a9fa267bf2b0474aeaabDaniel Dunbar assert((Offset || 106819bb87d0f80f3e6eed38a9fa267bf2b0474aeaabDaniel Dunbar (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4) && 1069cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng "This code isn't needed if offset already handled!"); 1070db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1071db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Insert a set of r12 with the full address: r12 = sp + offset 1072db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // If the offset we have is too large to fit into the instruction, we need 1073db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // to form it with a series of ADDri's. Do this by taking 8-bit chunks 1074db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // out of 'Offset'. 1075e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach unsigned ScratchReg = findScratchRegister(RS, ARM::GPRRegisterClass, AFI); 1076db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (ScratchReg == 0) 1077db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // No register is "free". Scavenge a register. 1078e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach ScratchReg = RS->scavengeRegister(ARM::GPRRegisterClass, II, SPAdj); 1079db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin int PIdx = MI.findFirstPredOperandIdx(); 1080db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMCC::CondCodes Pred = (PIdx == -1) 1081db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 1082db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 1083cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng if (Offset == 0) 1084cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng // Must be addrmode4. 1085cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false); 10866495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng else { 1087cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng if (!AFI->isThumbFunction()) 1088cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1089cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset, Pred, PredReg, TII); 1090cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng else { 1091cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng assert(AFI->isThumb2Function()); 1092cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1093cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset, Pred, PredReg, TII); 1094cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng } 1095cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); 10966495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1097db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1098db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1099db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// Move iterator pass the next bunch of callee save load / store ops for 1100db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// the particular spill area (1: integer area 1, 2: integer area 2, 1101db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// 3: fp area, 0: don't care). 1102db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinstatic void movePastCSLoadStoreOps(MachineBasicBlock &MBB, 1103db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock::iterator &MBBI, 11045ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin int Opc1, int Opc2, unsigned Area, 1105db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin const ARMSubtarget &STI) { 1106db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin while (MBBI != MBB.end() && 11075ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) && 11085ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MBBI->getOperand(1).isFI()) { 1109db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Area != 0) { 1110db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin bool Done = false; 1111db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Category = 0; 1112db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin switch (MBBI->getOperand(0).getReg()) { 1113db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: 1114db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::LR: 1115db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin Category = 1; 1116db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1117db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: 1118db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin Category = STI.isTargetDarwin() ? 2 : 1; 1119db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1120db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: 1121db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: 1122db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin Category = 3; 1123db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1124db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin default: 1125db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin Done = true; 1126db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1127db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1128db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Done || Category != Area) 1129db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1130db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1131db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1132db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ++MBBI; 1133db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1134db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1135db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1136db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinvoid ARMBaseRegisterInfo:: 1137db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinemitPrologue(MachineFunction &MF) const { 1138db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock &MBB = MF.front(); 1139db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock::iterator MBBI = MBB.begin(); 1140db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineFrameInfo *MFI = MF.getFrameInfo(); 1141db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 11426495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(!AFI->isThumb1OnlyFunction() && 11436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "This emitPrologue does not suppor Thumb1!"); 11446495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isARM = !AFI->isThumbFunction(); 1145db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1146db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned NumBytes = MFI->getStackSize(); 1147db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 1148db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin DebugLoc dl = (MBBI != MBB.end() ? 1149db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MBBI->getDebugLoc() : DebugLoc::getUnknownLoc()); 1150db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1151db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Determine the sizes of each callee-save spill areas and record which frame 1152db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // belongs to which callee-save spill areas. 1153db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 1154db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin int FramePtrSpillFI = 0; 1155db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1156db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (VARegSaveSize) 11576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize); 1158db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1159db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (!AFI->hasStackFrame()) { 1160db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (NumBytes != 0) 11616495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes); 1162db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return; 1163db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1164db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1165db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1166db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Reg = CSI[i].getReg(); 1167db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin int FI = CSI[i].getFrameIdx(); 1168db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin switch (Reg) { 1169db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R4: 1170db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R5: 1171db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R6: 1172db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R7: 1173db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::LR: 1174db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Reg == FramePtr) 1175db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin FramePtrSpillFI = FI; 1176db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->addGPRCalleeSavedArea1Frame(FI); 1177db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin GPRCS1Size += 4; 1178db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1179db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R8: 1180db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R9: 1181db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R10: 1182db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin case ARM::R11: 1183db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Reg == FramePtr) 1184db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin FramePtrSpillFI = FI; 1185db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (STI.isTargetDarwin()) { 1186db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->addGPRCalleeSavedArea2Frame(FI); 1187db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin GPRCS2Size += 4; 1188db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } else { 1189db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->addGPRCalleeSavedArea1Frame(FI); 1190db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin GPRCS1Size += 4; 1191db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1192db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin break; 1193db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin default: 1194db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->addDPRCalleeSavedAreaFrame(FI); 1195db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin DPRCSSize += 8; 1196db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1197db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1198db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1199db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Build the new SUBri to adjust SP for integer callee-save spill area 1. 12006495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size); 12015732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI); 1202db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1203db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Darwin ABI requires FP to point to the stack slot that contains the 1204db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // previous FP. 1205db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (STI.isTargetDarwin() || hasFP(MF)) { 12066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri; 1207db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineInstrBuilder MIB = 12086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr) 1209db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin .addFrameIndex(FramePtrSpillFI).addImm(0); 1210db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AddDefaultCC(AddDefaultPred(MIB)); 1211db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1212db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1213db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Build the new SUBri to adjust SP for integer callee-save spill area 2. 12146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size); 1215db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1216db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Build the new SUBri to adjust SP for FP callee-save spill area. 12175732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI); 12186495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize); 1219db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1220db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Determine starting offsets of spill areas. 1221db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 1222db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 1223db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 1224db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); 1225db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 1226db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 1227db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 1228db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1229db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin NumBytes = DPRCSOffset; 1230db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (NumBytes) { 1231db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Insert it after all the callee-save spills. 1232b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 0, 3, STI); 12336495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes); 1234db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1235db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1236db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (STI.isTargetELF() && hasFP(MF)) { 1237db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 1238db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->getFramePtrSpillOffset()); 1239db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1240db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1241db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 1242db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 1243db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 1244db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1245db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1246db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinstatic bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 1247db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin for (unsigned i = 0; CSRegs[i]; ++i) 1248db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Reg == CSRegs[i]) 1249db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return true; 1250db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return false; 1251db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1252db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 125377521f5232e679aa3de10aaaed2464aa91d7ff55David Goodwinstatic bool isCSRestore(MachineInstr *MI, 1254764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach const ARMBaseInstrInfo &TII, 125577521f5232e679aa3de10aaaed2464aa91d7ff55David Goodwin const unsigned *CSRegs) { 1256b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng return ((MI->getOpcode() == (int)ARM::FLDD || 12575732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng MI->getOpcode() == (int)ARM::LDR || 12585732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng MI->getOpcode() == (int)ARM::t2LDRi12) && 1259db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MI->getOperand(1).isFI() && 1260db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); 1261db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1262db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1263db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinvoid ARMBaseRegisterInfo:: 1264293f8d9b8800ab68c64b67f38a7f76e00126715dEvan ChengemitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { 1265db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock::iterator MBBI = prior(MBB.end()); 12665ca53a7ad821613d324e4189ddbb0d468a326146Evan Cheng assert(MBBI->getDesc().isReturn() && 1267db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin "Can only insert epilog into returning blocks"); 1268db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin DebugLoc dl = MBBI->getDebugLoc(); 1269db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineFrameInfo *MFI = MF.getFrameInfo(); 1270db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 12716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(!AFI->isThumb1OnlyFunction() && 12726495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng "This emitEpilogue does not suppor Thumb1!"); 12736495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isARM = !AFI->isThumbFunction(); 12746495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 1275db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 1276db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin int NumBytes = (int)MFI->getStackSize(); 1277db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1278db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (!AFI->hasStackFrame()) { 1279db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (NumBytes != 0) 12806495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 1281db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } else { 1282db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Unwind MBBI to point to first LDR / FLDD. 1283db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin const unsigned *CSRegs = getCalleeSavedRegs(); 1284db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (MBBI != MBB.begin()) { 1285db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin do 1286db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin --MBBI; 128777521f5232e679aa3de10aaaed2464aa91d7ff55David Goodwin while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs)); 128877521f5232e679aa3de10aaaed2464aa91d7ff55David Goodwin if (!isCSRestore(MBBI, TII, CSRegs)) 1289db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ++MBBI; 1290db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1291db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1292db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Move SP to start of FP callee save spill area. 1293db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 1294db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->getGPRCalleeSavedArea2Size() + 1295db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->getDPRCalleeSavedAreaSize()); 1296db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1297db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Darwin ABI requires FP to point to the stack slot that contains the 1298db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // previous FP. 1299010b1b9e7b11bced0b277a4d808226ba2af3044aEvan Cheng bool HasFP = hasFP(MF); 1300010b1b9e7b11bced0b277a4d808226ba2af3044aEvan Cheng if ((STI.isTargetDarwin() && NumBytes) || HasFP) { 1301db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 1302db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Reset SP based on frame pointer only if the stack frame extends beyond 1303db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // frame pointer stack slot or target is ELF and the function has FP. 1304010b1b9e7b11bced0b277a4d808226ba2af3044aEvan Cheng if (HasFP || 1305010b1b9e7b11bced0b277a4d808226ba2af3044aEvan Cheng AFI->getGPRCalleeSavedArea2Size() || 1306db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin AFI->getDPRCalleeSavedAreaSize() || 1307010b1b9e7b11bced0b277a4d808226ba2af3044aEvan Cheng AFI->getDPRCalleeSavedAreaOffset()) { 13086495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (NumBytes) { 1309861986401e05e437cb33bfd8320d510b956fe41eEvan Cheng if (isARM) 1310861986401e05e437cb33bfd8320d510b956fe41eEvan Cheng emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, 1311861986401e05e437cb33bfd8320d510b956fe41eEvan Cheng ARMCC::AL, 0, TII); 1312861986401e05e437cb33bfd8320d510b956fe41eEvan Cheng else 1313861986401e05e437cb33bfd8320d510b956fe41eEvan Cheng emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, 1314861986401e05e437cb33bfd8320d510b956fe41eEvan Cheng ARMCC::AL, 0, TII); 13156495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else { 13166495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng // Thumb2 or ARM. 1317764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach if (isARM) 1318052053bbe3169a3574cb5af026cf0a5d616ae04dEvan Cheng BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) 1319052053bbe3169a3574cb5af026cf0a5d616ae04dEvan Cheng .addReg(FramePtr) 1320052053bbe3169a3574cb5af026cf0a5d616ae04dEvan Cheng .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 1321052053bbe3169a3574cb5af026cf0a5d616ae04dEvan Cheng else 1322052053bbe3169a3574cb5af026cf0a5d616ae04dEvan Cheng BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP) 1323052053bbe3169a3574cb5af026cf0a5d616ae04dEvan Cheng .addReg(FramePtr); 13246495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1325db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 13266495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } else if (NumBytes) 13276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 1328db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1329db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Move SP to start of integer callee save spill area 2. 1330b74bb1a7a471a77e793d90de158aa4bbc67fe94dEvan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 0, 3, STI); 13316495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize()); 1332db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1333db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Move SP to start of integer callee save spill area 1. 13345732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI); 13356495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size()); 1336db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1337db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Move SP to SP upon entry to the function. 13385732ca084aaa0cd26149e50dd4b487efff37fe41Evan Cheng movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI); 13396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size()); 1340db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 1341db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1342db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (VARegSaveSize) 13436495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize); 1344db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1345db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 1346c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMGenRegisterInfo.inc" 1347