ARMBaseRegisterInfo.cpp revision e837dead3c8dc3445ef6a0e2322179c57e264a13
12cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattner//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===// 2c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 3c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// The LLVM Compiler Infrastructure 4c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 5c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// This file is distributed under the University of Illinois Open Source 6c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// License. See LICENSE.TXT for details. 7c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 8c140c4803dc3e10e08138670829bc0494986abe9David Goodwin//===----------------------------------------------------------------------===// 9c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 10c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// This file contains the base ARM implementation of TargetRegisterInfo class. 11c140c4803dc3e10e08138670829bc0494986abe9David Goodwin// 12c140c4803dc3e10e08138670829bc0494986abe9David Goodwin//===----------------------------------------------------------------------===// 13c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 14c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARM.h" 15c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMAddressingModes.h" 16db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin#include "ARMBaseInstrInfo.h" 17c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMBaseRegisterInfo.h" 1816c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov#include "ARMFrameLowering.h" 19c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMInstrInfo.h" 20c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMMachineFunctionInfo.h" 21c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "ARMSubtarget.h" 22c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/Constants.h" 23c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/DerivedTypes.h" 249adc0abad3c3ed40a268ccbcee0c74cb9e1359feOwen Anderson#include "llvm/Function.h" 259adc0abad3c3ed40a268ccbcee0c74cb9e1359feOwen Anderson#include "llvm/LLVMContext.h" 26c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineConstantPool.h" 27c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineFrameInfo.h" 28c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineFunction.h" 29c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineInstrBuilder.h" 30c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineLocation.h" 31c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/MachineRegisterInfo.h" 32c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/CodeGen/RegisterScavenging.h" 333dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach#include "llvm/Support/Debug.h" 34ab7c09b6b6f4516a631fd6788918c237c83939afTorok Edwin#include "llvm/Support/ErrorHandling.h" 35dac237e18209b697a8ba122d0ddd9cad4dfba1f8Torok Edwin#include "llvm/Support/raw_ostream.h" 3616c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov#include "llvm/Target/TargetFrameLowering.h" 37c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/Target/TargetMachine.h" 38c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/Target/TargetOptions.h" 39c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/ADT/BitVector.h" 40c140c4803dc3e10e08138670829bc0494986abe9David Goodwin#include "llvm/ADT/SmallVector.h" 4118ed9c9a2bd7f1f56129495b499264c58b5cc4f4Jim Grosbach#include "llvm/Support/CommandLine.h" 4273f50d9bc3bd46cc0abeba9bb0d46977ba1aea42Evan Cheng 4373f50d9bc3bd46cc0abeba9bb0d46977ba1aea42Evan Cheng#define GET_REGINFO_MC_DESC 4473f50d9bc3bd46cc0abeba9bb0d46977ba1aea42Evan Cheng#define GET_REGINFO_TARGET_DESC 45a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng#include "ARMGenRegisterInfo.inc" 46c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 471b4886dd00578038c0ca70b3bab97382b89def26Evan Chengusing namespace llvm; 481b4886dd00578038c0ca70b3bab97382b89def26Evan Cheng 49a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbachstatic cl::opt<bool> 503197380143cdc18837722129ac888528b9fbfc2bJim GrosbachForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false), 51cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach cl::desc("Force use of virtual base registers for stack load/store")); 52a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbachstatic cl::opt<bool> 53ae47c6d69e2e34bc558a302586cbc3f27a6d7334Jim GrosbachEnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden, 54a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach cl::desc("Enable pre-regalloc stack frame index allocation")); 5565482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbachstatic cl::opt<bool> 56d0bd76b0fb27830f18e15e3d73f2e383ff1c59f1Jim GrosbachEnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true), 5765482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach cl::desc("Enable use of a base pointer for complex stack frames")); 5865482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach 59db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, 60c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const ARMSubtarget &sti) 61a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng : ARMGenRegisterInfo(ARMRegDesc, ARMRegInfoDesc, 62a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), 63c140c4803dc3e10e08138670829bc0494986abe9David Goodwin TII(tii), STI(sti), 6465482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), 6565482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach BasePtr(ARM::R6) { 66c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 67c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 68c140c4803dc3e10e08138670829bc0494986abe9David Goodwinconst unsigned* 69c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 70c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned CalleeSavedRegs[] = { 71c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, 72c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R7, ARM::R6, ARM::R5, ARM::R4, 73c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 74c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::D15, ARM::D14, ARM::D13, ARM::D12, 75c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::D11, ARM::D10, ARM::D9, ARM::D8, 76c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 0 77c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 78c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 79c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned DarwinCalleeSavedRegs[] = { 80c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved 81c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // register. 82ab3d00e5350fd4c097e2a5b077da7584692029a7Jim Grosbach ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, 83ab3d00e5350fd4c097e2a5b077da7584692029a7Jim Grosbach ARM::R11, ARM::R10, ARM::R8, 84c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 85c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::D15, ARM::D14, ARM::D13, ARM::D12, 86c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::D11, ARM::D10, ARM::D9, ARM::D8, 87c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 0 88c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 89c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; 90c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 91c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 929631864688c593711f82bb8d21f8b724c628d786Jim GrosbachBitVector ARMBaseRegisterInfo:: 939631864688c593711f82bb8d21f8b724c628d786Jim GrosbachgetReservedRegs(const MachineFunction &MF) const { 9416c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 95d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov 967a2bdde0a0eebcd2125055e0eacaca040f0b766cChris Lattner // FIXME: avoid re-calculating this every time. 97c140c4803dc3e10e08138670829bc0494986abe9David Goodwin BitVector Reserved(getNumRegs()); 98c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(ARM::SP); 99c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(ARM::PC); 100d1fb583128c6682bb8a7c74eafa810a9270cc8dfNate Begeman Reserved.set(ARM::FPSCR); 101d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov if (TFI->hasFP(MF)) 102c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(FramePtr); 10365482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach if (hasBasePointer(MF)) 10465482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach Reserved.set(BasePtr); 105c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Some targets reserve R9. 106c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (STI.isR9Reserved()) 107c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Reserved.set(ARM::R9); 1083b6434e360315849a65b1ac85e16d160131a77a4Jakob Stoklund Olesen // Reserve D16-D31 if the subtarget doesn't support them. 1093b6434e360315849a65b1ac85e16d160131a77a4Jakob Stoklund Olesen if (!STI.hasVFP3() || STI.hasD16()) { 1103b6434e360315849a65b1ac85e16d160131a77a4Jakob Stoklund Olesen assert(ARM::D31 == ARM::D16 + 15); 1113b6434e360315849a65b1ac85e16d160131a77a4Jakob Stoklund Olesen for (unsigned i = 0; i != 16; ++i) 1123b6434e360315849a65b1ac85e16d160131a77a4Jakob Stoklund Olesen Reserved.set(ARM::D16 + i); 1133b6434e360315849a65b1ac85e16d160131a77a4Jakob Stoklund Olesen } 114c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return Reserved; 115c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 116c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1172cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattnerbool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF, 1182cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattner unsigned Reg) const { 11916c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 120d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov 121c140c4803dc3e10e08138670829bc0494986abe9David Goodwin switch (Reg) { 122c140c4803dc3e10e08138670829bc0494986abe9David Goodwin default: break; 123c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::SP: 124c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::PC: 125c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return true; 12665482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach case ARM::R6: 12765482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach if (hasBasePointer(MF)) 12865482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach return true; 12965482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach break; 130c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R7: 131c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R11: 132d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov if (FramePtr == Reg && TFI->hasFP(MF)) 133c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return true; 134c140c4803dc3e10e08138670829bc0494986abe9David Goodwin break; 135c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R9: 136c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return STI.isR9Reserved(); 137c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 138c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 139c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return false; 140c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 141c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 1422cfd52c507bd5790457a171eb9bcb39019cc6860Chris Lattnerconst TargetRegisterClass * 1434f54c1293af174a8002db20faf7b4f82ba4e8514Evan ChengARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, 1444f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng const TargetRegisterClass *B, 1454f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng unsigned SubIdx) const { 1464f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng switch (SubIdx) { 1474f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng default: return 0; 148e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::ssub_0: 149e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::ssub_1: 150e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::ssub_2: 151e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::ssub_3: { 1524f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng // S sub-registers. 1534f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng if (A->getSize() == 8) { 154ba908640b3e0c1218748776e244d4b7234451155Evan Cheng if (B == &ARM::SPR_8RegClass) 155ba908640b3e0c1218748776e244d4b7234451155Evan Cheng return &ARM::DPR_8RegClass; 156ba908640b3e0c1218748776e244d4b7234451155Evan Cheng assert(B == &ARM::SPRRegClass && "Expecting SPR register class!"); 1574f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng if (A == &ARM::DPR_8RegClass) 1584f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng return A; 1594f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng return &ARM::DPR_VFP2RegClass; 1604f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng } 1614f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng 162b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng if (A->getSize() == 16) { 163b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng if (B == &ARM::SPR_8RegClass) 164b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng return &ARM::QPR_8RegClass; 165b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng return &ARM::QPR_VFP2RegClass; 166b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng } 167b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng 16822c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (A->getSize() == 32) { 16922c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (B == &ARM::SPR_8RegClass) 17022c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return 0; // Do not allow coalescing! 17122c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return &ARM::QQPR_VFP2RegClass; 17222c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng } 17322c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng 17422c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng assert(A->getSize() == 64 && "Expecting a QQQQ register class!"); 17522c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return 0; // Do not allow coalescing! 176b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng } 177e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::dsub_0: 178e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::dsub_1: 179e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::dsub_2: 180e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::dsub_3: { 1814f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng // D sub-registers. 182b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng if (A->getSize() == 16) { 183b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng if (B == &ARM::DPR_VFP2RegClass) 184b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng return &ARM::QPR_VFP2RegClass; 185b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng if (B == &ARM::DPR_8RegClass) 18622c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return 0; // Do not allow coalescing! 187b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng return A; 188b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng } 189b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng 19022c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (A->getSize() == 32) { 19122c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (B == &ARM::DPR_VFP2RegClass) 19222c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return &ARM::QQPR_VFP2RegClass; 19322c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (B == &ARM::DPR_8RegClass) 19422c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return 0; // Do not allow coalescing! 19522c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return A; 19622c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng } 19722c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng 19822c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng assert(A->getSize() == 64 && "Expecting a QQQQ register class!"); 19922c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (B != &ARM::DPRRegClass) 20022c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return 0; // Do not allow coalescing! 2014f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng return A; 2024f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng } 203e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::dsub_4: 204e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::dsub_5: 205e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::dsub_6: 206e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::dsub_7: { 20722c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // D sub-registers of QQQQ registers. 20822c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (A->getSize() == 64 && B == &ARM::DPRRegClass) 20922c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return A; 21022c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return 0; // Do not allow coalescing! 21122c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng } 21222c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng 213e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::qsub_0: 214e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::qsub_1: { 215b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng // Q sub-registers. 21622c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (A->getSize() == 32) { 21722c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (B == &ARM::QPR_VFP2RegClass) 21822c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return &ARM::QQPR_VFP2RegClass; 21922c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (B == &ARM::QPR_8RegClass) 22022c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return 0; // Do not allow coalescing! 22122c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return A; 22222c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng } 22322c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng 22422c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng assert(A->getSize() == 64 && "Expecting a QQQQ register class!"); 22522c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (B == &ARM::QPRRegClass) 22622c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return A; 22722c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return 0; // Do not allow coalescing! 22822c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng } 229e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::qsub_2: 230e00fa64c16f40230d76417be8f09166b7c84c52dJakob Stoklund Olesen case ARM::qsub_3: { 23122c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng // Q sub-registers of QQQQ registers. 23222c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng if (A->getSize() == 64 && B == &ARM::QPRRegClass) 23322c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return A; 23422c687b6421d9cc03351ddb0c7fd3d45382bc01aEvan Cheng return 0; // Do not allow coalescing! 235b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng } 236b63387afc6b10e88631d1ef232c41ab6c18c8581Evan Cheng } 2374f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng return 0; 2384f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng} 2394f54c1293af174a8002db20faf7b4f82ba4e8514Evan Cheng 240b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Chengbool 24191a74da036d3a9442953ae1de3e797a50da4ccf0Bob WilsonARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC, 242b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng SmallVectorImpl<unsigned> &SubIndices, 243b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng unsigned &NewSubIdx) const { 244b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng 245b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng unsigned Size = RC->getSize() * 8; 246b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (Size < 6) 247b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return 0; 248b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng 249b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng NewSubIdx = 0; // Whole register. 250b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng unsigned NumRegs = SubIndices.size(); 251b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (NumRegs == 8) { 252b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 8 D registers -> 1 QQQQ register. 253b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return (Size == 512 && 254558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[0] == ARM::dsub_0 && 255558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[1] == ARM::dsub_1 && 256558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[2] == ARM::dsub_2 && 257558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[3] == ARM::dsub_3 && 258558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[4] == ARM::dsub_4 && 259558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[5] == ARM::dsub_5 && 260558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[6] == ARM::dsub_6 && 261558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[7] == ARM::dsub_7); 262b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } else if (NumRegs == 4) { 263558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (SubIndices[0] == ARM::qsub_0) { 264b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 4 Q registers -> 1 QQQQ register. 265b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return (Size == 512 && 266558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[1] == ARM::qsub_1 && 267558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[2] == ARM::qsub_2 && 268558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[3] == ARM::qsub_3); 269558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::dsub_0) { 270b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 4 D registers -> 1 QQ register. 271b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (Size >= 256 && 272558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[1] == ARM::dsub_1 && 273558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[2] == ARM::dsub_2 && 274558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[3] == ARM::dsub_3) { 275b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (Size == 512) 276558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::qqsub_0; 277b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 278b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 279558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::dsub_4) { 280b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 4 D registers -> 1 QQ register (2nd). 281b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (Size == 512 && 282558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[1] == ARM::dsub_5 && 283558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[2] == ARM::dsub_6 && 284558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[3] == ARM::dsub_7) { 285558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::qqsub_1; 286b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 287b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 288558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::ssub_0) { 289b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 4 S registers -> 1 Q register. 290b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (Size >= 128 && 291558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[1] == ARM::ssub_1 && 292558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[2] == ARM::ssub_2 && 293558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen SubIndices[3] == ARM::ssub_3) { 294b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (Size >= 256) 295558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::qsub_0; 296b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 297b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 298b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 299b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } else if (NumRegs == 2) { 300558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (SubIndices[0] == ARM::qsub_0) { 301b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 2 Q registers -> 1 QQ register. 302558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (Size >= 256 && SubIndices[1] == ARM::qsub_1) { 303b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (Size == 512) 304558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::qqsub_0; 305b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 306b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 307558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::qsub_2) { 308b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 2 Q registers -> 1 QQ register (2nd). 309558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (Size == 512 && SubIndices[1] == ARM::qsub_3) { 310558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::qqsub_1; 311b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 312b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 313558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::dsub_0) { 314b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 2 D registers -> 1 Q register. 315558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (Size >= 128 && SubIndices[1] == ARM::dsub_1) { 316b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (Size >= 256) 317558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::qsub_0; 318b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 319b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 320558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::dsub_2) { 321b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 2 D registers -> 1 Q register (2nd). 322558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (Size >= 256 && SubIndices[1] == ARM::dsub_3) { 323558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::qsub_1; 324b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 325b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 326558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::dsub_4) { 327b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 2 D registers -> 1 Q register (3rd). 328558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (Size == 512 && SubIndices[1] == ARM::dsub_5) { 329558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::qsub_2; 330b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 331b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 332558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::dsub_6) { 333b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 2 D registers -> 1 Q register (3rd). 334558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (Size == 512 && SubIndices[1] == ARM::dsub_7) { 335558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::qsub_3; 336b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 337b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 338558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::ssub_0) { 339b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 2 S registers -> 1 D register. 340558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (SubIndices[1] == ARM::ssub_1) { 341b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng if (Size >= 128) 342558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::dsub_0; 343b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 344b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 345558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen } else if (SubIndices[0] == ARM::ssub_2) { 346b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng // 2 S registers -> 1 D register (2nd). 347558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen if (Size >= 128 && SubIndices[1] == ARM::ssub_3) { 348558661d2718cf5750907c449d36ff1231924a2d1Jakob Stoklund Olesen NewSubIdx = ARM::dsub_1; 349b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return true; 350b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 351b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 352b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng } 353b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng return false; 354b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng} 355b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng 356c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesenconst TargetRegisterClass* 357c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund OlesenARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) 358c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen const { 359c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen const TargetRegisterClass *Super = RC; 360c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen TargetRegisterClass::sc_iterator I = RC->superclasses_begin(); 361c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen do { 362c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen switch (Super->getID()) { 363c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::GPRRegClassID: 364c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::SPRRegClassID: 365c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::DPRRegClassID: 366c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::QPRRegClassID: 367c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::QQPRRegClassID: 368c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen case ARM::QQQQPRRegClassID: 369c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen return Super; 370c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen } 371c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen Super = *I++; 372c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen } while (Super); 373c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen return RC; 374c9e5015dece0a1a73bec358e11bc87594831279dJakob Stoklund Olesen} 375b990a2f249196ad3e0cc451d40a45fc2f9278eafEvan Cheng 3764f54c1293af174a8002db20faf7b4f82ba4e8514Evan Chengconst TargetRegisterClass * 3772cfd52c507bd5790457a171eb9bcb39019cc6860Chris LattnerARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const { 378e11a8f565c6a019ddc54667227be9c4d8f117473Jim Grosbach return ARM::GPRRegisterClass; 379c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 380be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich 381be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarichunsigned 382be2119e8e2bc7006cfd638a24367acbfda625d16Cameron ZwarichARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 383be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich MachineFunction &MF) const { 384be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 385be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich 386be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich switch (RC->getID()) { 387be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich default: 388be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich return 0; 389be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich case ARM::tGPRRegClassID: 390be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich return TFI->hasFP(MF) ? 4 : 5; 391be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich case ARM::GPRRegClassID: { 392be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich unsigned FP = TFI->hasFP(MF) ? 1 : 0; 393be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich return 10 - FP - (STI.isR9Reserved() ? 1 : 0); 394be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich } 395be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich case ARM::SPRRegClassID: // Currently not used as 'rep' register class. 396be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich case ARM::DPRRegClassID: 397be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich return 32 - 10; 398be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich } 399be2119e8e2bc7006cfd638a24367acbfda625d16Cameron Zwarich} 400c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 401dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen/// getRawAllocationOrder - Returns the register allocation order for a 402dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen/// specified register class with a target-dependent hint. 403dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund OlesenArrayRef<unsigned> 404dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund OlesenARMBaseRegisterInfo::getRawAllocationOrder(const TargetRegisterClass *RC, 405dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen unsigned HintType, unsigned HintReg, 406dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen const MachineFunction &MF) const { 40716c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 408c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Alternative register allocation orders when favoring even / odd registers 409c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // of register pairs. 410c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 411c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // No FP, R9 is available. 412c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven1[] = { 413c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, 414c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, 415c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R9, ARM::R11 416c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 417c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd1[] = { 418c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11, 419c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 420c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R8, ARM::R10 421c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 422c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 423c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // FP is R7, R9 is available. 424c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven2[] = { 425c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10, 426c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, 427c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R9, ARM::R11 428c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 429c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd2[] = { 430c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11, 431c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 432c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R8, ARM::R10 433c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 434c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 435c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // FP is R11, R9 is available. 436c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven3[] = { 437c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, 438c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, 439c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R9 440c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 441c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd3[] = { 442c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9, 443c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7, 444c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R8 445c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 446c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 447c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // No FP, R9 is not available. 448c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven4[] = { 449c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10, 450c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8, 451c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R11 452c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 453c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd4[] = { 454c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11, 455c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 456c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R10 457c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 458c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 459c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // FP is R7, R9 is not available. 460c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven5[] = { 461c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R10, 462c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8, 463c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R11 464c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 465c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd5[] = { 466c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R11, 467c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 468c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R10 469c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 470c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 471c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // FP is R11, R9 is not available. 472c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPREven6[] = { 473c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R4, ARM::R6, 474c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8 475c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 476c140c4803dc3e10e08138670829bc0494986abe9David Goodwin static const unsigned GPROdd6[] = { 477c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R1, ARM::R3, ARM::R5, ARM::R7, 478c140c4803dc3e10e08138670829bc0494986abe9David Goodwin ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8 479c140c4803dc3e10e08138670829bc0494986abe9David Goodwin }; 480c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 481eb5067e0d9ca182f21db24949b63616ce4bb1eafJakob Stoklund Olesen // We only support even/odd hints for GPR and rGPR. 482eb5067e0d9ca182f21db24949b63616ce4bb1eafJakob Stoklund Olesen if (RC != ARM::GPRRegisterClass && RC != ARM::rGPRRegisterClass) 483dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen return RC->getRawAllocationOrder(MF); 484c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 485c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (HintType == ARMRI::RegPairEven) { 486c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0) 487c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // It's no longer possible to fulfill this hint. Return the default 488c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // allocation order. 489dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen return RC->getRawAllocationOrder(MF); 490c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 491d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov if (!TFI->hasFP(MF)) { 492c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 493e1fd84af7affc08cda70a4c8261f52ac83195bc4Jakob Stoklund Olesen return ArrayRef<unsigned>(GPREven1); 494c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 495e1fd84af7affc08cda70a4c8261f52ac83195bc4Jakob Stoklund Olesen return ArrayRef<unsigned>(GPREven4); 496c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else if (FramePtr == ARM::R7) { 497c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 498e1fd84af7affc08cda70a4c8261f52ac83195bc4Jakob Stoklund Olesen return ArrayRef<unsigned>(GPREven2); 499c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 500e1fd84af7affc08cda70a4c8261f52ac83195bc4Jakob Stoklund Olesen return ArrayRef<unsigned>(GPREven5); 501c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else { // FramePtr == ARM::R11 502c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 503e1fd84af7affc08cda70a4c8261f52ac83195bc4Jakob Stoklund Olesen return ArrayRef<unsigned>(GPREven3); 504c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 505e1fd84af7affc08cda70a4c8261f52ac83195bc4Jakob Stoklund Olesen return ArrayRef<unsigned>(GPREven6); 506c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 507c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else if (HintType == ARMRI::RegPairOdd) { 508c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0) 509c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // It's no longer possible to fulfill this hint. Return the default 510c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // allocation order. 511dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen return RC->getRawAllocationOrder(MF); 512c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 513d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov if (!TFI->hasFP(MF)) { 514c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 515e1fd84af7affc08cda70a4c8261f52ac83195bc4Jakob Stoklund Olesen return ArrayRef<unsigned>(GPROdd1); 516c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 517e1fd84af7affc08cda70a4c8261f52ac83195bc4Jakob Stoklund Olesen return ArrayRef<unsigned>(GPROdd4); 518c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else if (FramePtr == ARM::R7) { 519c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 520e1fd84af7affc08cda70a4c8261f52ac83195bc4Jakob Stoklund Olesen return ArrayRef<unsigned>(GPROdd2); 521c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 522e1fd84af7affc08cda70a4c8261f52ac83195bc4Jakob Stoklund Olesen return ArrayRef<unsigned>(GPROdd5); 523c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } else { // FramePtr == ARM::R11 524c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (!STI.isR9Reserved()) 525e1fd84af7affc08cda70a4c8261f52ac83195bc4Jakob Stoklund Olesen return ArrayRef<unsigned>(GPROdd3); 526c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else 527e1fd84af7affc08cda70a4c8261f52ac83195bc4Jakob Stoklund Olesen return ArrayRef<unsigned>(GPROdd6); 528c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 529c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 530dd5a8471526ceadf9bceb1a1221299b3db49c33aJakob Stoklund Olesen return RC->getRawAllocationOrder(MF); 531c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 532c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 533c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// ResolveRegAllocHint - Resolves the specified register allocation hint 534c140c4803dc3e10e08138670829bc0494986abe9David Goodwin/// to a physical register. Returns the physical register if it is successful. 535c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned 536c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg, 537c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const MachineFunction &MF) const { 538c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (Reg == 0 || !isPhysicalRegister(Reg)) 539c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 540c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (Type == 0) 541c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return Reg; 542c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else if (Type == (unsigned)ARMRI::RegPairOdd) 543c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Odd register. 544c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return getRegisterPairOdd(Reg, MF); 545c140c4803dc3e10e08138670829bc0494986abe9David Goodwin else if (Type == (unsigned)ARMRI::RegPairEven) 546c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Even register. 547c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return getRegisterPairEven(Reg, MF); 548c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 549c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 550c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 551c140c4803dc3e10e08138670829bc0494986abe9David Goodwinvoid 552c140c4803dc3e10e08138670829bc0494986abe9David GoodwinARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 553c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MachineFunction &MF) const { 554c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MachineRegisterInfo *MRI = &MF.getRegInfo(); 555c140c4803dc3e10e08138670829bc0494986abe9David Goodwin std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 556c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 557c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Hint.first == (unsigned)ARMRI::RegPairEven) && 558c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen TargetRegisterInfo::isVirtualRegister(Hint.second)) { 559c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // If 'Reg' is one of the even / odd register pair and it's now changed 560c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // (e.g. coalesced) into a different register. The other register of the 561c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // pair allocation hint must be updated to reflect the relationship 562c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // change. 563c140c4803dc3e10e08138670829bc0494986abe9David Goodwin unsigned OtherReg = Hint.second; 564c140c4803dc3e10e08138670829bc0494986abe9David Goodwin Hint = MRI->getRegAllocationHint(OtherReg); 565c140c4803dc3e10e08138670829bc0494986abe9David Goodwin if (Hint.second == Reg) 566c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Make sure the pair has not already divorced. 567c140c4803dc3e10e08138670829bc0494986abe9David Goodwin MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 568c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 569c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 570f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson 571f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilsonbool 572f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob WilsonARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 573f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson // CortexA9 has a Write-after-write hazard for NEON registers. 574f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson if (!STI.isCortexA9()) 575f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson return false; 576f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson 577f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson switch (RC->getID()) { 578f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson case ARM::DPRRegClassID: 579f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson case ARM::DPR_8RegClassID: 580f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson case ARM::DPR_VFP2RegClassID: 581f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson case ARM::QPRRegClassID: 582f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson case ARM::QPR_8RegClassID: 583f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson case ARM::QPR_VFP2RegClassID: 584f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson case ARM::SPRRegClassID: 585f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson case ARM::SPR_8RegClassID: 586f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson // Avoid reusing S, D, and Q registers. 587f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson // Don't increase register pressure for QQ and QQQQ. 588f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson return true; 589f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson default: 590f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson return false; 591f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson } 592f6a4d3c2f3e1029af252a0f6999edfa3c2f326eeBob Wilson} 593c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 59465482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbachbool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 5956a8700301ca6f8f2f5f787c8d1f5206a7dfceed6Daniel Dunbar const MachineFrameInfo *MFI = MF.getFrameInfo(); 5961755b3964f931bdd6fa9b4c0138f666ccfa12acaJim Grosbach const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 59765482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach 59865482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach if (!EnableBasePointer) 59965482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach return false; 60065482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach 60165482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach if (needsStackRealignment(MF) && MFI->hasVarSizedObjects()) 60265482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach return true; 60365482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach 60465482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited 60565482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // negative range for ldr/str (255), and thumb1 is positive offsets only. 60665482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // It's going to be better to use the SP or Base Pointer instead. When there 60765482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // are variable sized objects, we can't reference off of the SP, so we 60865482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // reserve a Base Pointer. 60965482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) { 61065482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // Conservatively estimate whether the negative offset from the frame 61165482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // pointer will be sufficient to reach. If a function has a smallish 61265482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // frame, it's less likely to have lots of spills and callee saved 61365482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // space, so it's all more likely to be within range of the frame pointer. 61465482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // If it's wrong, the scavenger will still enable access to work, it just 61565482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach // won't be optimal. 61665482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128) 61765482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach return false; 61865482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach return true; 61965482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach } 62065482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach 62165482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach return false; 62265482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach} 62365482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach 62465482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbachbool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { 62530c93e1cd3e43e174994834900325fcff3322288Jim Grosbach const MachineFrameInfo *MFI = MF.getFrameInfo(); 62665482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 62730c93e1cd3e43e174994834900325fcff3322288Jim Grosbach // We can't realign the stack if: 62830c93e1cd3e43e174994834900325fcff3322288Jim Grosbach // 1. Dynamic stack realignment is explicitly disabled, 62930c93e1cd3e43e174994834900325fcff3322288Jim Grosbach // 2. This is a Thumb1 function (it's not useful, so we don't bother), or 63030c93e1cd3e43e174994834900325fcff3322288Jim Grosbach // 3. There are VLAs in the function and the base pointer is disabled. 63130c93e1cd3e43e174994834900325fcff3322288Jim Grosbach return (RealignStack && !AFI->isThumb1OnlyFunction() && 63230c93e1cd3e43e174994834900325fcff3322288Jim Grosbach (!MFI->hasVarSizedObjects() || EnableBasePointer)); 633e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3Jim Grosbach} 634e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3Jim Grosbach 6353dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbachbool ARMBaseRegisterInfo:: 6363dab2778571b5bb00b35a0adcb7011dc85158bebJim GrosbachneedsStackRealignment(const MachineFunction &MF) const { 6373dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach const MachineFrameInfo *MFI = MF.getFrameInfo(); 638d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher const Function *F = MF.getFunction(); 63916c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 640fc633002339439339e94f83eca9a012c6fc51e50Jim Grosbach bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) || 641697cba8ec2b3f5160175fd5b4a641dbd48606e17Eric Christopher F->hasFnAttr(Attribute::StackAlignment)); 6425c33f5bf67f61e3a1addda6de735d28d550dd0ebJim Grosbach 643d4c36cec1db81b4ee48cd4ab462262615d78f22cEric Christopher return requiresRealignment && canRealignStack(MF); 6443dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach} 6453dab2778571b5bb00b35a0adcb7011dc85158bebJim Grosbach 6469631864688c593711f82bb8d21f8b724c628d786Jim Grosbachbool ARMBaseRegisterInfo:: 6479631864688c593711f82bb8d21f8b724c628d786Jim GrosbachcannotEliminateFrame(const MachineFunction &MF) const { 64898a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng const MachineFrameInfo *MFI = MF.getFrameInfo(); 649b92187a4103dca24c3767c380f63593d1f6161a7Bill Wendling if (DisableFramePointerElim(MF) && MFI->adjustsStack()) 65098a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng return true; 65131bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() 65231bc849123011b8eae6bb3c79876d9a3c26a6a1dJim Grosbach || needsStackRealignment(MF); 65398a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng} 65498a0104014e9bb6ed89c2572f615351fd526674aEvan Cheng 655c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getRARegister() const { 656c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::LR; 657c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 658c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 6595c33f5bf67f61e3a1addda6de735d28d550dd0ebJim Grosbachunsigned 6603f2bf85d14759cc4b28a86805f566ac805a54d00David GreeneARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 66116c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 662d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov 663d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov if (TFI->hasFP(MF)) 664c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return FramePtr; 665c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::SP; 666c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 667c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 668c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { 669c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("What is the exception register"); 670c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 671c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 672c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 673c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { 674c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("What is the exception handler register"); 675c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 676c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 677c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 678c140c4803dc3e10e08138670829bc0494986abe9David Goodwinint ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 679c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 680c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 681c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 6826e032942cf58d1c41f88609a1cec74eb74940ecdRafael Espindolaint ARMBaseRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const { 6836e032942cf58d1c41f88609a1cec74eb74940ecdRafael Espindola return ARMGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0); 6846e032942cf58d1c41f88609a1cec74eb74940ecdRafael Espindola} 6856e032942cf58d1c41f88609a1cec74eb74940ecdRafael Espindola 686c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg, 6879631864688c593711f82bb8d21f8b724c628d786Jim Grosbach const MachineFunction &MF) const { 688c140c4803dc3e10e08138670829bc0494986abe9David Goodwin switch (Reg) { 689c140c4803dc3e10e08138670829bc0494986abe9David Goodwin default: break; 690c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Return 0 if either register of the pair is a special register. 691c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // So no R12, etc. 692c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R1: 693c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::R0; 694c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R3: 6956009751244909c277e6cee8e74a4ccf1846953bcJim Grosbach return ARM::R2; 696c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R5: 697c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::R4; 698c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R7: 69965482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6)) 70065482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach ? 0 : ARM::R6; 701c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R9: 702c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8; 703c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R11: 704c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10; 705c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 706c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S1: 707c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S0; 708c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S3: 709c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S2; 710c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S5: 711c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S4; 712c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S7: 713c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S6; 714c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S9: 715c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S8; 716c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S11: 717c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S10; 718c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S13: 719c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S12; 720c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S15: 721c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S14; 722c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S17: 723c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S16; 724c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S19: 725c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S18; 726c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S21: 727c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S20; 728c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S23: 729c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S22; 730c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S25: 731c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S24; 732c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S27: 733c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S26; 734c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S29: 735c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S28; 736c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S31: 737c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S30; 738c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 739c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D1: 740c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D0; 741c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D3: 742c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D2; 743c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D5: 744c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D4; 745c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D7: 746c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D6; 747c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D9: 748c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D8; 749c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D11: 750c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D10; 751c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D13: 752c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D12; 753c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D15: 754c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D14; 7558295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D17: 7568295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D16; 7578295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D19: 7588295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D18; 7598295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D21: 7608295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D20; 7618295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D23: 7628295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D22; 7638295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D25: 7648295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D24; 7658295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D27: 7668295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D26; 7678295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D29: 7688295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D28; 7698295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D31: 7708295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D30; 771c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 772c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 773c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 774c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 775c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 776c140c4803dc3e10e08138670829bc0494986abe9David Goodwinunsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg, 777c140c4803dc3e10e08138670829bc0494986abe9David Goodwin const MachineFunction &MF) const { 778c140c4803dc3e10e08138670829bc0494986abe9David Goodwin switch (Reg) { 779c140c4803dc3e10e08138670829bc0494986abe9David Goodwin default: break; 780c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // Return 0 if either register of the pair is a special register. 781c140c4803dc3e10e08138670829bc0494986abe9David Goodwin // So no R12, etc. 782c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R0: 783c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::R1; 784c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R2: 7856009751244909c277e6cee8e74a4ccf1846953bcJim Grosbach return ARM::R3; 786c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R4: 787c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::R5; 788c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R6: 78965482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6)) 79065482b1bb873dd820f54a24a2f34bd65f2669e5cJim Grosbach ? 0 : ARM::R7; 791c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R8: 792c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9; 793c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::R10: 794c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11; 795c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 796c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S0: 797c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S1; 798c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S2: 799c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S3; 800c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S4: 801c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S5; 802c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S6: 803c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S7; 804c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S8: 805c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S9; 806c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S10: 807c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S11; 808c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S12: 809c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S13; 810c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S14: 811c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S15; 812c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S16: 813c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S17; 814c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S18: 815c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S19; 816c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S20: 817c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S21; 818c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S22: 819c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S23; 820c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S24: 821c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S25; 822c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S26: 823c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S27; 824c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S28: 825c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S29; 826c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::S30: 827c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::S31; 828c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 829c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D0: 830c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D1; 831c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D2: 832c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D3; 833c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D4: 834c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D5; 835c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D6: 836c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D7; 837c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D8: 838c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D9; 839c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D10: 840c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D11; 841c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D12: 842c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D13; 843c140c4803dc3e10e08138670829bc0494986abe9David Goodwin case ARM::D14: 844c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return ARM::D15; 8458295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D16: 8468295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D17; 8478295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D18: 8488295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D19; 8498295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D20: 8508295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D21; 8518295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D22: 8528295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D23; 8538295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D24: 8548295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D25; 8558295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D26: 8568295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D27; 8578295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D28: 8588295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D29; 8598295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng case ARM::D30: 8608295d99bff6f8e3dfdfdaf1871cb72adab423f20Evan Cheng return ARM::D31; 861c140c4803dc3e10e08138670829bc0494986abe9David Goodwin } 862c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 863c140c4803dc3e10e08138670829bc0494986abe9David Goodwin return 0; 864c140c4803dc3e10e08138670829bc0494986abe9David Goodwin} 865c140c4803dc3e10e08138670829bc0494986abe9David Goodwin 866db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// emitLoadConstPool - Emits a load from constpool to materialize the 867db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin/// specified immediate. 868db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinvoid ARMBaseRegisterInfo:: 869db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinemitLoadConstPool(MachineBasicBlock &MBB, 870db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock::iterator &MBBI, 87177521f5232e679aa3de10aaaed2464aa91d7ff55David Goodwin DebugLoc dl, 872378445303b10b092a898a75131141a8259cff50bEvan Cheng unsigned DestReg, unsigned SubIdx, int Val, 873db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMCC::CondCodes Pred, 8743daccd82d3151fa3629de430b55698a81084fc9eAnton Korobeynikov unsigned PredReg, unsigned MIFlags) const { 875db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineFunction &MF = *MBB.getParent(); 876db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineConstantPool *ConstantPool = MF.getConstantPool(); 87746510a73e977273ec67747eb34cbdb43f815e451Dan Gohman const Constant *C = 8781d0be15f89cb5056e20e2d24faa8d6afb1573bcaOwen Anderson ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); 879db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 880db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 881378445303b10b092a898a75131141a8259cff50bEvan Cheng BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 882378445303b10b092a898a75131141a8259cff50bEvan Cheng .addReg(DestReg, getDefRegState(true), SubIdx) 883db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin .addConstantPoolIndex(Idx) 8843daccd82d3151fa3629de430b55698a81084fc9eAnton Korobeynikov .addImm(0).addImm(Pred).addReg(PredReg) 8853daccd82d3151fa3629de430b55698a81084fc9eAnton Korobeynikov .setMIFlags(MIFlags); 886db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 887db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 888db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinbool ARMBaseRegisterInfo:: 889db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwinrequiresRegisterScavenging(const MachineFunction &MF) const { 890db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin return true; 891db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 89241fff8c19ab6d8e28f5362481c184ad628f8c704Jim Grosbach 8937e831db1d4f5dc51ca6526739cf41e59895c5c20Jim Grosbachbool ARMBaseRegisterInfo:: 8947e831db1d4f5dc51ca6526739cf41e59895c5c20Jim GrosbachrequiresFrameIndexScavenging(const MachineFunction &MF) const { 895ca5dfb71ba4aa4a8392a021ec056cf0b70f74f1eJim Grosbach return true; 8967e831db1d4f5dc51ca6526739cf41e59895c5c20Jim Grosbach} 897db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 898a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbachbool ARMBaseRegisterInfo:: 899a273442891ae20fd8192526132e3819ea9e5eda9Jim GrosbachrequiresVirtualBaseRegisters(const MachineFunction &MF) const { 900a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach return EnableLocalStackAlloc; 901a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach} 902a273442891ae20fd8192526132e3819ea9e5eda9Jim Grosbach 903db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinstatic void 9046495f63945e8dbde81f03a1dc2ab421993b9a495Evan ChengemitSPUpdate(bool isARM, 9056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 9066495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng DebugLoc dl, const ARMBaseInstrInfo &TII, 907db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin int NumBytes, 908db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { 9096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (isARM) 9106495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 9116495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Pred, PredReg, TII); 9126495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng else 9136495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 9146495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng Pred, PredReg, TII); 915db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 916db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 9176495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 918db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwinvoid ARMBaseRegisterInfo:: 919db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid GoodwineliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 920db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineBasicBlock::iterator I) const { 92116c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 922d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov if (!TFI->hasReservedCallFrame(MF)) { 923db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // If we have alloca, convert as follows: 924db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // ADJCALLSTACKDOWN -> sub, sp, sp, amount 925db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // ADJCALLSTACKUP -> add, sp, sp, amount 926db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MachineInstr *Old = I; 927db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin DebugLoc dl = Old->getDebugLoc(); 928db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Amount = Old->getOperand(0).getImm(); 929db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Amount != 0) { 930db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // We need to keep the stack aligned properly. To do this, we round the 931db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // amount of space needed for the outgoing arguments up to the next 932db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // alignment boundary. 93316c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov unsigned Align = TFI->getStackAlignment(); 934db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin Amount = (Amount+Align-1)/Align*Align; 935db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 9366495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 9376495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(!AFI->isThumb1OnlyFunction() && 938cf453ee70a1ae03cc641686fd5db0f8a7d8ce250Jim Grosbach "This eliminateCallFramePseudoInstr does not support Thumb1!"); 9396495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng bool isARM = !AFI->isThumbFunction(); 9406495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 941db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Replace the pseudo instruction with a new instruction... 942db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned Opc = Old->getOpcode(); 9434c7628e43d8468f215ea345545479b6d728cee92Jim Grosbach int PIdx = Old->findFirstPredOperandIdx(); 9444c7628e43d8468f215ea345545479b6d728cee92Jim Grosbach ARMCC::CondCodes Pred = (PIdx == -1) 9454c7628e43d8468f215ea345545479b6d728cee92Jim Grosbach ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm(); 946db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 947db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. 948db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned PredReg = Old->getOperand(2).getReg(); 9496495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg); 950db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } else { 951db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // Note: PredReg is operand 3 for ADJCALLSTACKUP. 952db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned PredReg = Old->getOperand(3).getReg(); 953db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 9546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg); 955db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 956db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 957db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin } 958db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin MBB.erase(I); 959db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 960db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 961e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbachint64_t ARMBaseRegisterInfo:: 9621ab3f16f06698596716593a30545799688acccd7Jim GrosbachgetFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { 963e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = MI->getDesc(); 964e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 965e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach int64_t InstrOffs = 0;; 966e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach int Scale = 1; 967e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach unsigned ImmIdx = 0; 9681ab3f16f06698596716593a30545799688acccd7Jim Grosbach switch (AddrMode) { 969e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrModeT2_i8: 970e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrModeT2_i12: 9713e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARMII::AddrMode_i12: 972e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = MI->getOperand(Idx+1).getImm(); 973e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach Scale = 1; 974e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 975e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrMode5: { 976e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach // VFP address mode. 977e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach const MachineOperand &OffOp = MI->getOperand(Idx+1); 978f78ee6316bc755779920ac207edc27a89c0bd2f9Jim Grosbach InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); 979e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) 980e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = -InstrOffs; 981e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach Scale = 4; 982e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 983e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 984e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrMode2: { 985e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach ImmIdx = Idx+2; 986e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); 987e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 988e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = -InstrOffs; 989e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 990e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 991e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrMode3: { 992e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach ImmIdx = Idx+2; 993e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); 994e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 995e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = -InstrOffs; 996e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 997e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 998e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach case ARMII::AddrModeT1_s: { 999e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach ImmIdx = Idx+1; 1000e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach InstrOffs = MI->getOperand(ImmIdx).getImm(); 1001e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach Scale = 4; 1002e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 1003e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 1004e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach default: 1005e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach llvm_unreachable("Unsupported addressing mode!"); 1006e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach break; 1007e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach } 1008e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach 1009e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach return InstrOffs * Scale; 1010e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach} 1011e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach 10128708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// needsFrameBaseReg - Returns true if the instruction's frame index 10138708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// reference would be better served by a base register other than FP 10148708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// or SP. Used by LocalStackFrameAllocation to determine which frame index 10158708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach/// references it should create new base registers for. 10168708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbachbool ARMBaseRegisterInfo:: 10173197380143cdc18837722129ac888528b9fbfc2bJim GrosbachneedsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 10183197380143cdc18837722129ac888528b9fbfc2bJim Grosbach for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) { 10193197380143cdc18837722129ac888528b9fbfc2bJim Grosbach assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 10203197380143cdc18837722129ac888528b9fbfc2bJim Grosbach } 10218708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 10228708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // It's the load/store FI references that cause issues, as it can be difficult 10238708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // to materialize the offset if it won't fit in the literal field. Estimate 10248708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // based on the size of the local frame and some conservative assumptions 10258708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // about the rest of the stack frame (note, this is pre-regalloc, so 10268708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // we don't know everything for certain yet) whether this offset is likely 10278708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach // to be out of range of the immediate. Return true if so. 10288708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 1029cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach // We only generate virtual base registers for loads and stores, so 1030cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach // return false for everything else. 10318708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach unsigned Opc = MI->getOpcode(); 10328708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach switch (Opc) { 1033c1d30212e911d1e55ff6b25bffefb503708883c3Jim Grosbach case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12: 10347e3383c007f53b3a00675af225e428cb66ddf404Jim Grosbach case ARM::STRi12: case ARM::STRH: case ARM::STRBi12: 10358708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach case ARM::t2LDRi12: case ARM::t2LDRi8: 10368708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach case ARM::t2STRi12: case ARM::t2STRi8: 10378708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach case ARM::VLDRS: case ARM::VLDRD: 10388708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach case ARM::VSTRS: case ARM::VSTRD: 103974d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach case ARM::tSTRspi: case ARM::tLDRspi: 1040cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach if (ForceAllBaseRegAlloc) 1041cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach return true; 1042cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach break; 10438708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach default: 10448708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach return false; 10458708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach } 1046cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach 1047cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach // Without a virtual base register, if the function has variable sized 1048cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach // objects, all fixed-size local references will be via the frame pointer, 10493197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Approximate the offset and see if it's legal for the instruction. 10503197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Note that the incoming offset is based on the SP value at function entry, 10513197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // so it'll be negative. 10523197380143cdc18837722129ac888528b9fbfc2bJim Grosbach MachineFunction &MF = *MI->getParent()->getParent(); 105316c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 10543197380143cdc18837722129ac888528b9fbfc2bJim Grosbach MachineFrameInfo *MFI = MF.getFrameInfo(); 10553197380143cdc18837722129ac888528b9fbfc2bJim Grosbach ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 10563197380143cdc18837722129ac888528b9fbfc2bJim Grosbach 10573197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Estimate an offset from the frame pointer. 10583197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Conservatively assume all callee-saved registers get pushed. R4-R6 10593197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // will be earlier than the FP, so we ignore those. 10603197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // R7, LR 10613197380143cdc18837722129ac888528b9fbfc2bJim Grosbach int64_t FPOffset = Offset - 8; 10623197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15 10633197380143cdc18837722129ac888528b9fbfc2bJim Grosbach if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction()) 10643197380143cdc18837722129ac888528b9fbfc2bJim Grosbach FPOffset -= 80; 10653197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Estimate an offset from the stack pointer. 1066c1dc78de762e8a65fe1edd0cced13d94ab5a971fJim Grosbach // The incoming offset is relating to the SP at the start of the function, 1067c1dc78de762e8a65fe1edd0cced13d94ab5a971fJim Grosbach // but when we access the local it'll be relative to the SP after local 1068c1dc78de762e8a65fe1edd0cced13d94ab5a971fJim Grosbach // allocation, so adjust our SP-relative offset by that allocation size. 10693197380143cdc18837722129ac888528b9fbfc2bJim Grosbach Offset = -Offset; 1070c1dc78de762e8a65fe1edd0cced13d94ab5a971fJim Grosbach Offset += MFI->getLocalFrameSize(); 10713197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // Assume that we'll have at least some spill slots allocated. 10723197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // FIXME: This is a total SWAG number. We should run some statistics 10733197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // and pick a real one. 10743197380143cdc18837722129ac888528b9fbfc2bJim Grosbach Offset += 128; // 128 bytes of spill slots 10753197380143cdc18837722129ac888528b9fbfc2bJim Grosbach 10763197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // If there is a frame pointer, try using it. 10773197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // The FP is only available if there is no dynamic realignment. We 10783197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // don't know for sure yet whether we'll need that, so we guess based 10793197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // on whether there are any local variables that would trigger it. 108016c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov unsigned StackAlign = TFI->getStackAlignment(); 1081d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov if (TFI->hasFP(MF) && 10823197380143cdc18837722129ac888528b9fbfc2bJim Grosbach !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) { 10833197380143cdc18837722129ac888528b9fbfc2bJim Grosbach if (isFrameOffsetLegal(MI, FPOffset)) 10843197380143cdc18837722129ac888528b9fbfc2bJim Grosbach return false; 10853197380143cdc18837722129ac888528b9fbfc2bJim Grosbach } 10863197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // If we can reference via the stack pointer, try that. 10873197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // FIXME: This (and the code that resolves the references) can be improved 10883197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // to only disallow SP relative references in the live range of 10893197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // the VLA(s). In practice, it's unclear how much difference that 10903197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // would make, but it may be worth doing. 10913197380143cdc18837722129ac888528b9fbfc2bJim Grosbach if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset)) 10923197380143cdc18837722129ac888528b9fbfc2bJim Grosbach return false; 1093cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach 10943197380143cdc18837722129ac888528b9fbfc2bJim Grosbach // The offset likely isn't legal, we want to allocate a virtual base register. 1095cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8cJim Grosbach return true; 10968708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach} 10978708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 1098976ef86689ed065361a748f81c44ca3510af2202Bill Wendling/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to 1099976ef86689ed065361a748f81c44ca3510af2202Bill Wendling/// be a pointer to FrameIdx at the beginning of the basic block. 1100dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbachvoid ARMBaseRegisterInfo:: 1101976ef86689ed065361a748f81c44ca3510af2202Bill WendlingmaterializeFrameBaseRegister(MachineBasicBlock *MBB, 1102976ef86689ed065361a748f81c44ca3510af2202Bill Wendling unsigned BaseReg, int FrameIdx, 1103976ef86689ed065361a748f81c44ca3510af2202Bill Wendling int64_t Offset) const { 1104976ef86689ed065361a748f81c44ca3510af2202Bill Wendling ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>(); 110574d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : 110674d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri); 1107dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 1108976ef86689ed065361a748f81c44ca3510af2202Bill Wendling MachineBasicBlock::iterator Ins = MBB->begin(); 1109976ef86689ed065361a748f81c44ca3510af2202Bill Wendling DebugLoc DL; // Defaults to "unknown" 1110976ef86689ed065361a748f81c44ca3510af2202Bill Wendling if (Ins != MBB->end()) 1111976ef86689ed065361a748f81c44ca3510af2202Bill Wendling DL = Ins->getDebugLoc(); 1112976ef86689ed065361a748f81c44ca3510af2202Bill Wendling 1113e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &MCID = TII.get(ADDriOpc); 111421803721d538255e4d223c29b6c8d3c9e93d4d86Cameron Zwarich MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 1115e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this)); 111621803721d538255e4d223c29b6c8d3c9e93d4d86Cameron Zwarich 1117e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg) 1118e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach .addFrameIndex(FrameIdx).addImm(Offset); 1119976ef86689ed065361a748f81c44ca3510af2202Bill Wendling 112074d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach if (!AFI->isThumb1OnlyFunction()) 112174d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach AddDefaultCC(AddDefaultPred(MIB)); 1122dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach} 1123dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 1124dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbachvoid 1125dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim GrosbachARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I, 1126dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach unsigned BaseReg, int64_t Offset) const { 1127dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach MachineInstr &MI = *I; 1128dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach MachineBasicBlock &MBB = *MI.getParent(); 1129dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach MachineFunction &MF = *MBB.getParent(); 1130dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1131dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach int Off = Offset; // ARM doesn't need the general 64-bit offsets 1132dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach unsigned i = 0; 1133dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 1134dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach assert(!AFI->isThumb1OnlyFunction() && 1135dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach "This resolveFrameIndex does not support Thumb1!"); 1136dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach 1137dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach while (!MI.getOperand(i).isFI()) { 1138dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach ++i; 1139dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 1140dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach } 1141dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach bool Done = false; 1142dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach if (!AFI->isThumbFunction()) 1143dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); 1144dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach else { 1145dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach assert(AFI->isThumb2Function()); 1146dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII); 1147dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach } 1148dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach assert (Done && "Unable to resolve frame index!"); 1149dc140c6e7b8350ca51aa1d408c10e25a27826e2cJim Grosbach} 11508708ead5a46f4ec8f2d5f832be23381924d72b8dJim Grosbach 1151e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbachbool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 1152e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach int64_t Offset) const { 1153e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = MI->getDesc(); 11542b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 11552b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned i = 0; 11562b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 11572b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach while (!MI->getOperand(i).isFI()) { 11582b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach ++i; 11592b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 11602b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach } 11612b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 11622b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach // AddrMode4 and AddrMode6 cannot handle any offset. 11632b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) 11642b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach return Offset == 0; 11652b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 11662b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned NumBits = 0; 11672b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned Scale = 1; 1168e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach bool isSigned = true; 11691ab3f16f06698596716593a30545799688acccd7Jim Grosbach switch (AddrMode) { 11702b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach case ARMII::AddrModeT2_i8: 11712b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach case ARMII::AddrModeT2_i12: 11722b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach // i8 supports only negative, and i12 supports only positive, so 11732b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach // based on Offset sign, consider the appropriate instruction 117474d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach Scale = 1; 11752b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach if (Offset < 0) { 11762b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 8; 11772b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach Offset = -Offset; 11782b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach } else { 11792b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 12; 11802b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach } 11812b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach break; 11821ab3f16f06698596716593a30545799688acccd7Jim Grosbach case ARMII::AddrMode5: 11832b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach // VFP address mode. 11842b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 8; 11852b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach Scale = 4; 11862b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach break; 11873e5561247202bae994dd259a2d8dc4eff8f799f3Jim Grosbach case ARMII::AddrMode_i12: 11881ab3f16f06698596716593a30545799688acccd7Jim Grosbach case ARMII::AddrMode2: 11892b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 12; 11902b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach break; 11911ab3f16f06698596716593a30545799688acccd7Jim Grosbach case ARMII::AddrMode3: 11922b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach NumBits = 8; 11932b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach break; 11941ab3f16f06698596716593a30545799688acccd7Jim Grosbach case ARMII::AddrModeT1_s: 119574d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach NumBits = 5; 119674d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach Scale = 4; 1197e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach isSigned = false; 119874d7b0af58951dce2f874c600a6a48a2454b4914Jim Grosbach break; 11992b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach default: 12002b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach llvm_unreachable("Unsupported addressing mode!"); 12012b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach break; 12022b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach } 12032b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 12041ab3f16f06698596716593a30545799688acccd7Jim Grosbach Offset += getFrameIndexInstrOffset(MI, i); 1205d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach // Make sure the offset is encodable for instructions that scale the 1206d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach // immediate. 1207d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach if ((Offset & (Scale-1)) != 0) 1208d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach return false; 1209d4511e947ee1e89a4f199bfac0d401976930ccfeJim Grosbach 1210e2f556933e1a19cddf6d4f370e2770c0f763b025Jim Grosbach if (isSigned && Offset < 0) 12112b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach Offset = -Offset; 12122b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach 12132b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach unsigned Mask = (1 << NumBits) - 1; 12142b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach if ((unsigned)Offset <= Mask * Scale) 12152b1e202e1c2137b03f7c6ecc18668e40819fa22fJim Grosbach return true; 121674d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach 121774d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach return false; 121874d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach} 121974d803a58c7935c067397bb19afc05ec464d8159Jim Grosbach 1220fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbachvoid 12216495f63945e8dbde81f03a1dc2ab421993b9a495Evan ChengARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 1222fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach int SPAdj, RegScavenger *RS) const { 12235ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin unsigned i = 0; 12245ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MachineInstr &MI = *II; 12255ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MachineBasicBlock &MBB = *MI.getParent(); 12265ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin MachineFunction &MF = *MBB.getParent(); 122716c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov const ARMFrameLowering *TFI = 122816c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering()); 12295ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 12306495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(!AFI->isThumb1OnlyFunction() && 1231a15de00f8246f19180b26ee5fe7ff8f436e0de08Bob Wilson "This eliminateFrameIndex does not support Thumb1!"); 12325ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 12335ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin while (!MI.getOperand(i).isFI()) { 12345ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin ++i; 12355ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 12365ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin } 12375ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 12385ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin int FrameIndex = MI.getOperand(i).getIndex(); 1239a37aa546224ec03ba1f1a1598e0781af4b692673Jim Grosbach unsigned FrameReg; 12405ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 124182f58740c76b42af8370247b23677a0318f6dde8Anton Korobeynikov int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); 12425ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 124362b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng // Special handling of dbg_value instructions. 124462b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng if (MI.isDebugValue()) { 124562b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/); 124662b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng MI.getOperand(i+1).ChangeToImmediate(Offset); 1247fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach return; 124862b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng } 124962b50656ceb854eb0be265d63b2a1d46e7400d8aEvan Cheng 125048d8afab73d72418cf9505a020f621014920463cEvan Cheng // Modify MI as necessary to handle as much of 'Offset' as possible 1251cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng bool Done = false; 12526495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng if (!AFI->isThumbFunction()) 1253cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII); 12546495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng else { 12556495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng assert(AFI->isThumb2Function()); 1256cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII); 12576495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1258cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng if (Done) 1259fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341aJim Grosbach return; 12605ff58b5c3ab6df332600678798ea5c69c5e943d3David Goodwin 1261db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // If we get here, the immediate doesn't fit into the instruction. We folded 1262db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // as much as possible above, handle the rest, providing a register that is 1263db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin // SP+LargeImm. 126419bb87d0f80f3e6eed38a9fa267bf2b0474aeaabDaniel Dunbar assert((Offset || 1265a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || 1266a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && 1267cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng "This code isn't needed if offset already handled!"); 1268db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin 12697e831db1d4f5dc51ca6526739cf41e59895c5c20Jim Grosbach unsigned ScratchReg = 0; 1270db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin int PIdx = MI.findFirstPredOperandIdx(); 1271db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ARMCC::CondCodes Pred = (PIdx == -1) 1272db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 1273db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 1274cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng if (Offset == 0) 1275a44321776ecd96fa0344335d3027758be3386e45Jim Grosbach // Must be addrmode4/6. 1276cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false); 12776495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng else { 1278ca5dfb71ba4aa4a8392a021ec056cf0b70f74f1eJim Grosbach ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass); 1279cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng if (!AFI->isThumbFunction()) 1280cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1281cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset, Pred, PredReg, TII); 1282cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng else { 1283cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng assert(AFI->isThumb2Function()); 1284cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1285cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng Offset, Pred, PredReg, TII); 1286cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng } 1287cde31293d45f14ddff482d385429d256bd4e0820Jim Grosbach // Update the original instruction to use the scratch register. 1288cdbb3f5d3311e0f46d22bc8daa211b2fab3541cbEvan Cheng MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); 1289cde31293d45f14ddff482d385429d256bd4e0820Jim Grosbach if (MI.getOpcode() == ARM::t2ADDrSPi) 1290cde31293d45f14ddff482d385429d256bd4e0820Jim Grosbach MI.setDesc(TII.get(ARM::t2ADDri)); 1291cde31293d45f14ddff482d385429d256bd4e0820Jim Grosbach else if (MI.getOpcode() == ARM::t2SUBrSPi) 1292cde31293d45f14ddff482d385429d256bd4e0820Jim Grosbach MI.setDesc(TII.get(ARM::t2SUBri)); 12936495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng } 1294db5a71a8e01ed9a0d93a19176df6ea0aea510d7bDavid Goodwin} 1295