ARMBaseRegisterInfo.cpp revision ebe69fe11e48d322045d5949c83283927a0d790b
1//===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the base ARM implementation of TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARMBaseRegisterInfo.h" 15#include "ARM.h" 16#include "ARMBaseInstrInfo.h" 17#include "ARMFrameLowering.h" 18#include "ARMMachineFunctionInfo.h" 19#include "ARMSubtarget.h" 20#include "MCTargetDesc/ARMAddressingModes.h" 21#include "llvm/ADT/BitVector.h" 22#include "llvm/ADT/SmallVector.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineFunction.h" 26#include "llvm/CodeGen/MachineInstrBuilder.h" 27#include "llvm/CodeGen/MachineRegisterInfo.h" 28#include "llvm/CodeGen/RegisterScavenging.h" 29#include "llvm/CodeGen/VirtRegMap.h" 30#include "llvm/IR/Constants.h" 31#include "llvm/IR/DerivedTypes.h" 32#include "llvm/IR/Function.h" 33#include "llvm/IR/LLVMContext.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/raw_ostream.h" 37#include "llvm/Target/TargetFrameLowering.h" 38#include "llvm/Target/TargetMachine.h" 39#include "llvm/Target/TargetOptions.h" 40 41#define DEBUG_TYPE "arm-register-info" 42 43#define GET_REGINFO_TARGET_DESC 44#include "ARMGenRegisterInfo.inc" 45 46using namespace llvm; 47 48ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMSubtarget &sti) 49 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), STI(sti), BasePtr(ARM::R6) { 50 if (STI.isTargetMachO()) { 51 if (STI.isTargetDarwin() || STI.isThumb1Only()) 52 FramePtr = ARM::R7; 53 else 54 FramePtr = ARM::R11; 55 } else if (STI.isTargetWindows()) 56 FramePtr = ARM::R11; 57 else // ARM EABI 58 FramePtr = STI.isThumb() ? ARM::R7 : ARM::R11; 59} 60 61const MCPhysReg* 62ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 63 const MCPhysReg *RegList = 64 STI.isTargetDarwin() ? CSR_iOS_SaveList : CSR_AAPCS_SaveList; 65 66 if (!MF) return RegList; 67 68 const Function *F = MF->getFunction(); 69 if (F->getCallingConv() == CallingConv::GHC) { 70 // GHC set of callee saved regs is empty as all those regs are 71 // used for passing STG regs around 72 return CSR_NoRegs_SaveList; 73 } else if (F->hasFnAttribute("interrupt")) { 74 if (STI.isMClass()) { 75 // M-class CPUs have hardware which saves the registers needed to allow a 76 // function conforming to the AAPCS to function as a handler. 77 return CSR_AAPCS_SaveList; 78 } else if (F->getFnAttribute("interrupt").getValueAsString() == "FIQ") { 79 // Fast interrupt mode gives the handler a private copy of R8-R14, so less 80 // need to be saved to restore user-mode state. 81 return CSR_FIQ_SaveList; 82 } else { 83 // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by 84 // exception handling. 85 return CSR_GenericInt_SaveList; 86 } 87 } 88 89 return RegList; 90} 91 92const uint32_t* 93ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { 94 if (CC == CallingConv::GHC) 95 // This is academic becase all GHC calls are (supposed to be) tail calls 96 return CSR_NoRegs_RegMask; 97 return STI.isTargetDarwin() ? CSR_iOS_RegMask : CSR_AAPCS_RegMask; 98} 99 100const uint32_t* 101ARMBaseRegisterInfo::getNoPreservedMask() const { 102 return CSR_NoRegs_RegMask; 103} 104 105const uint32_t* 106ARMBaseRegisterInfo::getThisReturnPreservedMask(CallingConv::ID CC) const { 107 // This should return a register mask that is the same as that returned by 108 // getCallPreservedMask but that additionally preserves the register used for 109 // the first i32 argument (which must also be the register used to return a 110 // single i32 return value) 111 // 112 // In case that the calling convention does not use the same register for 113 // both or otherwise does not want to enable this optimization, the function 114 // should return NULL 115 if (CC == CallingConv::GHC) 116 // This is academic becase all GHC calls are (supposed to be) tail calls 117 return nullptr; 118 return STI.isTargetDarwin() ? CSR_iOS_ThisReturn_RegMask 119 : CSR_AAPCS_ThisReturn_RegMask; 120} 121 122BitVector ARMBaseRegisterInfo:: 123getReservedRegs(const MachineFunction &MF) const { 124 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); 125 126 // FIXME: avoid re-calculating this every time. 127 BitVector Reserved(getNumRegs()); 128 Reserved.set(ARM::SP); 129 Reserved.set(ARM::PC); 130 Reserved.set(ARM::FPSCR); 131 Reserved.set(ARM::APSR_NZCV); 132 if (TFI->hasFP(MF)) 133 Reserved.set(FramePtr); 134 if (hasBasePointer(MF)) 135 Reserved.set(BasePtr); 136 // Some targets reserve R9. 137 if (STI.isR9Reserved()) 138 Reserved.set(ARM::R9); 139 // Reserve D16-D31 if the subtarget doesn't support them. 140 if (!STI.hasVFP3() || STI.hasD16()) { 141 assert(ARM::D31 == ARM::D16 + 15); 142 for (unsigned i = 0; i != 16; ++i) 143 Reserved.set(ARM::D16 + i); 144 } 145 const TargetRegisterClass *RC = &ARM::GPRPairRegClass; 146 for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I) 147 for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI) 148 if (Reserved.test(*SI)) Reserved.set(*I); 149 150 return Reserved; 151} 152 153const TargetRegisterClass* 154ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) 155 const { 156 const TargetRegisterClass *Super = RC; 157 TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); 158 do { 159 switch (Super->getID()) { 160 case ARM::GPRRegClassID: 161 case ARM::SPRRegClassID: 162 case ARM::DPRRegClassID: 163 case ARM::QPRRegClassID: 164 case ARM::QQPRRegClassID: 165 case ARM::QQQQPRRegClassID: 166 case ARM::GPRPairRegClassID: 167 return Super; 168 } 169 Super = *I++; 170 } while (Super); 171 return RC; 172} 173 174const TargetRegisterClass * 175ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 176 const { 177 return &ARM::GPRRegClass; 178} 179 180const TargetRegisterClass * 181ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { 182 if (RC == &ARM::CCRRegClass) 183 return &ARM::rGPRRegClass; // Can't copy CCR registers. 184 return RC; 185} 186 187unsigned 188ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 189 MachineFunction &MF) const { 190 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); 191 192 switch (RC->getID()) { 193 default: 194 return 0; 195 case ARM::tGPRRegClassID: 196 return TFI->hasFP(MF) ? 4 : 5; 197 case ARM::GPRRegClassID: { 198 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 199 return 10 - FP - (STI.isR9Reserved() ? 1 : 0); 200 } 201 case ARM::SPRRegClassID: // Currently not used as 'rep' register class. 202 case ARM::DPRRegClassID: 203 return 32 - 10; 204 } 205} 206 207// Get the other register in a GPRPair. 208static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) { 209 for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers) 210 if (ARM::GPRPairRegClass.contains(*Supers)) 211 return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0); 212 return 0; 213} 214 215// Resolve the RegPairEven / RegPairOdd register allocator hints. 216void 217ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg, 218 ArrayRef<MCPhysReg> Order, 219 SmallVectorImpl<MCPhysReg> &Hints, 220 const MachineFunction &MF, 221 const VirtRegMap *VRM) const { 222 const MachineRegisterInfo &MRI = MF.getRegInfo(); 223 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 224 225 unsigned Odd; 226 switch (Hint.first) { 227 case ARMRI::RegPairEven: 228 Odd = 0; 229 break; 230 case ARMRI::RegPairOdd: 231 Odd = 1; 232 break; 233 default: 234 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM); 235 return; 236 } 237 238 // This register should preferably be even (Odd == 0) or odd (Odd == 1). 239 // Check if the other part of the pair has already been assigned, and provide 240 // the paired register as the first hint. 241 unsigned PairedPhys = 0; 242 if (VRM && VRM->hasPhys(Hint.second)) { 243 PairedPhys = getPairedGPR(VRM->getPhys(Hint.second), Odd, this); 244 if (PairedPhys && MRI.isReserved(PairedPhys)) 245 PairedPhys = 0; 246 } 247 248 // First prefer the paired physreg. 249 if (PairedPhys && 250 std::find(Order.begin(), Order.end(), PairedPhys) != Order.end()) 251 Hints.push_back(PairedPhys); 252 253 // Then prefer even or odd registers. 254 for (unsigned I = 0, E = Order.size(); I != E; ++I) { 255 unsigned Reg = Order[I]; 256 if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd) 257 continue; 258 // Don't provide hints that are paired to a reserved register. 259 unsigned Paired = getPairedGPR(Reg, !Odd, this); 260 if (!Paired || MRI.isReserved(Paired)) 261 continue; 262 Hints.push_back(Reg); 263 } 264} 265 266void 267ARMBaseRegisterInfo::updateRegAllocHint(unsigned Reg, unsigned NewReg, 268 MachineFunction &MF) const { 269 MachineRegisterInfo *MRI = &MF.getRegInfo(); 270 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 271 if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 272 Hint.first == (unsigned)ARMRI::RegPairEven) && 273 TargetRegisterInfo::isVirtualRegister(Hint.second)) { 274 // If 'Reg' is one of the even / odd register pair and it's now changed 275 // (e.g. coalesced) into a different register. The other register of the 276 // pair allocation hint must be updated to reflect the relationship 277 // change. 278 unsigned OtherReg = Hint.second; 279 Hint = MRI->getRegAllocationHint(OtherReg); 280 if (Hint.second == Reg) 281 // Make sure the pair has not already divorced. 282 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 283 } 284} 285 286bool 287ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 288 // CortexA9 has a Write-after-write hazard for NEON registers. 289 if (!STI.isLikeA9()) 290 return false; 291 292 switch (RC->getID()) { 293 case ARM::DPRRegClassID: 294 case ARM::DPR_8RegClassID: 295 case ARM::DPR_VFP2RegClassID: 296 case ARM::QPRRegClassID: 297 case ARM::QPR_8RegClassID: 298 case ARM::QPR_VFP2RegClassID: 299 case ARM::SPRRegClassID: 300 case ARM::SPR_8RegClassID: 301 // Avoid reusing S, D, and Q registers. 302 // Don't increase register pressure for QQ and QQQQ. 303 return true; 304 default: 305 return false; 306 } 307} 308 309bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 310 const MachineFrameInfo *MFI = MF.getFrameInfo(); 311 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 312 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); 313 314 // When outgoing call frames are so large that we adjust the stack pointer 315 // around the call, we can no longer use the stack pointer to reach the 316 // emergency spill slot. 317 if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF)) 318 return true; 319 320 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited 321 // negative range for ldr/str (255), and thumb1 is positive offsets only. 322 // It's going to be better to use the SP or Base Pointer instead. When there 323 // are variable sized objects, we can't reference off of the SP, so we 324 // reserve a Base Pointer. 325 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) { 326 // Conservatively estimate whether the negative offset from the frame 327 // pointer will be sufficient to reach. If a function has a smallish 328 // frame, it's less likely to have lots of spills and callee saved 329 // space, so it's all more likely to be within range of the frame pointer. 330 // If it's wrong, the scavenger will still enable access to work, it just 331 // won't be optimal. 332 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128) 333 return false; 334 return true; 335 } 336 337 return false; 338} 339 340bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { 341 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 342 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 343 // We can't realign the stack if: 344 // 1. Dynamic stack realignment is explicitly disabled, 345 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or 346 // 3. There are VLAs in the function and the base pointer is disabled. 347 if (MF.getFunction()->hasFnAttribute("no-realign-stack")) 348 return false; 349 if (AFI->isThumb1OnlyFunction()) 350 return false; 351 // Stack realignment requires a frame pointer. If we already started 352 // register allocation with frame pointer elimination, it is too late now. 353 if (!MRI->canReserveReg(FramePtr)) 354 return false; 355 // We may also need a base pointer if there are dynamic allocas or stack 356 // pointer adjustments around calls. 357 if (MF.getSubtarget().getFrameLowering()->hasReservedCallFrame(MF)) 358 return true; 359 // A base pointer is required and allowed. Check that it isn't too late to 360 // reserve it. 361 return MRI->canReserveReg(BasePtr); 362} 363 364bool ARMBaseRegisterInfo:: 365needsStackRealignment(const MachineFunction &MF) const { 366 const MachineFrameInfo *MFI = MF.getFrameInfo(); 367 const Function *F = MF.getFunction(); 368 unsigned StackAlign = 369 MF.getSubtarget().getFrameLowering()->getStackAlignment(); 370 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) || 371 F->hasFnAttribute(Attribute::StackAlignment)); 372 373 return requiresRealignment && canRealignStack(MF); 374} 375 376bool ARMBaseRegisterInfo:: 377cannotEliminateFrame(const MachineFunction &MF) const { 378 const MachineFrameInfo *MFI = MF.getFrameInfo(); 379 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack()) 380 return true; 381 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() 382 || needsStackRealignment(MF); 383} 384 385unsigned 386ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 387 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); 388 389 if (TFI->hasFP(MF)) 390 return FramePtr; 391 return ARM::SP; 392} 393 394/// emitLoadConstPool - Emits a load from constpool to materialize the 395/// specified immediate. 396void ARMBaseRegisterInfo:: 397emitLoadConstPool(MachineBasicBlock &MBB, 398 MachineBasicBlock::iterator &MBBI, 399 DebugLoc dl, 400 unsigned DestReg, unsigned SubIdx, int Val, 401 ARMCC::CondCodes Pred, 402 unsigned PredReg, unsigned MIFlags) const { 403 MachineFunction &MF = *MBB.getParent(); 404 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 405 MachineConstantPool *ConstantPool = MF.getConstantPool(); 406 const Constant *C = 407 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); 408 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 409 410 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 411 .addReg(DestReg, getDefRegState(true), SubIdx) 412 .addConstantPoolIndex(Idx) 413 .addImm(0).addImm(Pred).addReg(PredReg) 414 .setMIFlags(MIFlags); 415} 416 417bool ARMBaseRegisterInfo:: 418requiresRegisterScavenging(const MachineFunction &MF) const { 419 return true; 420} 421 422bool ARMBaseRegisterInfo:: 423trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 424 return true; 425} 426 427bool ARMBaseRegisterInfo:: 428requiresFrameIndexScavenging(const MachineFunction &MF) const { 429 return true; 430} 431 432bool ARMBaseRegisterInfo:: 433requiresVirtualBaseRegisters(const MachineFunction &MF) const { 434 return true; 435} 436 437int64_t ARMBaseRegisterInfo:: 438getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { 439 const MCInstrDesc &Desc = MI->getDesc(); 440 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 441 int64_t InstrOffs = 0; 442 int Scale = 1; 443 unsigned ImmIdx = 0; 444 switch (AddrMode) { 445 case ARMII::AddrModeT2_i8: 446 case ARMII::AddrModeT2_i12: 447 case ARMII::AddrMode_i12: 448 InstrOffs = MI->getOperand(Idx+1).getImm(); 449 Scale = 1; 450 break; 451 case ARMII::AddrMode5: { 452 // VFP address mode. 453 const MachineOperand &OffOp = MI->getOperand(Idx+1); 454 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); 455 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) 456 InstrOffs = -InstrOffs; 457 Scale = 4; 458 break; 459 } 460 case ARMII::AddrMode2: { 461 ImmIdx = Idx+2; 462 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); 463 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 464 InstrOffs = -InstrOffs; 465 break; 466 } 467 case ARMII::AddrMode3: { 468 ImmIdx = Idx+2; 469 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); 470 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 471 InstrOffs = -InstrOffs; 472 break; 473 } 474 case ARMII::AddrModeT1_s: { 475 ImmIdx = Idx+1; 476 InstrOffs = MI->getOperand(ImmIdx).getImm(); 477 Scale = 4; 478 break; 479 } 480 default: 481 llvm_unreachable("Unsupported addressing mode!"); 482 } 483 484 return InstrOffs * Scale; 485} 486 487/// needsFrameBaseReg - Returns true if the instruction's frame index 488/// reference would be better served by a base register other than FP 489/// or SP. Used by LocalStackFrameAllocation to determine which frame index 490/// references it should create new base registers for. 491bool ARMBaseRegisterInfo:: 492needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 493 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) { 494 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 495 } 496 497 // It's the load/store FI references that cause issues, as it can be difficult 498 // to materialize the offset if it won't fit in the literal field. Estimate 499 // based on the size of the local frame and some conservative assumptions 500 // about the rest of the stack frame (note, this is pre-regalloc, so 501 // we don't know everything for certain yet) whether this offset is likely 502 // to be out of range of the immediate. Return true if so. 503 504 // We only generate virtual base registers for loads and stores, so 505 // return false for everything else. 506 unsigned Opc = MI->getOpcode(); 507 switch (Opc) { 508 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12: 509 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12: 510 case ARM::t2LDRi12: case ARM::t2LDRi8: 511 case ARM::t2STRi12: case ARM::t2STRi8: 512 case ARM::VLDRS: case ARM::VLDRD: 513 case ARM::VSTRS: case ARM::VSTRD: 514 case ARM::tSTRspi: case ARM::tLDRspi: 515 break; 516 default: 517 return false; 518 } 519 520 // Without a virtual base register, if the function has variable sized 521 // objects, all fixed-size local references will be via the frame pointer, 522 // Approximate the offset and see if it's legal for the instruction. 523 // Note that the incoming offset is based on the SP value at function entry, 524 // so it'll be negative. 525 MachineFunction &MF = *MI->getParent()->getParent(); 526 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); 527 MachineFrameInfo *MFI = MF.getFrameInfo(); 528 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 529 530 // Estimate an offset from the frame pointer. 531 // Conservatively assume all callee-saved registers get pushed. R4-R6 532 // will be earlier than the FP, so we ignore those. 533 // R7, LR 534 int64_t FPOffset = Offset - 8; 535 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15 536 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction()) 537 FPOffset -= 80; 538 // Estimate an offset from the stack pointer. 539 // The incoming offset is relating to the SP at the start of the function, 540 // but when we access the local it'll be relative to the SP after local 541 // allocation, so adjust our SP-relative offset by that allocation size. 542 Offset = -Offset; 543 Offset += MFI->getLocalFrameSize(); 544 // Assume that we'll have at least some spill slots allocated. 545 // FIXME: This is a total SWAG number. We should run some statistics 546 // and pick a real one. 547 Offset += 128; // 128 bytes of spill slots 548 549 // If there's a frame pointer and the addressing mode allows it, try using it. 550 // The FP is only available if there is no dynamic realignment. We 551 // don't know for sure yet whether we'll need that, so we guess based 552 // on whether there are any local variables that would trigger it. 553 unsigned StackAlign = TFI->getStackAlignment(); 554 if (TFI->hasFP(MF) && 555 (MI->getDesc().TSFlags & ARMII::AddrModeMask) != ARMII::AddrModeT1_s && 556 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) { 557 if (isFrameOffsetLegal(MI, FPOffset)) 558 return false; 559 } 560 // If we can reference via the stack pointer, try that. 561 // FIXME: This (and the code that resolves the references) can be improved 562 // to only disallow SP relative references in the live range of 563 // the VLA(s). In practice, it's unclear how much difference that 564 // would make, but it may be worth doing. 565 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset)) 566 return false; 567 568 // The offset likely isn't legal, we want to allocate a virtual base register. 569 return true; 570} 571 572/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to 573/// be a pointer to FrameIdx at the beginning of the basic block. 574void ARMBaseRegisterInfo:: 575materializeFrameBaseRegister(MachineBasicBlock *MBB, 576 unsigned BaseReg, int FrameIdx, 577 int64_t Offset) const { 578 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>(); 579 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : 580 (AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri); 581 582 MachineBasicBlock::iterator Ins = MBB->begin(); 583 DebugLoc DL; // Defaults to "unknown" 584 if (Ins != MBB->end()) 585 DL = Ins->getDebugLoc(); 586 587 const MachineFunction &MF = *MBB->getParent(); 588 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 589 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); 590 const MCInstrDesc &MCID = TII.get(ADDriOpc); 591 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 592 593 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg) 594 .addFrameIndex(FrameIdx).addImm(Offset); 595 596 if (!AFI->isThumb1OnlyFunction()) 597 AddDefaultCC(AddDefaultPred(MIB)); 598} 599 600void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 601 int64_t Offset) const { 602 MachineBasicBlock &MBB = *MI.getParent(); 603 MachineFunction &MF = *MBB.getParent(); 604 const ARMBaseInstrInfo &TII = 605 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); 606 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 607 int Off = Offset; // ARM doesn't need the general 64-bit offsets 608 unsigned i = 0; 609 610 assert(!AFI->isThumb1OnlyFunction() && 611 "This resolveFrameIndex does not support Thumb1!"); 612 613 while (!MI.getOperand(i).isFI()) { 614 ++i; 615 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 616 } 617 bool Done = false; 618 if (!AFI->isThumbFunction()) 619 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); 620 else { 621 assert(AFI->isThumb2Function()); 622 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII); 623 } 624 assert (Done && "Unable to resolve frame index!"); 625 (void)Done; 626} 627 628bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 629 int64_t Offset) const { 630 const MCInstrDesc &Desc = MI->getDesc(); 631 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 632 unsigned i = 0; 633 634 while (!MI->getOperand(i).isFI()) { 635 ++i; 636 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 637 } 638 639 // AddrMode4 and AddrMode6 cannot handle any offset. 640 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) 641 return Offset == 0; 642 643 unsigned NumBits = 0; 644 unsigned Scale = 1; 645 bool isSigned = true; 646 switch (AddrMode) { 647 case ARMII::AddrModeT2_i8: 648 case ARMII::AddrModeT2_i12: 649 // i8 supports only negative, and i12 supports only positive, so 650 // based on Offset sign, consider the appropriate instruction 651 Scale = 1; 652 if (Offset < 0) { 653 NumBits = 8; 654 Offset = -Offset; 655 } else { 656 NumBits = 12; 657 } 658 break; 659 case ARMII::AddrMode5: 660 // VFP address mode. 661 NumBits = 8; 662 Scale = 4; 663 break; 664 case ARMII::AddrMode_i12: 665 case ARMII::AddrMode2: 666 NumBits = 12; 667 break; 668 case ARMII::AddrMode3: 669 NumBits = 8; 670 break; 671 case ARMII::AddrModeT1_s: 672 NumBits = 8; 673 Scale = 4; 674 isSigned = false; 675 break; 676 default: 677 llvm_unreachable("Unsupported addressing mode!"); 678 } 679 680 Offset += getFrameIndexInstrOffset(MI, i); 681 // Make sure the offset is encodable for instructions that scale the 682 // immediate. 683 if ((Offset & (Scale-1)) != 0) 684 return false; 685 686 if (isSigned && Offset < 0) 687 Offset = -Offset; 688 689 unsigned Mask = (1 << NumBits) - 1; 690 if ((unsigned)Offset <= Mask * Scale) 691 return true; 692 693 return false; 694} 695 696void 697ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 698 int SPAdj, unsigned FIOperandNum, 699 RegScavenger *RS) const { 700 MachineInstr &MI = *II; 701 MachineBasicBlock &MBB = *MI.getParent(); 702 MachineFunction &MF = *MBB.getParent(); 703 const ARMBaseInstrInfo &TII = 704 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo()); 705 const ARMFrameLowering *TFI = static_cast<const ARMFrameLowering *>( 706 MF.getSubtarget().getFrameLowering()); 707 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 708 assert(!AFI->isThumb1OnlyFunction() && 709 "This eliminateFrameIndex does not support Thumb1!"); 710 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 711 unsigned FrameReg; 712 713 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); 714 715 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the 716 // call frame setup/destroy instructions have already been eliminated. That 717 // means the stack pointer cannot be used to access the emergency spill slot 718 // when !hasReservedCallFrame(). 719#ifndef NDEBUG 720 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){ 721 assert(TFI->hasReservedCallFrame(MF) && 722 "Cannot use SP to access the emergency spill slot in " 723 "functions without a reserved call frame"); 724 assert(!MF.getFrameInfo()->hasVarSizedObjects() && 725 "Cannot use SP to access the emergency spill slot in " 726 "functions with variable sized frame objects"); 727 } 728#endif // NDEBUG 729 730 assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code"); 731 732 // Modify MI as necessary to handle as much of 'Offset' as possible 733 bool Done = false; 734 if (!AFI->isThumbFunction()) 735 Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 736 else { 737 assert(AFI->isThumb2Function()); 738 Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII); 739 } 740 if (Done) 741 return; 742 743 // If we get here, the immediate doesn't fit into the instruction. We folded 744 // as much as possible above, handle the rest, providing a register that is 745 // SP+LargeImm. 746 assert((Offset || 747 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || 748 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && 749 "This code isn't needed if offset already handled!"); 750 751 unsigned ScratchReg = 0; 752 int PIdx = MI.findFirstPredOperandIdx(); 753 ARMCC::CondCodes Pred = (PIdx == -1) 754 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 755 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 756 if (Offset == 0) 757 // Must be addrmode4/6. 758 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false); 759 else { 760 ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass); 761 if (!AFI->isThumbFunction()) 762 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 763 Offset, Pred, PredReg, TII); 764 else { 765 assert(AFI->isThumb2Function()); 766 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 767 Offset, Pred, PredReg, TII); 768 } 769 // Update the original instruction to use the scratch register. 770 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true); 771 } 772} 773 774bool ARMBaseRegisterInfo::shouldCoalesce(MachineInstr *MI, 775 const TargetRegisterClass *SrcRC, 776 unsigned SubReg, 777 const TargetRegisterClass *DstRC, 778 unsigned DstSubReg, 779 const TargetRegisterClass *NewRC) const { 780 auto MBB = MI->getParent(); 781 auto MF = MBB->getParent(); 782 const MachineRegisterInfo &MRI = MF->getRegInfo(); 783 // If not copying into a sub-register this should be ok because we shouldn't 784 // need to split the reg. 785 if (!DstSubReg) 786 return true; 787 // Small registers don't frequently cause a problem, so we can coalesce them. 788 if (NewRC->getSize() < 32 && DstRC->getSize() < 32 && SrcRC->getSize() < 32) 789 return true; 790 791 auto NewRCWeight = 792 MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC); 793 auto SrcRCWeight = 794 MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC); 795 auto DstRCWeight = 796 MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC); 797 // If the source register class is more expensive than the destination, the 798 // coalescing is probably profitable. 799 if (SrcRCWeight.RegWeight > NewRCWeight.RegWeight) 800 return true; 801 if (DstRCWeight.RegWeight > NewRCWeight.RegWeight) 802 return true; 803 804 // If the register allocator isn't constrained, we can always allow coalescing 805 // unfortunately we don't know yet if we will be constrained. 806 // The goal of this heuristic is to restrict how many expensive registers 807 // we allow to coalesce in a given basic block. 808 auto AFI = MF->getInfo<ARMFunctionInfo>(); 809 auto It = AFI->getCoalescedWeight(MBB); 810 811 DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: " 812 << It->second << "\n"); 813 DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: " 814 << NewRCWeight.RegWeight << "\n"); 815 816 // This number is the largest round number that which meets the criteria: 817 // (1) addresses PR18825 818 // (2) generates better code in some test cases (like vldm-shed-a9.ll) 819 // (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC) 820 // In practice the SizeMultiplier will only factor in for straight line code 821 // that uses a lot of NEON vectors, which isn't terribly common. 822 unsigned SizeMultiplier = MBB->size()/100; 823 SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1; 824 if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) { 825 It->second += NewRCWeight.RegWeight; 826 return true; 827 } 828 return false; 829} 830