ARMISelLowering.h revision 23ff7cff52702a8bff904d8ab4c9ca67cc19d6ca
1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef ARMISELLOWERING_H 16#define ARMISELLOWERING_H 17 18#include "ARMSubtarget.h" 19#include "llvm/Target/TargetLowering.h" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/CodeGen/CallingConvLower.h" 22#include <vector> 23 24namespace llvm { 25 class ARMConstantPoolValue; 26 27 namespace ARMISD { 28 // ARM Specific DAG Nodes 29 enum NodeType { 30 // Start the numbering where the builtin ops and target ops leave off. 31 FIRST_NUMBER = ISD::BUILTIN_OP_END, 32 33 Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 34 // TargetExternalSymbol, and TargetGlobalAddress. 35 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 36 37 CALL, // Function call. 38 CALL_PRED, // Function call that's predicable. 39 CALL_NOLINK, // Function call with branch not branch-and-link. 40 tCALL, // Thumb function call. 41 BRCOND, // Conditional branch. 42 BR_JT, // Jumptable branch. 43 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). 44 RET_FLAG, // Return with a flag operand. 45 46 PIC_ADD, // Add with a PC operand and a PIC label. 47 48 CMP, // ARM compare instructions. 49 CMPZ, // ARM compare that sets only Z flag. 50 CMPFP, // ARM VFP compare instruction, sets FPSCR. 51 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR. 52 FMSTAT, // ARM fmstat instruction. 53 CMOV, // ARM conditional move instructions. 54 CNEG, // ARM conditional negate instructions. 55 56 RBIT, // ARM bitreverse instruction 57 58 FTOSI, // FP to sint within a FP register. 59 FTOUI, // FP to uint within a FP register. 60 SITOF, // sint to FP within a FP register. 61 UITOF, // uint to FP within a FP register. 62 63 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out. 64 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out. 65 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. 66 67 VMOVRRD, // double to two gprs. 68 VMOVDRR, // Two gprs to double. 69 70 EH_SJLJ_SETJMP, // SjLj exception handling setjmp. 71 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp. 72 73 THREAD_POINTER, 74 75 DYN_ALLOC, // Dynamic allocation on the stack. 76 77 MEMBARRIER, // Memory barrier 78 SYNCBARRIER, // Memory sync barrier 79 80 VCEQ, // Vector compare equal. 81 VCGE, // Vector compare greater than or equal. 82 VCGEU, // Vector compare unsigned greater than or equal. 83 VCGT, // Vector compare greater than. 84 VCGTU, // Vector compare unsigned greater than. 85 VTST, // Vector test bits. 86 87 // Vector shift by immediate: 88 VSHL, // ...left 89 VSHRs, // ...right (signed) 90 VSHRu, // ...right (unsigned) 91 VSHLLs, // ...left long (signed) 92 VSHLLu, // ...left long (unsigned) 93 VSHLLi, // ...left long (with maximum shift count) 94 VSHRN, // ...right narrow 95 96 // Vector rounding shift by immediate: 97 VRSHRs, // ...right (signed) 98 VRSHRu, // ...right (unsigned) 99 VRSHRN, // ...right narrow 100 101 // Vector saturating shift by immediate: 102 VQSHLs, // ...left (signed) 103 VQSHLu, // ...left (unsigned) 104 VQSHLsu, // ...left (signed to unsigned) 105 VQSHRNs, // ...right narrow (signed) 106 VQSHRNu, // ...right narrow (unsigned) 107 VQSHRNsu, // ...right narrow (signed to unsigned) 108 109 // Vector saturating rounding shift by immediate: 110 VQRSHRNs, // ...right narrow (signed) 111 VQRSHRNu, // ...right narrow (unsigned) 112 VQRSHRNsu, // ...right narrow (signed to unsigned) 113 114 // Vector shift and insert: 115 VSLI, // ...left 116 VSRI, // ...right 117 118 // Vector get lane (VMOV scalar to ARM core register) 119 // (These are used for 8- and 16-bit element types only.) 120 VGETLANEu, // zero-extend vector extract element 121 VGETLANEs, // sign-extend vector extract element 122 123 // Vector duplicate: 124 VDUP, 125 VDUPLANE, 126 127 // Vector shuffles: 128 VEXT, // extract 129 VREV64, // reverse elements within 64-bit doublewords 130 VREV32, // reverse elements within 32-bit words 131 VREV16, // reverse elements within 16-bit halfwords 132 VZIP, // zip (interleave) 133 VUZP, // unzip (deinterleave) 134 VTRN, // transpose 135 136 // Floating-point max and min: 137 FMAX, 138 FMIN 139 }; 140 } 141 142 /// Define some predicates that are used for node matching. 143 namespace ARM { 144 /// getVMOVImm - If this is a build_vector of constants which can be 145 /// formed by using a VMOV instruction of the specified element size, 146 /// return the constant being splatted. The ByteSize field indicates the 147 /// number of bytes of each element [1248]. 148 SDValue getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 149 150 /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be 151 /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd) 152 /// instruction, returns its 8-bit integer representation. Otherwise, 153 /// returns -1. 154 int getVFPf32Imm(const APFloat &FPImm); 155 int getVFPf64Imm(const APFloat &FPImm); 156 } 157 158 //===--------------------------------------------------------------------===// 159 // ARMTargetLowering - ARM Implementation of the TargetLowering interface 160 161 class ARMTargetLowering : public TargetLowering { 162 public: 163 explicit ARMTargetLowering(TargetMachine &TM); 164 165 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 166 167 /// ReplaceNodeResults - Replace the results of node with an illegal result 168 /// type with new values built out of custom code. 169 /// 170 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 171 SelectionDAG &DAG) const; 172 173 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 174 175 virtual const char *getTargetNodeName(unsigned Opcode) const; 176 177 virtual MachineBasicBlock * 178 EmitInstrWithCustomInserter(MachineInstr *MI, 179 MachineBasicBlock *MBB) const; 180 181 /// allowsUnalignedMemoryAccesses - Returns true if the target allows 182 /// unaligned memory accesses. of the specified type. 183 /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON? 184 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const; 185 186 /// isLegalAddressingMode - Return true if the addressing mode represented 187 /// by AM is legal for this target, for a load/store of the specified type. 188 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const; 189 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 190 191 /// isLegalICmpImmediate - Return true if the specified immediate is legal 192 /// icmp immediate, that is the target has icmp instructions which can compare 193 /// a register against the immediate without having to materialize the 194 /// immediate into a register. 195 virtual bool isLegalICmpImmediate(int64_t Imm) const; 196 197 /// getPreIndexedAddressParts - returns true by value, base pointer and 198 /// offset pointer and addressing mode by reference if the node's address 199 /// can be legally represented as pre-indexed load / store address. 200 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 201 SDValue &Offset, 202 ISD::MemIndexedMode &AM, 203 SelectionDAG &DAG) const; 204 205 /// getPostIndexedAddressParts - returns true by value, base pointer and 206 /// offset pointer and addressing mode by reference if this node can be 207 /// combined with a load / store to form a post-indexed load / store. 208 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 209 SDValue &Base, SDValue &Offset, 210 ISD::MemIndexedMode &AM, 211 SelectionDAG &DAG) const; 212 213 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 214 const APInt &Mask, 215 APInt &KnownZero, 216 APInt &KnownOne, 217 const SelectionDAG &DAG, 218 unsigned Depth) const; 219 220 221 ConstraintType getConstraintType(const std::string &Constraint) const; 222 std::pair<unsigned, const TargetRegisterClass*> 223 getRegForInlineAsmConstraint(const std::string &Constraint, 224 EVT VT) const; 225 std::vector<unsigned> 226 getRegClassForInlineAsmConstraint(const std::string &Constraint, 227 EVT VT) const; 228 229 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 230 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 231 /// true it means one of the asm constraint of the inline asm instruction 232 /// being processed is 'm'. 233 virtual void LowerAsmOperandForConstraint(SDValue Op, 234 char ConstraintLetter, 235 bool hasMemory, 236 std::vector<SDValue> &Ops, 237 SelectionDAG &DAG) const; 238 239 const ARMSubtarget* getSubtarget() const { 240 return Subtarget; 241 } 242 243 /// getRegClassFor - Return the register class that should be used for the 244 /// specified value type. 245 virtual TargetRegisterClass *getRegClassFor(EVT VT) const; 246 247 /// getFunctionAlignment - Return the Log2 alignment of this function. 248 virtual unsigned getFunctionAlignment(const Function *F) const; 249 250 Sched::Preference getSchedulingPreference(SDNode *N) const; 251 252 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const; 253 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 254 255 /// isFPImmLegal - Returns true if the target can instruction select the 256 /// specified FP immediate natively. If false, the legalizer will 257 /// materialize the FP immediate as a load from a constant pool. 258 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 259 260 private: 261 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 262 /// make the right decision when generating code for different targets. 263 const ARMSubtarget *Subtarget; 264 265 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created. 266 /// 267 unsigned ARMPCLabelIndex; 268 269 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT); 270 void addDRTypeForNEON(EVT VT); 271 void addQRTypeForNEON(EVT VT); 272 273 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector; 274 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, 275 SDValue Chain, SDValue &Arg, 276 RegsToPassVector &RegsToPass, 277 CCValAssign &VA, CCValAssign &NextVA, 278 SDValue &StackPtr, 279 SmallVector<SDValue, 8> &MemOpChains, 280 ISD::ArgFlagsTy Flags) const; 281 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 282 SDValue &Root, SelectionDAG &DAG, 283 DebugLoc dl) const; 284 285 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, bool isVarArg) const; 286 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 287 DebugLoc dl, SelectionDAG &DAG, 288 const CCValAssign &VA, 289 ISD::ArgFlagsTy Flags) const; 290 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 291 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 292 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 293 const ARMSubtarget *Subtarget) const; 294 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 295 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 296 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const; 297 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 298 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 299 SelectionDAG &DAG) const; 300 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, 301 SelectionDAG &DAG) const; 302 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const; 303 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 304 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 305 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 306 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 307 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 308 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 309 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; 310 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 311 312 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 313 CallingConv::ID CallConv, bool isVarArg, 314 const SmallVectorImpl<ISD::InputArg> &Ins, 315 DebugLoc dl, SelectionDAG &DAG, 316 SmallVectorImpl<SDValue> &InVals) const; 317 318 virtual SDValue 319 LowerFormalArguments(SDValue Chain, 320 CallingConv::ID CallConv, bool isVarArg, 321 const SmallVectorImpl<ISD::InputArg> &Ins, 322 DebugLoc dl, SelectionDAG &DAG, 323 SmallVectorImpl<SDValue> &InVals) const; 324 325 virtual SDValue 326 LowerCall(SDValue Chain, SDValue Callee, 327 CallingConv::ID CallConv, bool isVarArg, 328 bool &isTailCall, 329 const SmallVectorImpl<ISD::OutputArg> &Outs, 330 const SmallVectorImpl<ISD::InputArg> &Ins, 331 DebugLoc dl, SelectionDAG &DAG, 332 SmallVectorImpl<SDValue> &InVals) const; 333 334 virtual SDValue 335 LowerReturn(SDValue Chain, 336 CallingConv::ID CallConv, bool isVarArg, 337 const SmallVectorImpl<ISD::OutputArg> &Outs, 338 DebugLoc dl, SelectionDAG &DAG) const; 339 340 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 341 SDValue &ARMCC, SelectionDAG &DAG, DebugLoc dl) const; 342 343 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI, 344 MachineBasicBlock *BB, 345 unsigned Size) const; 346 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 347 MachineBasicBlock *BB, 348 unsigned Size, 349 unsigned BinOpcode) const; 350 351 }; 352} 353 354#endif // ARMISELLOWERING_H 355