ARMISelLowering.h revision 44d23825d61d530b8d562329ec8fc2d4f843bb8d
1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef ARMISELLOWERING_H 16#define ARMISELLOWERING_H 17 18#include "ARMSubtarget.h" 19#include "llvm/Target/TargetLowering.h" 20#include "llvm/Target/TargetRegisterInfo.h" 21#include "llvm/CodeGen/FastISel.h" 22#include "llvm/CodeGen/SelectionDAG.h" 23#include "llvm/CodeGen/CallingConvLower.h" 24#include <vector> 25 26namespace llvm { 27 class ARMConstantPoolValue; 28 29 namespace ARMISD { 30 // ARM Specific DAG Nodes 31 enum NodeType { 32 // Start the numbering where the builtin ops and target ops leave off. 33 FIRST_NUMBER = ISD::BUILTIN_OP_END, 34 35 Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 36 // TargetExternalSymbol, and TargetGlobalAddress. 37 WrapperDYN, // WrapperDYN - A wrapper node for TargetGlobalAddress in 38 // DYN mode. 39 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in 40 // PIC mode. 41 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 42 43 CALL, // Function call. 44 CALL_PRED, // Function call that's predicable. 45 CALL_NOLINK, // Function call with branch not branch-and-link. 46 tCALL, // Thumb function call. 47 BRCOND, // Conditional branch. 48 BR_JT, // Jumptable branch. 49 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). 50 RET_FLAG, // Return with a flag operand. 51 52 PIC_ADD, // Add with a PC operand and a PIC label. 53 54 CMP, // ARM compare instructions. 55 CMPZ, // ARM compare that sets only Z flag. 56 CMPFP, // ARM VFP compare instruction, sets FPSCR. 57 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR. 58 FMSTAT, // ARM fmstat instruction. 59 CMOV, // ARM conditional move instructions. 60 61 BCC_i64, 62 63 RBIT, // ARM bitreverse instruction 64 65 FTOSI, // FP to sint within a FP register. 66 FTOUI, // FP to uint within a FP register. 67 SITOF, // sint to FP within a FP register. 68 UITOF, // uint to FP within a FP register. 69 70 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out. 71 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out. 72 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. 73 74 ADDC, // Add with carry 75 ADDE, // Add using carry 76 SUBC, // Sub with carry 77 SUBE, // Sub using carry 78 79 VMOVRRD, // double to two gprs. 80 VMOVDRR, // Two gprs to double. 81 82 EH_SJLJ_SETJMP, // SjLj exception handling setjmp. 83 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp. 84 85 TC_RETURN, // Tail call return pseudo. 86 87 THREAD_POINTER, 88 89 DYN_ALLOC, // Dynamic allocation on the stack. 90 91 MEMBARRIER, // Memory barrier (DMB) 92 MEMBARRIER_MCR, // Memory barrier (MCR) 93 94 PRELOAD, // Preload 95 96 VCEQ, // Vector compare equal. 97 VCEQZ, // Vector compare equal to zero. 98 VCGE, // Vector compare greater than or equal. 99 VCGEZ, // Vector compare greater than or equal to zero. 100 VCLEZ, // Vector compare less than or equal to zero. 101 VCGEU, // Vector compare unsigned greater than or equal. 102 VCGT, // Vector compare greater than. 103 VCGTZ, // Vector compare greater than zero. 104 VCLTZ, // Vector compare less than zero. 105 VCGTU, // Vector compare unsigned greater than. 106 VTST, // Vector test bits. 107 108 // Vector shift by immediate: 109 VSHL, // ...left 110 VSHRs, // ...right (signed) 111 VSHRu, // ...right (unsigned) 112 VSHLLs, // ...left long (signed) 113 VSHLLu, // ...left long (unsigned) 114 VSHLLi, // ...left long (with maximum shift count) 115 VSHRN, // ...right narrow 116 117 // Vector rounding shift by immediate: 118 VRSHRs, // ...right (signed) 119 VRSHRu, // ...right (unsigned) 120 VRSHRN, // ...right narrow 121 122 // Vector saturating shift by immediate: 123 VQSHLs, // ...left (signed) 124 VQSHLu, // ...left (unsigned) 125 VQSHLsu, // ...left (signed to unsigned) 126 VQSHRNs, // ...right narrow (signed) 127 VQSHRNu, // ...right narrow (unsigned) 128 VQSHRNsu, // ...right narrow (signed to unsigned) 129 130 // Vector saturating rounding shift by immediate: 131 VQRSHRNs, // ...right narrow (signed) 132 VQRSHRNu, // ...right narrow (unsigned) 133 VQRSHRNsu, // ...right narrow (signed to unsigned) 134 135 // Vector shift and insert: 136 VSLI, // ...left 137 VSRI, // ...right 138 139 // Vector get lane (VMOV scalar to ARM core register) 140 // (These are used for 8- and 16-bit element types only.) 141 VGETLANEu, // zero-extend vector extract element 142 VGETLANEs, // sign-extend vector extract element 143 144 // Vector move immediate and move negated immediate: 145 VMOVIMM, 146 VMVNIMM, 147 148 // Vector move f32 immediate: 149 VMOVFPIMM, 150 151 // Vector duplicate: 152 VDUP, 153 VDUPLANE, 154 155 // Vector shuffles: 156 VEXT, // extract 157 VREV64, // reverse elements within 64-bit doublewords 158 VREV32, // reverse elements within 32-bit words 159 VREV16, // reverse elements within 16-bit halfwords 160 VZIP, // zip (interleave) 161 VUZP, // unzip (deinterleave) 162 VTRN, // transpose 163 VTBL1, // 1-register shuffle with mask 164 VTBL2, // 2-register shuffle with mask 165 166 // Vector multiply long: 167 VMULLs, // ...signed 168 VMULLu, // ...unsigned 169 170 // Operands of the standard BUILD_VECTOR node are not legalized, which 171 // is fine if BUILD_VECTORs are always lowered to shuffles or other 172 // operations, but for ARM some BUILD_VECTORs are legal as-is and their 173 // operands need to be legalized. Define an ARM-specific version of 174 // BUILD_VECTOR for this purpose. 175 BUILD_VECTOR, 176 177 // Floating-point max and min: 178 FMAX, 179 FMIN, 180 181 // Bit-field insert 182 BFI, 183 184 // Vector OR with immediate 185 VORRIMM, 186 // Vector AND with NOT of immediate 187 VBICIMM, 188 189 // Vector bitwise select 190 VBSL, 191 192 // Vector load N-element structure to all lanes: 193 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE, 194 VLD3DUP, 195 VLD4DUP, 196 197 // NEON loads with post-increment base updates: 198 VLD1_UPD, 199 VLD2_UPD, 200 VLD3_UPD, 201 VLD4_UPD, 202 VLD2LN_UPD, 203 VLD3LN_UPD, 204 VLD4LN_UPD, 205 VLD2DUP_UPD, 206 VLD3DUP_UPD, 207 VLD4DUP_UPD, 208 209 // NEON stores with post-increment base updates: 210 VST1_UPD, 211 VST2_UPD, 212 VST3_UPD, 213 VST4_UPD, 214 VST2LN_UPD, 215 VST3LN_UPD, 216 VST4LN_UPD, 217 218 // 64-bit atomic ops (value split into two registers) 219 ATOMADD64_DAG, 220 ATOMSUB64_DAG, 221 ATOMOR64_DAG, 222 ATOMXOR64_DAG, 223 ATOMAND64_DAG, 224 ATOMNAND64_DAG, 225 ATOMSWAP64_DAG, 226 ATOMCMPXCHG64_DAG 227 }; 228 } 229 230 /// Define some predicates that are used for node matching. 231 namespace ARM { 232 bool isBitFieldInvertedMask(unsigned v); 233 } 234 235 //===--------------------------------------------------------------------===// 236 // ARMTargetLowering - ARM Implementation of the TargetLowering interface 237 238 class ARMTargetLowering : public TargetLowering { 239 public: 240 explicit ARMTargetLowering(TargetMachine &TM); 241 242 virtual unsigned getJumpTableEncoding(void) const; 243 244 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 245 246 /// ReplaceNodeResults - Replace the results of node with an illegal result 247 /// type with new values built out of custom code. 248 /// 249 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 250 SelectionDAG &DAG) const; 251 252 virtual const char *getTargetNodeName(unsigned Opcode) const; 253 254 /// getSetCCResultType - Return the value type to use for ISD::SETCC. 255 virtual EVT getSetCCResultType(EVT VT) const; 256 257 virtual MachineBasicBlock * 258 EmitInstrWithCustomInserter(MachineInstr *MI, 259 MachineBasicBlock *MBB) const; 260 261 virtual void 262 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const; 263 264 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const; 265 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 266 267 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const; 268 269 /// allowsUnalignedMemoryAccesses - Returns true if the target allows 270 /// unaligned memory accesses. of the specified type. 271 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const; 272 273 virtual EVT getOptimalMemOpType(uint64_t Size, 274 unsigned DstAlign, unsigned SrcAlign, 275 bool IsZeroVal, 276 bool MemcpyStrSrc, 277 MachineFunction &MF) const; 278 279 /// isLegalAddressingMode - Return true if the addressing mode represented 280 /// by AM is legal for this target, for a load/store of the specified type. 281 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const; 282 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 283 284 /// isLegalICmpImmediate - Return true if the specified immediate is legal 285 /// icmp immediate, that is the target has icmp instructions which can 286 /// compare a register against the immediate without having to materialize 287 /// the immediate into a register. 288 virtual bool isLegalICmpImmediate(int64_t Imm) const; 289 290 /// isLegalAddImmediate - Return true if the specified immediate is legal 291 /// add immediate, that is the target has add instructions which can 292 /// add a register and the immediate without having to materialize 293 /// the immediate into a register. 294 virtual bool isLegalAddImmediate(int64_t Imm) const; 295 296 /// getPreIndexedAddressParts - returns true by value, base pointer and 297 /// offset pointer and addressing mode by reference if the node's address 298 /// can be legally represented as pre-indexed load / store address. 299 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 300 SDValue &Offset, 301 ISD::MemIndexedMode &AM, 302 SelectionDAG &DAG) const; 303 304 /// getPostIndexedAddressParts - returns true by value, base pointer and 305 /// offset pointer and addressing mode by reference if this node can be 306 /// combined with a load / store to form a post-indexed load / store. 307 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 308 SDValue &Base, SDValue &Offset, 309 ISD::MemIndexedMode &AM, 310 SelectionDAG &DAG) const; 311 312 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 313 const APInt &Mask, 314 APInt &KnownZero, 315 APInt &KnownOne, 316 const SelectionDAG &DAG, 317 unsigned Depth) const; 318 319 320 virtual bool ExpandInlineAsm(CallInst *CI) const; 321 322 ConstraintType getConstraintType(const std::string &Constraint) const; 323 324 /// Examine constraint string and operand type and determine a weight value. 325 /// The operand object must already have been set up with the operand type. 326 ConstraintWeight getSingleConstraintMatchWeight( 327 AsmOperandInfo &info, const char *constraint) const; 328 329 std::pair<unsigned, const TargetRegisterClass*> 330 getRegForInlineAsmConstraint(const std::string &Constraint, 331 EVT VT) const; 332 333 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 334 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 335 /// true it means one of the asm constraint of the inline asm instruction 336 /// being processed is 'm'. 337 virtual void LowerAsmOperandForConstraint(SDValue Op, 338 std::string &Constraint, 339 std::vector<SDValue> &Ops, 340 SelectionDAG &DAG) const; 341 342 const ARMSubtarget* getSubtarget() const { 343 return Subtarget; 344 } 345 346 /// getRegClassFor - Return the register class that should be used for the 347 /// specified value type. 348 virtual const TargetRegisterClass *getRegClassFor(EVT VT) const; 349 350 /// getMaximalGlobalOffset - Returns the maximal possible offset which can 351 /// be used for loads / stores from the global. 352 virtual unsigned getMaximalGlobalOffset() const; 353 354 /// createFastISel - This method returns a target specific FastISel object, 355 /// or null if the target does not support "fast" ISel. 356 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const; 357 358 Sched::Preference getSchedulingPreference(SDNode *N) const; 359 360 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const; 361 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 362 363 /// isFPImmLegal - Returns true if the target can instruction select the 364 /// specified FP immediate natively. If false, the legalizer will 365 /// materialize the FP immediate as a load from a constant pool. 366 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 367 368 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, 369 const CallInst &I, 370 unsigned Intrinsic) const; 371 protected: 372 std::pair<const TargetRegisterClass*, uint8_t> 373 findRepresentativeClass(EVT VT) const; 374 375 private: 376 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 377 /// make the right decision when generating code for different targets. 378 const ARMSubtarget *Subtarget; 379 380 const TargetRegisterInfo *RegInfo; 381 382 const InstrItineraryData *Itins; 383 384 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created. 385 /// 386 unsigned ARMPCLabelIndex; 387 388 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT); 389 void addDRTypeForNEON(EVT VT); 390 void addQRTypeForNEON(EVT VT); 391 392 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector; 393 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, 394 SDValue Chain, SDValue &Arg, 395 RegsToPassVector &RegsToPass, 396 CCValAssign &VA, CCValAssign &NextVA, 397 SDValue &StackPtr, 398 SmallVector<SDValue, 8> &MemOpChains, 399 ISD::ArgFlagsTy Flags) const; 400 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 401 SDValue &Root, SelectionDAG &DAG, 402 DebugLoc dl) const; 403 404 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, 405 bool isVarArg) const; 406 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 407 DebugLoc dl, SelectionDAG &DAG, 408 const CCValAssign &VA, 409 ISD::ArgFlagsTy Flags) const; 410 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 411 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 412 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 413 const ARMSubtarget *Subtarget) const; 414 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 415 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 416 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const; 417 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 418 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 419 SelectionDAG &DAG) const; 420 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, 421 SelectionDAG &DAG) const; 422 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const; 423 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 424 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 425 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 426 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 427 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 428 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 429 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 430 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; 431 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 432 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 433 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 434 const ARMSubtarget *ST) const; 435 436 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const; 437 438 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 439 CallingConv::ID CallConv, bool isVarArg, 440 const SmallVectorImpl<ISD::InputArg> &Ins, 441 DebugLoc dl, SelectionDAG &DAG, 442 SmallVectorImpl<SDValue> &InVals) const; 443 444 virtual SDValue 445 LowerFormalArguments(SDValue Chain, 446 CallingConv::ID CallConv, bool isVarArg, 447 const SmallVectorImpl<ISD::InputArg> &Ins, 448 DebugLoc dl, SelectionDAG &DAG, 449 SmallVectorImpl<SDValue> &InVals) const; 450 451 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, 452 DebugLoc dl, SDValue &Chain, unsigned ArgOffset) 453 const; 454 455 void computeRegArea(CCState &CCInfo, MachineFunction &MF, 456 unsigned &VARegSize, unsigned &VARegSaveSize) const; 457 458 virtual SDValue 459 LowerCall(SDValue Chain, SDValue Callee, 460 CallingConv::ID CallConv, bool isVarArg, 461 bool &isTailCall, 462 const SmallVectorImpl<ISD::OutputArg> &Outs, 463 const SmallVectorImpl<SDValue> &OutVals, 464 const SmallVectorImpl<ISD::InputArg> &Ins, 465 DebugLoc dl, SelectionDAG &DAG, 466 SmallVectorImpl<SDValue> &InVals) const; 467 468 /// HandleByVal - Target-specific cleanup for ByVal support. 469 virtual void HandleByVal(CCState *, unsigned &) const; 470 471 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 472 /// for tail call optimization. Targets which want to do tail call 473 /// optimization should implement this function. 474 bool IsEligibleForTailCallOptimization(SDValue Callee, 475 CallingConv::ID CalleeCC, 476 bool isVarArg, 477 bool isCalleeStructRet, 478 bool isCallerStructRet, 479 const SmallVectorImpl<ISD::OutputArg> &Outs, 480 const SmallVectorImpl<SDValue> &OutVals, 481 const SmallVectorImpl<ISD::InputArg> &Ins, 482 SelectionDAG& DAG) const; 483 virtual SDValue 484 LowerReturn(SDValue Chain, 485 CallingConv::ID CallConv, bool isVarArg, 486 const SmallVectorImpl<ISD::OutputArg> &Outs, 487 const SmallVectorImpl<SDValue> &OutVals, 488 DebugLoc dl, SelectionDAG &DAG) const; 489 490 virtual bool isUsedByReturnOnly(SDNode *N) const; 491 492 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const; 493 494 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 495 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const; 496 SDValue getVFPCmp(SDValue LHS, SDValue RHS, 497 SelectionDAG &DAG, DebugLoc dl) const; 498 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const; 499 500 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const; 501 502 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI, 503 MachineBasicBlock *BB, 504 unsigned Size) const; 505 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 506 MachineBasicBlock *BB, 507 unsigned Size, 508 unsigned BinOpcode) const; 509 MachineBasicBlock *EmitAtomicBinary64(MachineInstr *MI, 510 MachineBasicBlock *BB, 511 unsigned Op1, 512 unsigned Op2, 513 bool NeedsCarry = false, 514 bool IsCmpxchg = false) const; 515 MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI, 516 MachineBasicBlock *BB, 517 unsigned Size, 518 bool signExtend, 519 ARMCC::CondCodes Cond) const; 520 521 void SetupEntryBlockForSjLj(MachineInstr *MI, 522 MachineBasicBlock *MBB, 523 MachineBasicBlock *DispatchBB, int FI) const; 524 525 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI, 526 MachineBasicBlock *MBB) const; 527 528 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const; 529 }; 530 531 enum NEONModImmType { 532 VMOVModImm, 533 VMVNModImm, 534 OtherModImm 535 }; 536 537 538 namespace ARM { 539 FastISel *createFastISel(FunctionLoweringInfo &funcInfo); 540 } 541} 542 543#endif // ARMISELLOWERING_H 544