ARMISelLowering.h revision bcc4c1d2d1b6877418de92835c537d79d44363a6
1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef ARMISELLOWERING_H 16#define ARMISELLOWERING_H 17 18#include "ARM.h" 19#include "ARMSubtarget.h" 20#include "llvm/Target/TargetLowering.h" 21#include "llvm/Target/TargetRegisterInfo.h" 22#include "llvm/CodeGen/FastISel.h" 23#include "llvm/CodeGen/SelectionDAG.h" 24#include "llvm/CodeGen/CallingConvLower.h" 25#include <vector> 26 27namespace llvm { 28 class ARMConstantPoolValue; 29 30 namespace ARMISD { 31 // ARM Specific DAG Nodes 32 enum NodeType { 33 // Start the numbering where the builtin ops and target ops leave off. 34 FIRST_NUMBER = ISD::BUILTIN_OP_END, 35 36 Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 37 // TargetExternalSymbol, and TargetGlobalAddress. 38 WrapperDYN, // WrapperDYN - A wrapper node for TargetGlobalAddress in 39 // DYN mode. 40 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in 41 // PIC mode. 42 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 43 44 // Add pseudo op to model memcpy for struct byval. 45 COPY_STRUCT_BYVAL, 46 47 CALL, // Function call. 48 CALL_PRED, // Function call that's predicable. 49 CALL_NOLINK, // Function call with branch not branch-and-link. 50 tCALL, // Thumb function call. 51 BRCOND, // Conditional branch. 52 BR_JT, // Jumptable branch. 53 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). 54 RET_FLAG, // Return with a flag operand. 55 56 PIC_ADD, // Add with a PC operand and a PIC label. 57 58 CMP, // ARM compare instructions. 59 CMN, // ARM CMN instructions. 60 CMPZ, // ARM compare that sets only Z flag. 61 CMPFP, // ARM VFP compare instruction, sets FPSCR. 62 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR. 63 FMSTAT, // ARM fmstat instruction. 64 65 CMOV, // ARM conditional move instructions. 66 CAND, // ARM conditional and instructions. 67 COR, // ARM conditional or instructions. 68 CXOR, // ARM conditional xor instructions. 69 70 BCC_i64, 71 72 RBIT, // ARM bitreverse instruction 73 74 FTOSI, // FP to sint within a FP register. 75 FTOUI, // FP to uint within a FP register. 76 SITOF, // sint to FP within a FP register. 77 UITOF, // uint to FP within a FP register. 78 79 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out. 80 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out. 81 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. 82 83 ADDC, // Add with carry 84 ADDE, // Add using carry 85 SUBC, // Sub with carry 86 SUBE, // Sub using carry 87 88 VMOVRRD, // double to two gprs. 89 VMOVDRR, // Two gprs to double. 90 91 EH_SJLJ_SETJMP, // SjLj exception handling setjmp. 92 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp. 93 94 TC_RETURN, // Tail call return pseudo. 95 96 THREAD_POINTER, 97 98 DYN_ALLOC, // Dynamic allocation on the stack. 99 100 MEMBARRIER, // Memory barrier (DMB) 101 MEMBARRIER_MCR, // Memory barrier (MCR) 102 103 PRELOAD, // Preload 104 105 VCEQ, // Vector compare equal. 106 VCEQZ, // Vector compare equal to zero. 107 VCGE, // Vector compare greater than or equal. 108 VCGEZ, // Vector compare greater than or equal to zero. 109 VCLEZ, // Vector compare less than or equal to zero. 110 VCGEU, // Vector compare unsigned greater than or equal. 111 VCGT, // Vector compare greater than. 112 VCGTZ, // Vector compare greater than zero. 113 VCLTZ, // Vector compare less than zero. 114 VCGTU, // Vector compare unsigned greater than. 115 VTST, // Vector test bits. 116 117 // Vector shift by immediate: 118 VSHL, // ...left 119 VSHRs, // ...right (signed) 120 VSHRu, // ...right (unsigned) 121 VSHLLs, // ...left long (signed) 122 VSHLLu, // ...left long (unsigned) 123 VSHLLi, // ...left long (with maximum shift count) 124 VSHRN, // ...right narrow 125 126 // Vector rounding shift by immediate: 127 VRSHRs, // ...right (signed) 128 VRSHRu, // ...right (unsigned) 129 VRSHRN, // ...right narrow 130 131 // Vector saturating shift by immediate: 132 VQSHLs, // ...left (signed) 133 VQSHLu, // ...left (unsigned) 134 VQSHLsu, // ...left (signed to unsigned) 135 VQSHRNs, // ...right narrow (signed) 136 VQSHRNu, // ...right narrow (unsigned) 137 VQSHRNsu, // ...right narrow (signed to unsigned) 138 139 // Vector saturating rounding shift by immediate: 140 VQRSHRNs, // ...right narrow (signed) 141 VQRSHRNu, // ...right narrow (unsigned) 142 VQRSHRNsu, // ...right narrow (signed to unsigned) 143 144 // Vector shift and insert: 145 VSLI, // ...left 146 VSRI, // ...right 147 148 // Vector get lane (VMOV scalar to ARM core register) 149 // (These are used for 8- and 16-bit element types only.) 150 VGETLANEu, // zero-extend vector extract element 151 VGETLANEs, // sign-extend vector extract element 152 153 // Vector move immediate and move negated immediate: 154 VMOVIMM, 155 VMVNIMM, 156 157 // Vector move f32 immediate: 158 VMOVFPIMM, 159 160 // Vector duplicate: 161 VDUP, 162 VDUPLANE, 163 164 // Vector shuffles: 165 VEXT, // extract 166 VREV64, // reverse elements within 64-bit doublewords 167 VREV32, // reverse elements within 32-bit words 168 VREV16, // reverse elements within 16-bit halfwords 169 VZIP, // zip (interleave) 170 VUZP, // unzip (deinterleave) 171 VTRN, // transpose 172 VTBL1, // 1-register shuffle with mask 173 VTBL2, // 2-register shuffle with mask 174 175 // Vector multiply long: 176 VMULLs, // ...signed 177 VMULLu, // ...unsigned 178 179 UMLAL, // 64bit Unsigned Accumulate Multiply 180 SMLAL, // 64bit Signed Accumulate Multiply 181 182 // Operands of the standard BUILD_VECTOR node are not legalized, which 183 // is fine if BUILD_VECTORs are always lowered to shuffles or other 184 // operations, but for ARM some BUILD_VECTORs are legal as-is and their 185 // operands need to be legalized. Define an ARM-specific version of 186 // BUILD_VECTOR for this purpose. 187 BUILD_VECTOR, 188 189 // Floating-point max and min: 190 FMAX, 191 FMIN, 192 193 // Bit-field insert 194 BFI, 195 196 // Vector OR with immediate 197 VORRIMM, 198 // Vector AND with NOT of immediate 199 VBICIMM, 200 201 // Vector bitwise select 202 VBSL, 203 204 // Vector load N-element structure to all lanes: 205 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE, 206 VLD3DUP, 207 VLD4DUP, 208 209 // NEON loads with post-increment base updates: 210 VLD1_UPD, 211 VLD2_UPD, 212 VLD3_UPD, 213 VLD4_UPD, 214 VLD2LN_UPD, 215 VLD3LN_UPD, 216 VLD4LN_UPD, 217 VLD2DUP_UPD, 218 VLD3DUP_UPD, 219 VLD4DUP_UPD, 220 221 // NEON stores with post-increment base updates: 222 VST1_UPD, 223 VST2_UPD, 224 VST3_UPD, 225 VST4_UPD, 226 VST2LN_UPD, 227 VST3LN_UPD, 228 VST4LN_UPD, 229 230 // 64-bit atomic ops (value split into two registers) 231 ATOMADD64_DAG, 232 ATOMSUB64_DAG, 233 ATOMOR64_DAG, 234 ATOMXOR64_DAG, 235 ATOMAND64_DAG, 236 ATOMNAND64_DAG, 237 ATOMSWAP64_DAG, 238 ATOMCMPXCHG64_DAG 239 }; 240 } 241 242 /// Define some predicates that are used for node matching. 243 namespace ARM { 244 bool isBitFieldInvertedMask(unsigned v); 245 } 246 247 //===--------------------------------------------------------------------===// 248 // ARMTargetLowering - ARM Implementation of the TargetLowering interface 249 250 class ARMTargetLowering : public TargetLowering { 251 public: 252 explicit ARMTargetLowering(TargetMachine &TM); 253 254 virtual unsigned getJumpTableEncoding(void) const; 255 256 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 257 258 /// ReplaceNodeResults - Replace the results of node with an illegal result 259 /// type with new values built out of custom code. 260 /// 261 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 262 SelectionDAG &DAG) const; 263 264 virtual const char *getTargetNodeName(unsigned Opcode) const; 265 266 /// getSetCCResultType - Return the value type to use for ISD::SETCC. 267 virtual EVT getSetCCResultType(EVT VT) const; 268 269 virtual MachineBasicBlock * 270 EmitInstrWithCustomInserter(MachineInstr *MI, 271 MachineBasicBlock *MBB) const; 272 273 virtual void 274 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const; 275 276 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const; 277 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 278 279 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const; 280 281 /// allowsUnalignedMemoryAccesses - Returns true if the target allows 282 /// unaligned memory accesses. of the specified type. 283 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const; 284 285 virtual EVT getOptimalMemOpType(uint64_t Size, 286 unsigned DstAlign, unsigned SrcAlign, 287 bool IsZeroVal, 288 bool MemcpyStrSrc, 289 MachineFunction &MF) const; 290 291 /// isLegalAddressingMode - Return true if the addressing mode represented 292 /// by AM is legal for this target, for a load/store of the specified type. 293 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const; 294 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 295 296 /// isLegalICmpImmediate - Return true if the specified immediate is legal 297 /// icmp immediate, that is the target has icmp instructions which can 298 /// compare a register against the immediate without having to materialize 299 /// the immediate into a register. 300 virtual bool isLegalICmpImmediate(int64_t Imm) const; 301 302 /// isLegalAddImmediate - Return true if the specified immediate is legal 303 /// add immediate, that is the target has add instructions which can 304 /// add a register and the immediate without having to materialize 305 /// the immediate into a register. 306 virtual bool isLegalAddImmediate(int64_t Imm) const; 307 308 /// getPreIndexedAddressParts - returns true by value, base pointer and 309 /// offset pointer and addressing mode by reference if the node's address 310 /// can be legally represented as pre-indexed load / store address. 311 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 312 SDValue &Offset, 313 ISD::MemIndexedMode &AM, 314 SelectionDAG &DAG) const; 315 316 /// getPostIndexedAddressParts - returns true by value, base pointer and 317 /// offset pointer and addressing mode by reference if this node can be 318 /// combined with a load / store to form a post-indexed load / store. 319 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 320 SDValue &Base, SDValue &Offset, 321 ISD::MemIndexedMode &AM, 322 SelectionDAG &DAG) const; 323 324 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 325 APInt &KnownZero, 326 APInt &KnownOne, 327 const SelectionDAG &DAG, 328 unsigned Depth) const; 329 330 331 virtual bool ExpandInlineAsm(CallInst *CI) const; 332 333 ConstraintType getConstraintType(const std::string &Constraint) const; 334 335 /// Examine constraint string and operand type and determine a weight value. 336 /// The operand object must already have been set up with the operand type. 337 ConstraintWeight getSingleConstraintMatchWeight( 338 AsmOperandInfo &info, const char *constraint) const; 339 340 std::pair<unsigned, const TargetRegisterClass*> 341 getRegForInlineAsmConstraint(const std::string &Constraint, 342 EVT VT) const; 343 344 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 345 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 346 /// true it means one of the asm constraint of the inline asm instruction 347 /// being processed is 'm'. 348 virtual void LowerAsmOperandForConstraint(SDValue Op, 349 std::string &Constraint, 350 std::vector<SDValue> &Ops, 351 SelectionDAG &DAG) const; 352 353 const ARMSubtarget* getSubtarget() const { 354 return Subtarget; 355 } 356 357 /// getRegClassFor - Return the register class that should be used for the 358 /// specified value type. 359 virtual const TargetRegisterClass *getRegClassFor(EVT VT) const; 360 361 /// getMaximalGlobalOffset - Returns the maximal possible offset which can 362 /// be used for loads / stores from the global. 363 virtual unsigned getMaximalGlobalOffset() const; 364 365 /// createFastISel - This method returns a target specific FastISel object, 366 /// or null if the target does not support "fast" ISel. 367 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 368 const TargetLibraryInfo *libInfo) const; 369 370 Sched::Preference getSchedulingPreference(SDNode *N) const; 371 372 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const; 373 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 374 375 /// isFPImmLegal - Returns true if the target can instruction select the 376 /// specified FP immediate natively. If false, the legalizer will 377 /// materialize the FP immediate as a load from a constant pool. 378 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 379 380 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, 381 const CallInst &I, 382 unsigned Intrinsic) const; 383 protected: 384 std::pair<const TargetRegisterClass*, uint8_t> 385 findRepresentativeClass(EVT VT) const; 386 387 private: 388 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 389 /// make the right decision when generating code for different targets. 390 const ARMSubtarget *Subtarget; 391 392 const TargetRegisterInfo *RegInfo; 393 394 const InstrItineraryData *Itins; 395 396 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created. 397 /// 398 unsigned ARMPCLabelIndex; 399 400 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT); 401 void addDRTypeForNEON(EVT VT); 402 void addQRTypeForNEON(EVT VT); 403 404 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector; 405 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, 406 SDValue Chain, SDValue &Arg, 407 RegsToPassVector &RegsToPass, 408 CCValAssign &VA, CCValAssign &NextVA, 409 SDValue &StackPtr, 410 SmallVector<SDValue, 8> &MemOpChains, 411 ISD::ArgFlagsTy Flags) const; 412 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 413 SDValue &Root, SelectionDAG &DAG, 414 DebugLoc dl) const; 415 416 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, 417 bool isVarArg) const; 418 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 419 DebugLoc dl, SelectionDAG &DAG, 420 const CCValAssign &VA, 421 ISD::ArgFlagsTy Flags) const; 422 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 423 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 424 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 425 const ARMSubtarget *Subtarget) const; 426 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 427 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 428 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const; 429 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 430 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 431 SelectionDAG &DAG) const; 432 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, 433 SelectionDAG &DAG, 434 TLSModel::Model model) const; 435 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const; 436 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 437 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 438 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 439 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 440 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 441 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 442 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 443 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; 444 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 445 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 446 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG, 447 const ARMSubtarget *ST) const; 448 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 449 const ARMSubtarget *ST) const; 450 451 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const; 452 453 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 454 CallingConv::ID CallConv, bool isVarArg, 455 const SmallVectorImpl<ISD::InputArg> &Ins, 456 DebugLoc dl, SelectionDAG &DAG, 457 SmallVectorImpl<SDValue> &InVals) const; 458 459 virtual SDValue 460 LowerFormalArguments(SDValue Chain, 461 CallingConv::ID CallConv, bool isVarArg, 462 const SmallVectorImpl<ISD::InputArg> &Ins, 463 DebugLoc dl, SelectionDAG &DAG, 464 SmallVectorImpl<SDValue> &InVals) const; 465 466 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, 467 DebugLoc dl, SDValue &Chain, unsigned ArgOffset) 468 const; 469 470 void computeRegArea(CCState &CCInfo, MachineFunction &MF, 471 unsigned &VARegSize, unsigned &VARegSaveSize) const; 472 473 virtual SDValue 474 LowerCall(TargetLowering::CallLoweringInfo &CLI, 475 SmallVectorImpl<SDValue> &InVals) const; 476 477 /// HandleByVal - Target-specific cleanup for ByVal support. 478 virtual void HandleByVal(CCState *, unsigned &) const; 479 480 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 481 /// for tail call optimization. Targets which want to do tail call 482 /// optimization should implement this function. 483 bool IsEligibleForTailCallOptimization(SDValue Callee, 484 CallingConv::ID CalleeCC, 485 bool isVarArg, 486 bool isCalleeStructRet, 487 bool isCallerStructRet, 488 const SmallVectorImpl<ISD::OutputArg> &Outs, 489 const SmallVectorImpl<SDValue> &OutVals, 490 const SmallVectorImpl<ISD::InputArg> &Ins, 491 SelectionDAG& DAG) const; 492 virtual SDValue 493 LowerReturn(SDValue Chain, 494 CallingConv::ID CallConv, bool isVarArg, 495 const SmallVectorImpl<ISD::OutputArg> &Outs, 496 const SmallVectorImpl<SDValue> &OutVals, 497 DebugLoc dl, SelectionDAG &DAG) const; 498 499 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const; 500 501 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const; 502 503 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 504 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const; 505 SDValue getVFPCmp(SDValue LHS, SDValue RHS, 506 SelectionDAG &DAG, DebugLoc dl) const; 507 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const; 508 509 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const; 510 511 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI, 512 MachineBasicBlock *BB, 513 unsigned Size) const; 514 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 515 MachineBasicBlock *BB, 516 unsigned Size, 517 unsigned BinOpcode) const; 518 MachineBasicBlock *EmitAtomicBinary64(MachineInstr *MI, 519 MachineBasicBlock *BB, 520 unsigned Op1, 521 unsigned Op2, 522 bool NeedsCarry = false, 523 bool IsCmpxchg = false) const; 524 MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI, 525 MachineBasicBlock *BB, 526 unsigned Size, 527 bool signExtend, 528 ARMCC::CondCodes Cond) const; 529 530 void SetupEntryBlockForSjLj(MachineInstr *MI, 531 MachineBasicBlock *MBB, 532 MachineBasicBlock *DispatchBB, int FI) const; 533 534 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI, 535 MachineBasicBlock *MBB) const; 536 537 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const; 538 539 MachineBasicBlock *EmitStructByval(MachineInstr *MI, 540 MachineBasicBlock *MBB) const; 541 }; 542 543 enum NEONModImmType { 544 VMOVModImm, 545 VMVNModImm, 546 OtherModImm 547 }; 548 549 550 namespace ARM { 551 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 552 const TargetLibraryInfo *libInfo); 553 } 554} 555 556#endif // ARMISELLOWERING_H 557