HexagonPeephole.cpp revision 02d937d86420409210291accd9aa023d97b4a8b5 
1//===-- HexagonPeephole.cpp - Hexagon Peephole Optimiztions ---------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8// This peephole pass optimizes in the following cases.
9// 1. Optimizes redundant sign extends for the following case
10//    Transform the following pattern
11//    %vreg170<def> = SXTW %vreg166
12//    ...
13//    %vreg176<def> = COPY %vreg170:subreg_loreg
14//
15//    Into
16//    %vreg176<def> = COPY vreg166
17//
18//  2. Optimizes redundant negation of predicates.
19//     %vreg15<def> = CMPGTrr %vreg6, %vreg2
20//     ...
21//     %vreg16<def> = NOT_p %vreg15<kill>
22//     ...
23//     JMP_c %vreg16<kill>, <BB#1>, %PC<imp-def,dead>
24//
25//     Into
26//     %vreg15<def> = CMPGTrr %vreg6, %vreg2;
27//     ...
28//     JMP_cNot %vreg15<kill>, <BB#1>, %PC<imp-def,dead>;
29//
30// Note: The peephole pass makes the instrucstions like
31// %vreg170<def> = SXTW %vreg166 or %vreg16<def> = NOT_p %vreg15<kill>
32// redundant and relies on some form of dead removal instrucions, like
33// DCE or DIE to actually eliminate them.
34
35
36//===----------------------------------------------------------------------===//
37
38#define DEBUG_TYPE "hexagon-peephole"
39#include "Hexagon.h"
40#include "HexagonTargetMachine.h"
41#include "llvm/ADT/DenseMap.h"
42#include "llvm/ADT/Statistic.h"
43#include "llvm/CodeGen/MachineFunction.h"
44#include "llvm/CodeGen/MachineFunctionPass.h"
45#include "llvm/CodeGen/MachineInstrBuilder.h"
46#include "llvm/CodeGen/MachineRegisterInfo.h"
47#include "llvm/CodeGen/Passes.h"
48#include "llvm/IR/Constants.h"
49#include "llvm/PassSupport.h"
50#include "llvm/Support/CommandLine.h"
51#include "llvm/Support/Debug.h"
52#include "llvm/Support/raw_ostream.h"
53#include "llvm/Target/TargetInstrInfo.h"
54#include "llvm/Target/TargetMachine.h"
55#include "llvm/Target/TargetRegisterInfo.h"
56#include <algorithm>
57
58using namespace llvm;
59
60static cl::opt<bool> DisableHexagonPeephole("disable-hexagon-peephole",
61    cl::Hidden, cl::ZeroOrMore, cl::init(false),
62    cl::desc("Disable Peephole Optimization"));
63
64static cl::opt<int>
65DbgPNPCount("pnp-count", cl::init(-1), cl::Hidden,
66  cl::desc("Maximum number of P=NOT(P) to be optimized"));
67
68static cl::opt<bool> DisablePNotP("disable-hexagon-pnotp",
69    cl::Hidden, cl::ZeroOrMore, cl::init(false),
70    cl::desc("Disable Optimization of PNotP"));
71
72static cl::opt<bool> DisableOptSZExt("disable-hexagon-optszext",
73    cl::Hidden, cl::ZeroOrMore, cl::init(false),
74    cl::desc("Disable Optimization of Sign/Zero Extends"));
75
76static cl::opt<bool> DisableOptExtTo64("disable-hexagon-opt-ext-to-64",
77    cl::Hidden, cl::ZeroOrMore, cl::init(false),
78    cl::desc("Disable Optimization of extensions to i64."));
79
80namespace {
81  struct HexagonPeephole : public MachineFunctionPass {
82    const HexagonInstrInfo    *QII;
83    const HexagonRegisterInfo *QRI;
84    const MachineRegisterInfo *MRI;
85
86  public:
87    static char ID;
88    HexagonPeephole() : MachineFunctionPass(ID) { }
89
90    bool runOnMachineFunction(MachineFunction &MF);
91
92    const char *getPassName() const {
93      return "Hexagon optimize redundant zero and size extends";
94    }
95
96    void getAnalysisUsage(AnalysisUsage &AU) const {
97      MachineFunctionPass::getAnalysisUsage(AU);
98    }
99
100  private:
101    void ChangeOpInto(MachineOperand &Dst, MachineOperand &Src);
102  };
103}
104
105char HexagonPeephole::ID = 0;
106
107bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
108
109  QII = static_cast<const HexagonInstrInfo *>(MF.getTarget().
110                                        getInstrInfo());
111  QRI = static_cast<const HexagonRegisterInfo *>(MF.getTarget().
112                                       getRegisterInfo());
113  MRI = &MF.getRegInfo();
114
115  DenseMap<unsigned, unsigned> PeepholeMap;
116  DenseMap<unsigned, std::pair<unsigned, unsigned> > PeepholeDoubleRegsMap;
117
118  if (DisableHexagonPeephole) return false;
119
120  // Loop over all of the basic blocks.
121  for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
122       MBBb != MBBe; ++MBBb) {
123    MachineBasicBlock* MBB = MBBb;
124    PeepholeMap.clear();
125    PeepholeDoubleRegsMap.clear();
126
127    // Traverse the basic block.
128    for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end();
129                                     ++MII) {
130      MachineInstr *MI = MII;
131      // Look for sign extends:
132      // %vreg170<def> = SXTW %vreg166
133      if (!DisableOptSZExt && MI->getOpcode() == Hexagon::SXTW) {
134        assert (MI->getNumOperands() == 2);
135        MachineOperand &Dst = MI->getOperand(0);
136        MachineOperand &Src  = MI->getOperand(1);
137        unsigned DstReg = Dst.getReg();
138        unsigned SrcReg = Src.getReg();
139        // Just handle virtual registers.
140        if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
141            TargetRegisterInfo::isVirtualRegister(SrcReg)) {
142          // Map the following:
143          // %vreg170<def> = SXTW %vreg166
144          // PeepholeMap[170] = vreg166
145          PeepholeMap[DstReg] = SrcReg;
146        }
147      }
148
149      // Look for  %vreg170<def> = COMBINE_ir_V4 (0, %vreg169)
150      // %vreg170:DoublRegs, %vreg169:IntRegs
151      if (!DisableOptExtTo64 &&
152          MI->getOpcode () == Hexagon::COMBINE_Ir_V4) {
153        assert (MI->getNumOperands() == 3);
154        MachineOperand &Dst = MI->getOperand(0);
155        MachineOperand &Src1 = MI->getOperand(1);
156        MachineOperand &Src2 = MI->getOperand(2);
157        if (Src1.getImm() != 0)
158          continue;
159        unsigned DstReg = Dst.getReg();
160        unsigned SrcReg = Src2.getReg();
161        PeepholeMap[DstReg] = SrcReg;
162      }
163
164      // Look for this sequence below
165      // %vregDoubleReg1 = LSRd_ri %vregDoubleReg0, 32
166      // %vregIntReg = COPY %vregDoubleReg1:subreg_loreg.
167      // and convert into
168      // %vregIntReg = COPY %vregDoubleReg0:subreg_hireg.
169      if (MI->getOpcode() == Hexagon::LSRd_ri) {
170        assert(MI->getNumOperands() == 3);
171        MachineOperand &Dst = MI->getOperand(0);
172        MachineOperand &Src1 = MI->getOperand(1);
173        MachineOperand &Src2 = MI->getOperand(2);
174        if (Src2.getImm() != 32)
175          continue;
176        unsigned DstReg = Dst.getReg();
177        unsigned SrcReg = Src1.getReg();
178        PeepholeDoubleRegsMap[DstReg] =
179          std::make_pair(*&SrcReg, 1/*Hexagon::subreg_hireg*/);
180      }
181
182      // Look for P=NOT(P).
183      if (!DisablePNotP &&
184          (MI->getOpcode() == Hexagon::NOT_p)) {
185        assert (MI->getNumOperands() == 2);
186        MachineOperand &Dst = MI->getOperand(0);
187        MachineOperand &Src  = MI->getOperand(1);
188        unsigned DstReg = Dst.getReg();
189        unsigned SrcReg = Src.getReg();
190        // Just handle virtual registers.
191        if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
192            TargetRegisterInfo::isVirtualRegister(SrcReg)) {
193          // Map the following:
194          // %vreg170<def> = NOT_xx %vreg166
195          // PeepholeMap[170] = vreg166
196          PeepholeMap[DstReg] = SrcReg;
197        }
198      }
199
200      // Look for copy:
201      // %vreg176<def> = COPY %vreg170:subreg_loreg
202      if (!DisableOptSZExt && MI->isCopy()) {
203        assert (MI->getNumOperands() == 2);
204        MachineOperand &Dst = MI->getOperand(0);
205        MachineOperand &Src  = MI->getOperand(1);
206
207        // Make sure we are copying the lower 32 bits.
208        if (Src.getSubReg() != Hexagon::subreg_loreg)
209          continue;
210
211        unsigned DstReg = Dst.getReg();
212        unsigned SrcReg = Src.getReg();
213        if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
214            TargetRegisterInfo::isVirtualRegister(SrcReg)) {
215          // Try to find in the map.
216          if (unsigned PeepholeSrc = PeepholeMap.lookup(SrcReg)) {
217            // Change the 1st operand.
218            MI->RemoveOperand(1);
219            MI->addOperand(MachineOperand::CreateReg(PeepholeSrc, false));
220          } else  {
221            DenseMap<unsigned, std::pair<unsigned, unsigned> >::iterator DI =
222              PeepholeDoubleRegsMap.find(SrcReg);
223            if (DI != PeepholeDoubleRegsMap.end()) {
224              std::pair<unsigned,unsigned> PeepholeSrc = DI->second;
225              MI->RemoveOperand(1);
226              MI->addOperand(MachineOperand::CreateReg(PeepholeSrc.first,
227                                                       false /*isDef*/,
228                                                       false /*isImp*/,
229                                                       false /*isKill*/,
230                                                       false /*isDead*/,
231                                                       false /*isUndef*/,
232                                                       false /*isEarlyClobber*/,
233                                                       PeepholeSrc.second));
234            }
235          }
236        }
237      }
238
239      // Look for Predicated instructions.
240      if (!DisablePNotP) {
241        bool Done = false;
242        if (QII->isPredicated(MI)) {
243          MachineOperand &Op0 = MI->getOperand(0);
244          unsigned Reg0 = Op0.getReg();
245          const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
246          if (RC0->getID() == Hexagon::PredRegsRegClassID) {
247            // Handle instructions that have a prediate register in op0
248            // (most cases of predicable instructions).
249            if (TargetRegisterInfo::isVirtualRegister(Reg0)) {
250              // Try to find in the map.
251              if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {
252                // Change the 1st operand and, flip the opcode.
253                MI->getOperand(0).setReg(PeepholeSrc);
254                int NewOp = QII->getInvertedPredicatedOpcode(MI->getOpcode());
255                MI->setDesc(QII->get(NewOp));
256                Done = true;
257              }
258            }
259          }
260        }
261
262        if (!Done) {
263          // Handle special instructions.
264          unsigned Op = MI->getOpcode();
265          unsigned NewOp = 0;
266          unsigned PR = 1, S1 = 2, S2 = 3;   // Operand indices.
267
268          switch (Op) {
269            case Hexagon::TFR_condset_rr:
270            case Hexagon::TFR_condset_ii:
271            case Hexagon::MUX_ii:
272            case Hexagon::MUX_rr:
273              NewOp = Op;
274              break;
275            case Hexagon::TFR_condset_ri:
276              NewOp = Hexagon::TFR_condset_ir;
277              break;
278            case Hexagon::TFR_condset_ir:
279              NewOp = Hexagon::TFR_condset_ri;
280              break;
281            case Hexagon::MUX_ri:
282              NewOp = Hexagon::MUX_ir;
283              break;
284            case Hexagon::MUX_ir:
285              NewOp = Hexagon::MUX_ri;
286              break;
287          }
288          if (NewOp) {
289            unsigned PSrc = MI->getOperand(PR).getReg();
290            if (unsigned POrig = PeepholeMap.lookup(PSrc)) {
291              MI->getOperand(PR).setReg(POrig);
292              MI->setDesc(QII->get(NewOp));
293              // Swap operands S1 and S2.
294              MachineOperand Op1 = MI->getOperand(S1);
295              MachineOperand Op2 = MI->getOperand(S2);
296              ChangeOpInto(MI->getOperand(S1), Op2);
297              ChangeOpInto(MI->getOperand(S2), Op1);
298            }
299          } // if (NewOp)
300        } // if (!Done)
301
302      } // if (!DisablePNotP)
303
304    } // Instruction
305  } // Basic Block
306  return true;
307}
308
309void HexagonPeephole::ChangeOpInto(MachineOperand &Dst, MachineOperand &Src) {
310  assert (&Dst != &Src && "Cannot duplicate into itself");
311  switch (Dst.getType()) {
312    case MachineOperand::MO_Register:
313      if (Src.isReg()) {
314        Dst.setReg(Src.getReg());
315      } else if (Src.isImm()) {
316        Dst.ChangeToImmediate(Src.getImm());
317      } else {
318        llvm_unreachable("Unexpected src operand type");
319      }
320      break;
321
322    case MachineOperand::MO_Immediate:
323      if (Src.isImm()) {
324        Dst.setImm(Src.getImm());
325      } else if (Src.isReg()) {
326        Dst.ChangeToRegister(Src.getReg(), Src.isDef(), Src.isImplicit(),
327                             Src.isKill(), Src.isDead(), Src.isUndef(),
328                             Src.isDebug());
329      } else {
330        llvm_unreachable("Unexpected src operand type");
331      }
332      break;
333
334    default:
335      llvm_unreachable("Unexpected dst operand type");
336      break;
337  }
338}
339
340FunctionPass *llvm::createHexagonPeephole() {
341  return new HexagonPeephole();
342}
343