MSP430ISelLowering.cpp revision 37ed9c199ca639565f6ce88105f9e39e898d82d0 
1//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MSP430TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MSP430ISelLowering.h"
15#include "MSP430.h"
16#include "MSP430MachineFunctionInfo.h"
17#include "MSP430Subtarget.h"
18#include "MSP430TargetMachine.h"
19#include "llvm/CodeGen/CallingConvLower.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/SelectionDAGISel.h"
25#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
26#include "llvm/CodeGen/ValueTypes.h"
27#include "llvm/IR/CallingConv.h"
28#include "llvm/IR/DerivedTypes.h"
29#include "llvm/IR/Function.h"
30#include "llvm/IR/GlobalAlias.h"
31#include "llvm/IR/GlobalVariable.h"
32#include "llvm/IR/Intrinsics.h"
33#include "llvm/Support/CommandLine.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/raw_ostream.h"
37using namespace llvm;
38
39#define DEBUG_TYPE "msp430-lower"
40
41typedef enum {
42  NoHWMult,
43  HWMultIntr,
44  HWMultNoIntr
45} HWMultUseMode;
46
47static cl::opt<HWMultUseMode>
48HWMultMode("msp430-hwmult-mode", cl::Hidden,
49           cl::desc("Hardware multiplier use mode"),
50           cl::init(HWMultNoIntr),
51           cl::values(
52             clEnumValN(NoHWMult, "no",
53                "Do not use hardware multiplier"),
54             clEnumValN(HWMultIntr, "interrupts",
55                "Assume hardware multiplier can be used inside interrupts"),
56             clEnumValN(HWMultNoIntr, "use",
57                "Assume hardware multiplier cannot be used inside interrupts"),
58             clEnumValEnd));
59
60MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM)
61    : TargetLowering(TM) {
62
63  // Set up the register classes.
64  addRegisterClass(MVT::i8,  &MSP430::GR8RegClass);
65  addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
66
67  // Compute derived properties from the register classes
68  computeRegisterProperties();
69
70  // Provide all sorts of operation actions
71
72  // Division is expensive
73  setIntDivIsCheap(false);
74
75  setStackPointerRegisterToSaveRestore(MSP430::SP);
76  setBooleanContents(ZeroOrOneBooleanContent);
77  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
78
79  // We have post-incremented loads / stores.
80  setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
81  setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
82
83  setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
84  setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
85  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
86  setLoadExtAction(ISD::SEXTLOAD, MVT::i8,  Expand);
87  setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
88
89  // We don't have any truncstores
90  setTruncStoreAction(MVT::i16, MVT::i8, Expand);
91
92  setOperationAction(ISD::SRA,              MVT::i8,    Custom);
93  setOperationAction(ISD::SHL,              MVT::i8,    Custom);
94  setOperationAction(ISD::SRL,              MVT::i8,    Custom);
95  setOperationAction(ISD::SRA,              MVT::i16,   Custom);
96  setOperationAction(ISD::SHL,              MVT::i16,   Custom);
97  setOperationAction(ISD::SRL,              MVT::i16,   Custom);
98  setOperationAction(ISD::ROTL,             MVT::i8,    Expand);
99  setOperationAction(ISD::ROTR,             MVT::i8,    Expand);
100  setOperationAction(ISD::ROTL,             MVT::i16,   Expand);
101  setOperationAction(ISD::ROTR,             MVT::i16,   Expand);
102  setOperationAction(ISD::GlobalAddress,    MVT::i16,   Custom);
103  setOperationAction(ISD::ExternalSymbol,   MVT::i16,   Custom);
104  setOperationAction(ISD::BlockAddress,     MVT::i16,   Custom);
105  setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
106  setOperationAction(ISD::BR_CC,            MVT::i8,    Custom);
107  setOperationAction(ISD::BR_CC,            MVT::i16,   Custom);
108  setOperationAction(ISD::BRCOND,           MVT::Other, Expand);
109  setOperationAction(ISD::SETCC,            MVT::i8,    Custom);
110  setOperationAction(ISD::SETCC,            MVT::i16,   Custom);
111  setOperationAction(ISD::SELECT,           MVT::i8,    Expand);
112  setOperationAction(ISD::SELECT,           MVT::i16,   Expand);
113  setOperationAction(ISD::SELECT_CC,        MVT::i8,    Custom);
114  setOperationAction(ISD::SELECT_CC,        MVT::i16,   Custom);
115  setOperationAction(ISD::SIGN_EXTEND,      MVT::i16,   Custom);
116  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
117  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
118
119  setOperationAction(ISD::CTTZ,             MVT::i8,    Expand);
120  setOperationAction(ISD::CTTZ,             MVT::i16,   Expand);
121  setOperationAction(ISD::CTTZ_ZERO_UNDEF,  MVT::i8,    Expand);
122  setOperationAction(ISD::CTTZ_ZERO_UNDEF,  MVT::i16,   Expand);
123  setOperationAction(ISD::CTLZ,             MVT::i8,    Expand);
124  setOperationAction(ISD::CTLZ,             MVT::i16,   Expand);
125  setOperationAction(ISD::CTLZ_ZERO_UNDEF,  MVT::i8,    Expand);
126  setOperationAction(ISD::CTLZ_ZERO_UNDEF,  MVT::i16,   Expand);
127  setOperationAction(ISD::CTPOP,            MVT::i8,    Expand);
128  setOperationAction(ISD::CTPOP,            MVT::i16,   Expand);
129
130  setOperationAction(ISD::SHL_PARTS,        MVT::i8,    Expand);
131  setOperationAction(ISD::SHL_PARTS,        MVT::i16,   Expand);
132  setOperationAction(ISD::SRL_PARTS,        MVT::i8,    Expand);
133  setOperationAction(ISD::SRL_PARTS,        MVT::i16,   Expand);
134  setOperationAction(ISD::SRA_PARTS,        MVT::i8,    Expand);
135  setOperationAction(ISD::SRA_PARTS,        MVT::i16,   Expand);
136
137  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,   Expand);
138
139  // FIXME: Implement efficiently multiplication by a constant
140  setOperationAction(ISD::MUL,              MVT::i8,    Expand);
141  setOperationAction(ISD::MULHS,            MVT::i8,    Expand);
142  setOperationAction(ISD::MULHU,            MVT::i8,    Expand);
143  setOperationAction(ISD::SMUL_LOHI,        MVT::i8,    Expand);
144  setOperationAction(ISD::UMUL_LOHI,        MVT::i8,    Expand);
145  setOperationAction(ISD::MUL,              MVT::i16,   Expand);
146  setOperationAction(ISD::MULHS,            MVT::i16,   Expand);
147  setOperationAction(ISD::MULHU,            MVT::i16,   Expand);
148  setOperationAction(ISD::SMUL_LOHI,        MVT::i16,   Expand);
149  setOperationAction(ISD::UMUL_LOHI,        MVT::i16,   Expand);
150
151  setOperationAction(ISD::UDIV,             MVT::i8,    Expand);
152  setOperationAction(ISD::UDIVREM,          MVT::i8,    Expand);
153  setOperationAction(ISD::UREM,             MVT::i8,    Expand);
154  setOperationAction(ISD::SDIV,             MVT::i8,    Expand);
155  setOperationAction(ISD::SDIVREM,          MVT::i8,    Expand);
156  setOperationAction(ISD::SREM,             MVT::i8,    Expand);
157  setOperationAction(ISD::UDIV,             MVT::i16,   Expand);
158  setOperationAction(ISD::UDIVREM,          MVT::i16,   Expand);
159  setOperationAction(ISD::UREM,             MVT::i16,   Expand);
160  setOperationAction(ISD::SDIV,             MVT::i16,   Expand);
161  setOperationAction(ISD::SDIVREM,          MVT::i16,   Expand);
162  setOperationAction(ISD::SREM,             MVT::i16,   Expand);
163
164  // varargs support
165  setOperationAction(ISD::VASTART,          MVT::Other, Custom);
166  setOperationAction(ISD::VAARG,            MVT::Other, Expand);
167  setOperationAction(ISD::VAEND,            MVT::Other, Expand);
168  setOperationAction(ISD::VACOPY,           MVT::Other, Expand);
169  setOperationAction(ISD::JumpTable,        MVT::i16,   Custom);
170
171  // Libcalls names.
172  if (HWMultMode == HWMultIntr) {
173    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw");
174    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw");
175  } else if (HWMultMode == HWMultNoIntr) {
176    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw_noint");
177    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint");
178  }
179
180  setMinFunctionAlignment(1);
181  setPrefFunctionAlignment(2);
182}
183
184SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
185                                             SelectionDAG &DAG) const {
186  switch (Op.getOpcode()) {
187  case ISD::SHL: // FALLTHROUGH
188  case ISD::SRL:
189  case ISD::SRA:              return LowerShifts(Op, DAG);
190  case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
191  case ISD::BlockAddress:     return LowerBlockAddress(Op, DAG);
192  case ISD::ExternalSymbol:   return LowerExternalSymbol(Op, DAG);
193  case ISD::SETCC:            return LowerSETCC(Op, DAG);
194  case ISD::BR_CC:            return LowerBR_CC(Op, DAG);
195  case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
196  case ISD::SIGN_EXTEND:      return LowerSIGN_EXTEND(Op, DAG);
197  case ISD::RETURNADDR:       return LowerRETURNADDR(Op, DAG);
198  case ISD::FRAMEADDR:        return LowerFRAMEADDR(Op, DAG);
199  case ISD::VASTART:          return LowerVASTART(Op, DAG);
200  case ISD::JumpTable:        return LowerJumpTable(Op, DAG);
201  default:
202    llvm_unreachable("unimplemented operand");
203  }
204}
205
206//===----------------------------------------------------------------------===//
207//                       MSP430 Inline Assembly Support
208//===----------------------------------------------------------------------===//
209
210/// getConstraintType - Given a constraint letter, return the type of
211/// constraint it is for this target.
212TargetLowering::ConstraintType
213MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
214  if (Constraint.size() == 1) {
215    switch (Constraint[0]) {
216    case 'r':
217      return C_RegisterClass;
218    default:
219      break;
220    }
221  }
222  return TargetLowering::getConstraintType(Constraint);
223}
224
225std::pair<unsigned, const TargetRegisterClass*>
226MSP430TargetLowering::
227getRegForInlineAsmConstraint(const std::string &Constraint,
228                             MVT VT) const {
229  if (Constraint.size() == 1) {
230    // GCC Constraint Letters
231    switch (Constraint[0]) {
232    default: break;
233    case 'r':   // GENERAL_REGS
234      if (VT == MVT::i8)
235        return std::make_pair(0U, &MSP430::GR8RegClass);
236
237      return std::make_pair(0U, &MSP430::GR16RegClass);
238    }
239  }
240
241  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
242}
243
244//===----------------------------------------------------------------------===//
245//                      Calling Convention Implementation
246//===----------------------------------------------------------------------===//
247
248#include "MSP430GenCallingConv.inc"
249
250/// For each argument in a function store the number of pieces it is composed
251/// of.
252template<typename ArgT>
253static void ParseFunctionArgs(const SmallVectorImpl<ArgT> &Args,
254                              SmallVectorImpl<unsigned> &Out) {
255  unsigned CurrentArgIndex = ~0U;
256  for (unsigned i = 0, e = Args.size(); i != e; i++) {
257    if (CurrentArgIndex == Args[i].OrigArgIndex) {
258      Out.back()++;
259    } else {
260      Out.push_back(1);
261      CurrentArgIndex++;
262    }
263  }
264}
265
266static void AnalyzeVarArgs(CCState &State,
267                           const SmallVectorImpl<ISD::OutputArg> &Outs) {
268  State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack);
269}
270
271static void AnalyzeVarArgs(CCState &State,
272                           const SmallVectorImpl<ISD::InputArg> &Ins) {
273  State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack);
274}
275
276/// Analyze incoming and outgoing function arguments. We need custom C++ code
277/// to handle special constraints in the ABI like reversing the order of the
278/// pieces of splitted arguments. In addition, all pieces of a certain argument
279/// have to be passed either using registers or the stack but never mixing both.
280template<typename ArgT>
281static void AnalyzeArguments(CCState &State,
282                             SmallVectorImpl<CCValAssign> &ArgLocs,
283                             const SmallVectorImpl<ArgT> &Args) {
284  static const MCPhysReg RegList[] = {
285    MSP430::R15, MSP430::R14, MSP430::R13, MSP430::R12
286  };
287  static const unsigned NbRegs = array_lengthof(RegList);
288
289  if (State.isVarArg()) {
290    AnalyzeVarArgs(State, Args);
291    return;
292  }
293
294  SmallVector<unsigned, 4> ArgsParts;
295  ParseFunctionArgs(Args, ArgsParts);
296
297  unsigned RegsLeft = NbRegs;
298  bool UseStack = false;
299  unsigned ValNo = 0;
300
301  for (unsigned i = 0, e = ArgsParts.size(); i != e; i++) {
302    MVT ArgVT = Args[ValNo].VT;
303    ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags;
304    MVT LocVT = ArgVT;
305    CCValAssign::LocInfo LocInfo = CCValAssign::Full;
306
307    // Promote i8 to i16
308    if (LocVT == MVT::i8) {
309      LocVT = MVT::i16;
310      if (ArgFlags.isSExt())
311          LocInfo = CCValAssign::SExt;
312      else if (ArgFlags.isZExt())
313          LocInfo = CCValAssign::ZExt;
314      else
315          LocInfo = CCValAssign::AExt;
316    }
317
318    // Handle byval arguments
319    if (ArgFlags.isByVal()) {
320      State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, 2, ArgFlags);
321      continue;
322    }
323
324    unsigned Parts = ArgsParts[i];
325
326    if (!UseStack && Parts <= RegsLeft) {
327      unsigned FirstVal = ValNo;
328      for (unsigned j = 0; j < Parts; j++) {
329        unsigned Reg = State.AllocateReg(RegList, NbRegs);
330        State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
331        RegsLeft--;
332      }
333
334      // Reverse the order of the pieces to agree with the "big endian" format
335      // required in the calling convention ABI.
336      SmallVectorImpl<CCValAssign>::iterator B = ArgLocs.begin() + FirstVal;
337      std::reverse(B, B + Parts);
338    } else {
339      UseStack = true;
340      for (unsigned j = 0; j < Parts; j++)
341        CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
342    }
343  }
344}
345
346static void AnalyzeRetResult(CCState &State,
347                             const SmallVectorImpl<ISD::InputArg> &Ins) {
348  State.AnalyzeCallResult(Ins, RetCC_MSP430);
349}
350
351static void AnalyzeRetResult(CCState &State,
352                             const SmallVectorImpl<ISD::OutputArg> &Outs) {
353  State.AnalyzeReturn(Outs, RetCC_MSP430);
354}
355
356template<typename ArgT>
357static void AnalyzeReturnValues(CCState &State,
358                                SmallVectorImpl<CCValAssign> &RVLocs,
359                                const SmallVectorImpl<ArgT> &Args) {
360  AnalyzeRetResult(State, Args);
361
362  // Reverse splitted return values to get the "big endian" format required
363  // to agree with the calling convention ABI.
364  std::reverse(RVLocs.begin(), RVLocs.end());
365}
366
367SDValue
368MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
369                                           CallingConv::ID CallConv,
370                                           bool isVarArg,
371                                           const SmallVectorImpl<ISD::InputArg>
372                                             &Ins,
373                                           SDLoc dl,
374                                           SelectionDAG &DAG,
375                                           SmallVectorImpl<SDValue> &InVals)
376                                             const {
377
378  switch (CallConv) {
379  default:
380    llvm_unreachable("Unsupported calling convention");
381  case CallingConv::C:
382  case CallingConv::Fast:
383    return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
384  case CallingConv::MSP430_INTR:
385    if (Ins.empty())
386      return Chain;
387    report_fatal_error("ISRs cannot have arguments");
388  }
389}
390
391SDValue
392MSP430TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
393                                SmallVectorImpl<SDValue> &InVals) const {
394  SelectionDAG &DAG                     = CLI.DAG;
395  SDLoc &dl                             = CLI.DL;
396  SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
397  SmallVectorImpl<SDValue> &OutVals     = CLI.OutVals;
398  SmallVectorImpl<ISD::InputArg> &Ins   = CLI.Ins;
399  SDValue Chain                         = CLI.Chain;
400  SDValue Callee                        = CLI.Callee;
401  bool &isTailCall                      = CLI.IsTailCall;
402  CallingConv::ID CallConv              = CLI.CallConv;
403  bool isVarArg                         = CLI.IsVarArg;
404
405  // MSP430 target does not yet support tail call optimization.
406  isTailCall = false;
407
408  switch (CallConv) {
409  default:
410    llvm_unreachable("Unsupported calling convention");
411  case CallingConv::Fast:
412  case CallingConv::C:
413    return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
414                          Outs, OutVals, Ins, dl, DAG, InVals);
415  case CallingConv::MSP430_INTR:
416    report_fatal_error("ISRs cannot be called directly");
417  }
418}
419
420/// LowerCCCArguments - transform physical registers into virtual registers and
421/// generate load operations for arguments places on the stack.
422// FIXME: struct return stuff
423SDValue
424MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
425                                        CallingConv::ID CallConv,
426                                        bool isVarArg,
427                                        const SmallVectorImpl<ISD::InputArg>
428                                          &Ins,
429                                        SDLoc dl,
430                                        SelectionDAG &DAG,
431                                        SmallVectorImpl<SDValue> &InVals)
432                                          const {
433  MachineFunction &MF = DAG.getMachineFunction();
434  MachineFrameInfo *MFI = MF.getFrameInfo();
435  MachineRegisterInfo &RegInfo = MF.getRegInfo();
436  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
437
438  // Assign locations to all of the incoming arguments.
439  SmallVector<CCValAssign, 16> ArgLocs;
440  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
441                 *DAG.getContext());
442  AnalyzeArguments(CCInfo, ArgLocs, Ins);
443
444  // Create frame index for the start of the first vararg value
445  if (isVarArg) {
446    unsigned Offset = CCInfo.getNextStackOffset();
447    FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, Offset, true));
448  }
449
450  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
451    CCValAssign &VA = ArgLocs[i];
452    if (VA.isRegLoc()) {
453      // Arguments passed in registers
454      EVT RegVT = VA.getLocVT();
455      switch (RegVT.getSimpleVT().SimpleTy) {
456      default:
457        {
458#ifndef NDEBUG
459          errs() << "LowerFormalArguments Unhandled argument type: "
460               << RegVT.getSimpleVT().SimpleTy << "\n";
461#endif
462          llvm_unreachable(nullptr);
463        }
464      case MVT::i16:
465        unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass);
466        RegInfo.addLiveIn(VA.getLocReg(), VReg);
467        SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
468
469        // If this is an 8-bit value, it is really passed promoted to 16
470        // bits. Insert an assert[sz]ext to capture this, then truncate to the
471        // right size.
472        if (VA.getLocInfo() == CCValAssign::SExt)
473          ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
474                                 DAG.getValueType(VA.getValVT()));
475        else if (VA.getLocInfo() == CCValAssign::ZExt)
476          ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
477                                 DAG.getValueType(VA.getValVT()));
478
479        if (VA.getLocInfo() != CCValAssign::Full)
480          ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
481
482        InVals.push_back(ArgValue);
483      }
484    } else {
485      // Sanity check
486      assert(VA.isMemLoc());
487
488      SDValue InVal;
489      ISD::ArgFlagsTy Flags = Ins[i].Flags;
490
491      if (Flags.isByVal()) {
492        int FI = MFI->CreateFixedObject(Flags.getByValSize(),
493                                        VA.getLocMemOffset(), true);
494        InVal = DAG.getFrameIndex(FI, getPointerTy());
495      } else {
496        // Load the argument to a virtual register
497        unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
498        if (ObjSize > 2) {
499            errs() << "LowerFormalArguments Unhandled argument type: "
500                << EVT(VA.getLocVT()).getEVTString()
501                << "\n";
502        }
503        // Create the frame index object for this incoming parameter...
504        int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
505
506        // Create the SelectionDAG nodes corresponding to a load
507        //from this parameter
508        SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
509        InVal = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
510                            MachinePointerInfo::getFixedStack(FI),
511                            false, false, false, 0);
512      }
513
514      InVals.push_back(InVal);
515    }
516  }
517
518  return Chain;
519}
520
521SDValue
522MSP430TargetLowering::LowerReturn(SDValue Chain,
523                                  CallingConv::ID CallConv, bool isVarArg,
524                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
525                                  const SmallVectorImpl<SDValue> &OutVals,
526                                  SDLoc dl, SelectionDAG &DAG) const {
527
528  // CCValAssign - represent the assignment of the return value to a location
529  SmallVector<CCValAssign, 16> RVLocs;
530
531  // ISRs cannot return any value.
532  if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
533    report_fatal_error("ISRs cannot return any value");
534
535  // CCState - Info about the registers and stack slot.
536  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
537                 *DAG.getContext());
538
539  // Analize return values.
540  AnalyzeReturnValues(CCInfo, RVLocs, Outs);
541
542  SDValue Flag;
543  SmallVector<SDValue, 4> RetOps(1, Chain);
544
545  // Copy the result values into the output registers.
546  for (unsigned i = 0; i != RVLocs.size(); ++i) {
547    CCValAssign &VA = RVLocs[i];
548    assert(VA.isRegLoc() && "Can only return in registers!");
549
550    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
551                             OutVals[i], Flag);
552
553    // Guarantee that all emitted copies are stuck together,
554    // avoiding something bad.
555    Flag = Chain.getValue(1);
556    RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
557  }
558
559  unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
560                  MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG);
561
562  RetOps[0] = Chain;  // Update chain.
563
564  // Add the flag if we have it.
565  if (Flag.getNode())
566    RetOps.push_back(Flag);
567
568  return DAG.getNode(Opc, dl, MVT::Other, RetOps);
569}
570
571/// LowerCCCCallTo - functions arguments are copied from virtual regs to
572/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
573// TODO: sret.
574SDValue
575MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
576                                     CallingConv::ID CallConv, bool isVarArg,
577                                     bool isTailCall,
578                                     const SmallVectorImpl<ISD::OutputArg>
579                                       &Outs,
580                                     const SmallVectorImpl<SDValue> &OutVals,
581                                     const SmallVectorImpl<ISD::InputArg> &Ins,
582                                     SDLoc dl, SelectionDAG &DAG,
583                                     SmallVectorImpl<SDValue> &InVals) const {
584  // Analyze operands of the call, assigning locations to each operand.
585  SmallVector<CCValAssign, 16> ArgLocs;
586  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
587                 *DAG.getContext());
588  AnalyzeArguments(CCInfo, ArgLocs, Outs);
589
590  // Get a count of how many bytes are to be pushed on the stack.
591  unsigned NumBytes = CCInfo.getNextStackOffset();
592
593  Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
594                                                      getPointerTy(), true),
595                               dl);
596
597  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
598  SmallVector<SDValue, 12> MemOpChains;
599  SDValue StackPtr;
600
601  // Walk the register/memloc assignments, inserting copies/loads.
602  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
603    CCValAssign &VA = ArgLocs[i];
604
605    SDValue Arg = OutVals[i];
606
607    // Promote the value if needed.
608    switch (VA.getLocInfo()) {
609      default: llvm_unreachable("Unknown loc info!");
610      case CCValAssign::Full: break;
611      case CCValAssign::SExt:
612        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
613        break;
614      case CCValAssign::ZExt:
615        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
616        break;
617      case CCValAssign::AExt:
618        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
619        break;
620    }
621
622    // Arguments that can be passed on register must be kept at RegsToPass
623    // vector
624    if (VA.isRegLoc()) {
625      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
626    } else {
627      assert(VA.isMemLoc());
628
629      if (!StackPtr.getNode())
630        StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SP, getPointerTy());
631
632      SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
633                                   StackPtr,
634                                   DAG.getIntPtrConstant(VA.getLocMemOffset()));
635
636      SDValue MemOp;
637      ISD::ArgFlagsTy Flags = Outs[i].Flags;
638
639      if (Flags.isByVal()) {
640        SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i16);
641        MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode,
642                              Flags.getByValAlign(),
643                              /*isVolatile*/false,
644                              /*AlwaysInline=*/true,
645                              MachinePointerInfo(),
646                              MachinePointerInfo());
647      } else {
648        MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo(),
649                             false, false, 0);
650      }
651
652      MemOpChains.push_back(MemOp);
653    }
654  }
655
656  // Transform all store nodes into one single node because all store nodes are
657  // independent of each other.
658  if (!MemOpChains.empty())
659    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
660
661  // Build a sequence of copy-to-reg nodes chained together with token chain and
662  // flag operands which copy the outgoing args into registers.  The InFlag in
663  // necessary since all emitted instructions must be stuck together.
664  SDValue InFlag;
665  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
666    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
667                             RegsToPass[i].second, InFlag);
668    InFlag = Chain.getValue(1);
669  }
670
671  // If the callee is a GlobalAddress node (quite common, every direct call is)
672  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
673  // Likewise ExternalSymbol -> TargetExternalSymbol.
674  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
675    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16);
676  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
677    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
678
679  // Returns a chain & a flag for retval copy to use.
680  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
681  SmallVector<SDValue, 8> Ops;
682  Ops.push_back(Chain);
683  Ops.push_back(Callee);
684
685  // Add argument registers to the end of the list so that they are
686  // known live into the call.
687  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
688    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
689                                  RegsToPass[i].second.getValueType()));
690
691  if (InFlag.getNode())
692    Ops.push_back(InFlag);
693
694  Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, Ops);
695  InFlag = Chain.getValue(1);
696
697  // Create the CALLSEQ_END node.
698  Chain = DAG.getCALLSEQ_END(Chain,
699                             DAG.getConstant(NumBytes, getPointerTy(), true),
700                             DAG.getConstant(0, getPointerTy(), true),
701                             InFlag, dl);
702  InFlag = Chain.getValue(1);
703
704  // Handle result values, copying them out of physregs into vregs that we
705  // return.
706  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
707                         DAG, InVals);
708}
709
710/// LowerCallResult - Lower the result values of a call into the
711/// appropriate copies out of appropriate physical registers.
712///
713SDValue
714MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
715                                      CallingConv::ID CallConv, bool isVarArg,
716                                      const SmallVectorImpl<ISD::InputArg> &Ins,
717                                      SDLoc dl, SelectionDAG &DAG,
718                                      SmallVectorImpl<SDValue> &InVals) const {
719
720  // Assign locations to each value returned by this call.
721  SmallVector<CCValAssign, 16> RVLocs;
722  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
723                 *DAG.getContext());
724
725  AnalyzeReturnValues(CCInfo, RVLocs, Ins);
726
727  // Copy all of the result registers out of their specified physreg.
728  for (unsigned i = 0; i != RVLocs.size(); ++i) {
729    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
730                               RVLocs[i].getValVT(), InFlag).getValue(1);
731    InFlag = Chain.getValue(2);
732    InVals.push_back(Chain.getValue(0));
733  }
734
735  return Chain;
736}
737
738SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
739                                          SelectionDAG &DAG) const {
740  unsigned Opc = Op.getOpcode();
741  SDNode* N = Op.getNode();
742  EVT VT = Op.getValueType();
743  SDLoc dl(N);
744
745  // Expand non-constant shifts to loops:
746  if (!isa<ConstantSDNode>(N->getOperand(1)))
747    switch (Opc) {
748    default: llvm_unreachable("Invalid shift opcode!");
749    case ISD::SHL:
750      return DAG.getNode(MSP430ISD::SHL, dl,
751                         VT, N->getOperand(0), N->getOperand(1));
752    case ISD::SRA:
753      return DAG.getNode(MSP430ISD::SRA, dl,
754                         VT, N->getOperand(0), N->getOperand(1));
755    case ISD::SRL:
756      return DAG.getNode(MSP430ISD::SRL, dl,
757                         VT, N->getOperand(0), N->getOperand(1));
758    }
759
760  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
761
762  // Expand the stuff into sequence of shifts.
763  // FIXME: for some shift amounts this might be done better!
764  // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
765  SDValue Victim = N->getOperand(0);
766
767  if (Opc == ISD::SRL && ShiftAmount) {
768    // Emit a special goodness here:
769    // srl A, 1 => clrc; rrc A
770    Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
771    ShiftAmount -= 1;
772  }
773
774  while (ShiftAmount--)
775    Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
776                         dl, VT, Victim);
777
778  return Victim;
779}
780
781SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op,
782                                                 SelectionDAG &DAG) const {
783  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
784  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
785
786  // Create the TargetGlobalAddress node, folding in the constant offset.
787  SDValue Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
788                                              getPointerTy(), Offset);
789  return DAG.getNode(MSP430ISD::Wrapper, SDLoc(Op),
790                     getPointerTy(), Result);
791}
792
793SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
794                                                  SelectionDAG &DAG) const {
795  SDLoc dl(Op);
796  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
797  SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
798
799  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);
800}
801
802SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op,
803                                                SelectionDAG &DAG) const {
804  SDLoc dl(Op);
805  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
806  SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy());
807
808  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);
809}
810
811static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
812                       ISD::CondCode CC,
813                       SDLoc dl, SelectionDAG &DAG) {
814  // FIXME: Handle bittests someday
815  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
816
817  // FIXME: Handle jump negative someday
818  MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
819  switch (CC) {
820  default: llvm_unreachable("Invalid integer condition!");
821  case ISD::SETEQ:
822    TCC = MSP430CC::COND_E;     // aka COND_Z
823    // Minor optimization: if LHS is a constant, swap operands, then the
824    // constant can be folded into comparison.
825    if (LHS.getOpcode() == ISD::Constant)
826      std::swap(LHS, RHS);
827    break;
828  case ISD::SETNE:
829    TCC = MSP430CC::COND_NE;    // aka COND_NZ
830    // Minor optimization: if LHS is a constant, swap operands, then the
831    // constant can be folded into comparison.
832    if (LHS.getOpcode() == ISD::Constant)
833      std::swap(LHS, RHS);
834    break;
835  case ISD::SETULE:
836    std::swap(LHS, RHS);        // FALLTHROUGH
837  case ISD::SETUGE:
838    // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
839    // fold constant into instruction.
840    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
841      LHS = RHS;
842      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
843      TCC = MSP430CC::COND_LO;
844      break;
845    }
846    TCC = MSP430CC::COND_HS;    // aka COND_C
847    break;
848  case ISD::SETUGT:
849    std::swap(LHS, RHS);        // FALLTHROUGH
850  case ISD::SETULT:
851    // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
852    // fold constant into instruction.
853    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
854      LHS = RHS;
855      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
856      TCC = MSP430CC::COND_HS;
857      break;
858    }
859    TCC = MSP430CC::COND_LO;    // aka COND_NC
860    break;
861  case ISD::SETLE:
862    std::swap(LHS, RHS);        // FALLTHROUGH
863  case ISD::SETGE:
864    // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
865    // fold constant into instruction.
866    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
867      LHS = RHS;
868      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
869      TCC = MSP430CC::COND_L;
870      break;
871    }
872    TCC = MSP430CC::COND_GE;
873    break;
874  case ISD::SETGT:
875    std::swap(LHS, RHS);        // FALLTHROUGH
876  case ISD::SETLT:
877    // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
878    // fold constant into instruction.
879    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
880      LHS = RHS;
881      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
882      TCC = MSP430CC::COND_GE;
883      break;
884    }
885    TCC = MSP430CC::COND_L;
886    break;
887  }
888
889  TargetCC = DAG.getConstant(TCC, MVT::i8);
890  return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS);
891}
892
893
894SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
895  SDValue Chain = Op.getOperand(0);
896  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
897  SDValue LHS   = Op.getOperand(2);
898  SDValue RHS   = Op.getOperand(3);
899  SDValue Dest  = Op.getOperand(4);
900  SDLoc dl  (Op);
901
902  SDValue TargetCC;
903  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
904
905  return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
906                     Chain, Dest, TargetCC, Flag);
907}
908
909SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
910  SDValue LHS   = Op.getOperand(0);
911  SDValue RHS   = Op.getOperand(1);
912  SDLoc dl  (Op);
913
914  // If we are doing an AND and testing against zero, then the CMP
915  // will not be generated.  The AND (or BIT) will generate the condition codes,
916  // but they are different from CMP.
917  // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
918  // lowering & isel wouldn't diverge.
919  bool andCC = false;
920  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
921    if (RHSC->isNullValue() && LHS.hasOneUse() &&
922        (LHS.getOpcode() == ISD::AND ||
923         (LHS.getOpcode() == ISD::TRUNCATE &&
924          LHS.getOperand(0).getOpcode() == ISD::AND))) {
925      andCC = true;
926    }
927  }
928  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
929  SDValue TargetCC;
930  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
931
932  // Get the condition codes directly from the status register, if its easy.
933  // Otherwise a branch will be generated.  Note that the AND and BIT
934  // instructions generate different flags than CMP, the carry bit can be used
935  // for NE/EQ.
936  bool Invert = false;
937  bool Shift = false;
938  bool Convert = true;
939  switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
940   default:
941    Convert = false;
942    break;
943   case MSP430CC::COND_HS:
944     // Res = SR & 1, no processing is required
945     break;
946   case MSP430CC::COND_LO:
947     // Res = ~(SR & 1)
948     Invert = true;
949     break;
950   case MSP430CC::COND_NE:
951     if (andCC) {
952       // C = ~Z, thus Res = SR & 1, no processing is required
953     } else {
954       // Res = ~((SR >> 1) & 1)
955       Shift = true;
956       Invert = true;
957     }
958     break;
959   case MSP430CC::COND_E:
960     Shift = true;
961     // C = ~Z for AND instruction, thus we can put Res = ~(SR & 1), however,
962     // Res = (SR >> 1) & 1 is 1 word shorter.
963     break;
964  }
965  EVT VT = Op.getValueType();
966  SDValue One  = DAG.getConstant(1, VT);
967  if (Convert) {
968    SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SR,
969                                    MVT::i16, Flag);
970    if (Shift)
971      // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
972      SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
973    SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
974    if (Invert)
975      SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
976    return SR;
977  } else {
978    SDValue Zero = DAG.getConstant(0, VT);
979    SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
980    SmallVector<SDValue, 4> Ops;
981    Ops.push_back(One);
982    Ops.push_back(Zero);
983    Ops.push_back(TargetCC);
984    Ops.push_back(Flag);
985    return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
986  }
987}
988
989SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op,
990                                             SelectionDAG &DAG) const {
991  SDValue LHS    = Op.getOperand(0);
992  SDValue RHS    = Op.getOperand(1);
993  SDValue TrueV  = Op.getOperand(2);
994  SDValue FalseV = Op.getOperand(3);
995  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
996  SDLoc dl   (Op);
997
998  SDValue TargetCC;
999  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
1000
1001  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1002  SmallVector<SDValue, 4> Ops;
1003  Ops.push_back(TrueV);
1004  Ops.push_back(FalseV);
1005  Ops.push_back(TargetCC);
1006  Ops.push_back(Flag);
1007
1008  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
1009}
1010
1011SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
1012                                               SelectionDAG &DAG) const {
1013  SDValue Val = Op.getOperand(0);
1014  EVT VT      = Op.getValueType();
1015  SDLoc dl(Op);
1016
1017  assert(VT == MVT::i16 && "Only support i16 for now!");
1018
1019  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
1020                     DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
1021                     DAG.getValueType(Val.getValueType()));
1022}
1023
1024SDValue
1025MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
1026  MachineFunction &MF = DAG.getMachineFunction();
1027  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
1028  int ReturnAddrIndex = FuncInfo->getRAIndex();
1029
1030  if (ReturnAddrIndex == 0) {
1031    // Set up a frame object for the return address.
1032    uint64_t SlotSize = getDataLayout()->getPointerSize();
1033    ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
1034                                                           true);
1035    FuncInfo->setRAIndex(ReturnAddrIndex);
1036  }
1037
1038  return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1039}
1040
1041SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op,
1042                                              SelectionDAG &DAG) const {
1043  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1044  MFI->setReturnAddressIsTaken(true);
1045
1046  if (verifyReturnAddressArgumentIsConstant(Op, DAG))
1047    return SDValue();
1048
1049  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1050  SDLoc dl(Op);
1051
1052  if (Depth > 0) {
1053    SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1054    SDValue Offset =
1055        DAG.getConstant(getDataLayout()->getPointerSize(), MVT::i16);
1056    return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
1057                       DAG.getNode(ISD::ADD, dl, getPointerTy(),
1058                                   FrameAddr, Offset),
1059                       MachinePointerInfo(), false, false, false, 0);
1060  }
1061
1062  // Just load the return address.
1063  SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
1064  return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
1065                     RetAddrFI, MachinePointerInfo(), false, false, false, 0);
1066}
1067
1068SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op,
1069                                             SelectionDAG &DAG) const {
1070  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1071  MFI->setFrameAddressIsTaken(true);
1072
1073  EVT VT = Op.getValueType();
1074  SDLoc dl(Op);  // FIXME probably not meaningful
1075  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1076  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1077                                         MSP430::FP, VT);
1078  while (Depth--)
1079    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1080                            MachinePointerInfo(),
1081                            false, false, false, 0);
1082  return FrameAddr;
1083}
1084
1085SDValue MSP430TargetLowering::LowerVASTART(SDValue Op,
1086                                           SelectionDAG &DAG) const {
1087  MachineFunction &MF = DAG.getMachineFunction();
1088  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
1089
1090  // Frame index of first vararg argument
1091  SDValue FrameIndex = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1092                                         getPointerTy());
1093  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1094
1095  // Create a store of the frame index to the location operand
1096  return DAG.getStore(Op.getOperand(0), SDLoc(Op), FrameIndex,
1097                      Op.getOperand(1), MachinePointerInfo(SV),
1098                      false, false, 0);
1099}
1100
1101SDValue MSP430TargetLowering::LowerJumpTable(SDValue Op,
1102                                             SelectionDAG &DAG) const {
1103    JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1104    SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
1105    return DAG.getNode(MSP430ISD::Wrapper, SDLoc(JT),
1106                       getPointerTy(), Result);
1107}
1108
1109/// getPostIndexedAddressParts - returns true by value, base pointer and
1110/// offset pointer and addressing mode by reference if this node can be
1111/// combined with a load / store to form a post-indexed load / store.
1112bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1113                                                      SDValue &Base,
1114                                                      SDValue &Offset,
1115                                                      ISD::MemIndexedMode &AM,
1116                                                      SelectionDAG &DAG) const {
1117
1118  LoadSDNode *LD = cast<LoadSDNode>(N);
1119  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1120    return false;
1121
1122  EVT VT = LD->getMemoryVT();
1123  if (VT != MVT::i8 && VT != MVT::i16)
1124    return false;
1125
1126  if (Op->getOpcode() != ISD::ADD)
1127    return false;
1128
1129  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
1130    uint64_t RHSC = RHS->getZExtValue();
1131    if ((VT == MVT::i16 && RHSC != 2) ||
1132        (VT == MVT::i8 && RHSC != 1))
1133      return false;
1134
1135    Base = Op->getOperand(0);
1136    Offset = DAG.getConstant(RHSC, VT);
1137    AM = ISD::POST_INC;
1138    return true;
1139  }
1140
1141  return false;
1142}
1143
1144
1145const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
1146  switch (Opcode) {
1147  default: return nullptr;
1148  case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
1149  case MSP430ISD::RETI_FLAG:          return "MSP430ISD::RETI_FLAG";
1150  case MSP430ISD::RRA:                return "MSP430ISD::RRA";
1151  case MSP430ISD::RLA:                return "MSP430ISD::RLA";
1152  case MSP430ISD::RRC:                return "MSP430ISD::RRC";
1153  case MSP430ISD::CALL:               return "MSP430ISD::CALL";
1154  case MSP430ISD::Wrapper:            return "MSP430ISD::Wrapper";
1155  case MSP430ISD::BR_CC:              return "MSP430ISD::BR_CC";
1156  case MSP430ISD::CMP:                return "MSP430ISD::CMP";
1157  case MSP430ISD::SELECT_CC:          return "MSP430ISD::SELECT_CC";
1158  case MSP430ISD::SHL:                return "MSP430ISD::SHL";
1159  case MSP430ISD::SRA:                return "MSP430ISD::SRA";
1160  }
1161}
1162
1163bool MSP430TargetLowering::isTruncateFree(Type *Ty1,
1164                                          Type *Ty2) const {
1165  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
1166    return false;
1167
1168  return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
1169}
1170
1171bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1172  if (!VT1.isInteger() || !VT2.isInteger())
1173    return false;
1174
1175  return (VT1.getSizeInBits() > VT2.getSizeInBits());
1176}
1177
1178bool MSP430TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
1179  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1180  return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
1181}
1182
1183bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
1184  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1185  return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
1186}
1187
1188bool MSP430TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
1189  return isZExtFree(Val.getValueType(), VT2);
1190}
1191
1192//===----------------------------------------------------------------------===//
1193//  Other Lowering Code
1194//===----------------------------------------------------------------------===//
1195
1196MachineBasicBlock*
1197MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,
1198                                     MachineBasicBlock *BB) const {
1199  MachineFunction *F = BB->getParent();
1200  MachineRegisterInfo &RI = F->getRegInfo();
1201  DebugLoc dl = MI->getDebugLoc();
1202  const TargetInstrInfo &TII =
1203      *getTargetMachine().getSubtargetImpl()->getInstrInfo();
1204
1205  unsigned Opc;
1206  const TargetRegisterClass * RC;
1207  switch (MI->getOpcode()) {
1208  default: llvm_unreachable("Invalid shift opcode!");
1209  case MSP430::Shl8:
1210   Opc = MSP430::SHL8r1;
1211   RC = &MSP430::GR8RegClass;
1212   break;
1213  case MSP430::Shl16:
1214   Opc = MSP430::SHL16r1;
1215   RC = &MSP430::GR16RegClass;
1216   break;
1217  case MSP430::Sra8:
1218   Opc = MSP430::SAR8r1;
1219   RC = &MSP430::GR8RegClass;
1220   break;
1221  case MSP430::Sra16:
1222   Opc = MSP430::SAR16r1;
1223   RC = &MSP430::GR16RegClass;
1224   break;
1225  case MSP430::Srl8:
1226   Opc = MSP430::SAR8r1c;
1227   RC = &MSP430::GR8RegClass;
1228   break;
1229  case MSP430::Srl16:
1230   Opc = MSP430::SAR16r1c;
1231   RC = &MSP430::GR16RegClass;
1232   break;
1233  }
1234
1235  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1236  MachineFunction::iterator I = BB;
1237  ++I;
1238
1239  // Create loop block
1240  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1241  MachineBasicBlock *RemBB  = F->CreateMachineBasicBlock(LLVM_BB);
1242
1243  F->insert(I, LoopBB);
1244  F->insert(I, RemBB);
1245
1246  // Update machine-CFG edges by transferring all successors of the current
1247  // block to the block containing instructions after shift.
1248  RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1249                BB->end());
1250  RemBB->transferSuccessorsAndUpdatePHIs(BB);
1251
1252  // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1253  BB->addSuccessor(LoopBB);
1254  BB->addSuccessor(RemBB);
1255  LoopBB->addSuccessor(RemBB);
1256  LoopBB->addSuccessor(LoopBB);
1257
1258  unsigned ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass);
1259  unsigned ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass);
1260  unsigned ShiftReg = RI.createVirtualRegister(RC);
1261  unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1262  unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg();
1263  unsigned SrcReg = MI->getOperand(1).getReg();
1264  unsigned DstReg = MI->getOperand(0).getReg();
1265
1266  // BB:
1267  // cmp 0, N
1268  // je RemBB
1269  BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1270    .addReg(ShiftAmtSrcReg).addImm(0);
1271  BuildMI(BB, dl, TII.get(MSP430::JCC))
1272    .addMBB(RemBB)
1273    .addImm(MSP430CC::COND_E);
1274
1275  // LoopBB:
1276  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1277  // ShiftAmt = phi [%N, BB],      [%ShiftAmt2, LoopBB]
1278  // ShiftReg2 = shift ShiftReg
1279  // ShiftAmt2 = ShiftAmt - 1;
1280  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1281    .addReg(SrcReg).addMBB(BB)
1282    .addReg(ShiftReg2).addMBB(LoopBB);
1283  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1284    .addReg(ShiftAmtSrcReg).addMBB(BB)
1285    .addReg(ShiftAmtReg2).addMBB(LoopBB);
1286  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1287    .addReg(ShiftReg);
1288  BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1289    .addReg(ShiftAmtReg).addImm(1);
1290  BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1291    .addMBB(LoopBB)
1292    .addImm(MSP430CC::COND_NE);
1293
1294  // RemBB:
1295  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1296  BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1297    .addReg(SrcReg).addMBB(BB)
1298    .addReg(ShiftReg2).addMBB(LoopBB);
1299
1300  MI->eraseFromParent();   // The pseudo instruction is gone now.
1301  return RemBB;
1302}
1303
1304MachineBasicBlock*
1305MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1306                                                  MachineBasicBlock *BB) const {
1307  unsigned Opc = MI->getOpcode();
1308
1309  if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1310      Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1311      Opc == MSP430::Srl8 || Opc == MSP430::Srl16)
1312    return EmitShiftInstr(MI, BB);
1313
1314  const TargetInstrInfo &TII =
1315      *getTargetMachine().getSubtargetImpl()->getInstrInfo();
1316  DebugLoc dl = MI->getDebugLoc();
1317
1318  assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1319         "Unexpected instr type to insert");
1320
1321  // To "insert" a SELECT instruction, we actually have to insert the diamond
1322  // control-flow pattern.  The incoming instruction knows the destination vreg
1323  // to set, the condition code register to branch on, the true/false values to
1324  // select between, and a branch opcode to use.
1325  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1326  MachineFunction::iterator I = BB;
1327  ++I;
1328
1329  //  thisMBB:
1330  //  ...
1331  //   TrueVal = ...
1332  //   cmpTY ccX, r1, r2
1333  //   jCC copy1MBB
1334  //   fallthrough --> copy0MBB
1335  MachineBasicBlock *thisMBB = BB;
1336  MachineFunction *F = BB->getParent();
1337  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1338  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1339  F->insert(I, copy0MBB);
1340  F->insert(I, copy1MBB);
1341  // Update machine-CFG edges by transferring all successors of the current
1342  // block to the new block which will contain the Phi node for the select.
1343  copy1MBB->splice(copy1MBB->begin(), BB,
1344                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
1345  copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
1346  // Next, add the true and fallthrough blocks as its successors.
1347  BB->addSuccessor(copy0MBB);
1348  BB->addSuccessor(copy1MBB);
1349
1350  BuildMI(BB, dl, TII.get(MSP430::JCC))
1351    .addMBB(copy1MBB)
1352    .addImm(MI->getOperand(3).getImm());
1353
1354  //  copy0MBB:
1355  //   %FalseValue = ...
1356  //   # fallthrough to copy1MBB
1357  BB = copy0MBB;
1358
1359  // Update machine-CFG edges
1360  BB->addSuccessor(copy1MBB);
1361
1362  //  copy1MBB:
1363  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1364  //  ...
1365  BB = copy1MBB;
1366  BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI),
1367          MI->getOperand(0).getReg())
1368    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1369    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1370
1371  MI->eraseFromParent();   // The pseudo instruction is gone now.
1372  return BB;
1373}
1374