MSP430ISelLowering.cpp revision 65c3c8f323198b99b88b109654194540cf9b3fa5 
1//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MSP430TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "msp430-lower"
15
16#include "MSP430ISelLowering.h"
17#include "MSP430.h"
18#include "MSP430TargetMachine.h"
19#include "MSP430Subtarget.h"
20#include "llvm/DerivedTypes.h"
21#include "llvm/Function.h"
22#include "llvm/Intrinsics.h"
23#include "llvm/CallingConv.h"
24#include "llvm/GlobalVariable.h"
25#include "llvm/GlobalAlias.h"
26#include "llvm/CodeGen/CallingConvLower.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/PseudoSourceValue.h"
32#include "llvm/CodeGen/SelectionDAGISel.h"
33#include "llvm/CodeGen/ValueTypes.h"
34#include "llvm/Target/TargetLoweringObjectFile.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38#include "llvm/ADT/VectorExtras.h"
39using namespace llvm;
40
41MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
42  TargetLowering(tm, new TargetLoweringObjectFileELF()),
43  Subtarget(*tm.getSubtargetImpl()), TM(tm) {
44
45  // Set up the register classes.
46  addRegisterClass(MVT::i8,  MSP430::GR8RegisterClass);
47  addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
48
49  // Compute derived properties from the register classes
50  computeRegisterProperties();
51
52  // Provide all sorts of operation actions
53
54  // Division is expensive
55  setIntDivIsCheap(false);
56
57  // Even if we have only 1 bit shift here, we can perform
58  // shifts of the whole bitwidth 1 bit per step.
59  setShiftAmountType(MVT::i8);
60
61  setStackPointerRegisterToSaveRestore(MSP430::SPW);
62  setBooleanContents(ZeroOrOneBooleanContent);
63  setSchedulingPreference(SchedulingForLatency);
64
65  setLoadExtAction(ISD::EXTLOAD,  MVT::i1, Promote);
66  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
67  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
68  setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
69  setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
70
71  // We don't have any truncstores
72  setTruncStoreAction(MVT::i16, MVT::i8, Expand);
73
74  setOperationAction(ISD::SRA,              MVT::i8,    Custom);
75  setOperationAction(ISD::SHL,              MVT::i8,    Custom);
76  setOperationAction(ISD::SRL,              MVT::i8,    Custom);
77  setOperationAction(ISD::SRA,              MVT::i16,   Custom);
78  setOperationAction(ISD::SHL,              MVT::i16,   Custom);
79  setOperationAction(ISD::SRL,              MVT::i16,   Custom);
80  setOperationAction(ISD::ROTL,             MVT::i8,    Expand);
81  setOperationAction(ISD::ROTR,             MVT::i8,    Expand);
82  setOperationAction(ISD::ROTL,             MVT::i16,   Expand);
83  setOperationAction(ISD::ROTR,             MVT::i16,   Expand);
84  setOperationAction(ISD::GlobalAddress,    MVT::i16,   Custom);
85  setOperationAction(ISD::ExternalSymbol,   MVT::i16,   Custom);
86  setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
87  setOperationAction(ISD::BRIND,            MVT::Other, Expand);
88  setOperationAction(ISD::BR_CC,            MVT::i8,    Custom);
89  setOperationAction(ISD::BR_CC,            MVT::i16,   Custom);
90  setOperationAction(ISD::BRCOND,           MVT::Other, Expand);
91  setOperationAction(ISD::SETCC,            MVT::i8,    Expand);
92  setOperationAction(ISD::SETCC,            MVT::i16,   Expand);
93  setOperationAction(ISD::SELECT,           MVT::i8,    Expand);
94  setOperationAction(ISD::SELECT,           MVT::i16,   Expand);
95  setOperationAction(ISD::SELECT_CC,        MVT::i8,    Custom);
96  setOperationAction(ISD::SELECT_CC,        MVT::i16,   Custom);
97  setOperationAction(ISD::SIGN_EXTEND,      MVT::i16,   Custom);
98  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
99  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
100
101  setOperationAction(ISD::CTTZ,             MVT::i8,    Expand);
102  setOperationAction(ISD::CTTZ,             MVT::i16,   Expand);
103  setOperationAction(ISD::CTLZ,             MVT::i8,    Expand);
104  setOperationAction(ISD::CTLZ,             MVT::i16,   Expand);
105  setOperationAction(ISD::CTPOP,            MVT::i8,    Expand);
106  setOperationAction(ISD::CTPOP,            MVT::i16,   Expand);
107
108  setOperationAction(ISD::SHL_PARTS,        MVT::i8,    Expand);
109  setOperationAction(ISD::SHL_PARTS,        MVT::i16,   Expand);
110  setOperationAction(ISD::SRL_PARTS,        MVT::i8,    Expand);
111  setOperationAction(ISD::SRL_PARTS,        MVT::i16,   Expand);
112  setOperationAction(ISD::SRA_PARTS,        MVT::i8,    Expand);
113  setOperationAction(ISD::SRA_PARTS,        MVT::i16,   Expand);
114
115  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,   Expand);
116
117  // FIXME: Implement efficiently multiplication by a constant
118  setOperationAction(ISD::MUL,              MVT::i16,   Expand);
119  setOperationAction(ISD::MULHS,            MVT::i16,   Expand);
120  setOperationAction(ISD::MULHU,            MVT::i16,   Expand);
121  setOperationAction(ISD::SMUL_LOHI,        MVT::i16,   Expand);
122  setOperationAction(ISD::UMUL_LOHI,        MVT::i16,   Expand);
123
124  setOperationAction(ISD::UDIV,             MVT::i16,   Expand);
125  setOperationAction(ISD::UDIVREM,          MVT::i16,   Expand);
126  setOperationAction(ISD::UREM,             MVT::i16,   Expand);
127  setOperationAction(ISD::SDIV,             MVT::i16,   Expand);
128  setOperationAction(ISD::SDIVREM,          MVT::i16,   Expand);
129  setOperationAction(ISD::SREM,             MVT::i16,   Expand);
130}
131
132SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
133  switch (Op.getOpcode()) {
134  case ISD::SHL: // FALLTHROUGH
135  case ISD::SRL:
136  case ISD::SRA:              return LowerShifts(Op, DAG);
137  case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
138  case ISD::ExternalSymbol:   return LowerExternalSymbol(Op, DAG);
139  case ISD::BR_CC:            return LowerBR_CC(Op, DAG);
140  case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
141  case ISD::SIGN_EXTEND:      return LowerSIGN_EXTEND(Op, DAG);
142  default:
143    llvm_unreachable("unimplemented operand");
144    return SDValue();
145  }
146}
147
148/// getFunctionAlignment - Return the Log2 alignment of this function.
149unsigned MSP430TargetLowering::getFunctionAlignment(const Function *F) const {
150  return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 4;
151}
152
153//===----------------------------------------------------------------------===//
154//                       MSP430 Inline Assembly Support
155//===----------------------------------------------------------------------===//
156
157/// getConstraintType - Given a constraint letter, return the type of
158/// constraint it is for this target.
159TargetLowering::ConstraintType
160MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
161  if (Constraint.size() == 1) {
162    switch (Constraint[0]) {
163    case 'r':
164      return C_RegisterClass;
165    default:
166      break;
167    }
168  }
169  return TargetLowering::getConstraintType(Constraint);
170}
171
172std::pair<unsigned, const TargetRegisterClass*>
173MSP430TargetLowering::
174getRegForInlineAsmConstraint(const std::string &Constraint,
175                             EVT VT) const {
176  if (Constraint.size() == 1) {
177    // GCC Constraint Letters
178    switch (Constraint[0]) {
179    default: break;
180    case 'r':   // GENERAL_REGS
181      if (VT == MVT::i8)
182        return std::make_pair(0U, MSP430::GR8RegisterClass);
183
184      return std::make_pair(0U, MSP430::GR16RegisterClass);
185    }
186  }
187
188  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
189}
190
191//===----------------------------------------------------------------------===//
192//                      Calling Convention Implementation
193//===----------------------------------------------------------------------===//
194
195#include "MSP430GenCallingConv.inc"
196
197SDValue
198MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
199                                           CallingConv::ID CallConv,
200                                           bool isVarArg,
201                                           const SmallVectorImpl<ISD::InputArg>
202                                             &Ins,
203                                           DebugLoc dl,
204                                           SelectionDAG &DAG,
205                                           SmallVectorImpl<SDValue> &InVals) {
206
207  switch (CallConv) {
208  default:
209    llvm_unreachable("Unsupported calling convention");
210  case CallingConv::C:
211  case CallingConv::Fast:
212    return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
213  }
214}
215
216SDValue
217MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
218                                CallingConv::ID CallConv, bool isVarArg,
219                                bool isTailCall,
220                                const SmallVectorImpl<ISD::OutputArg> &Outs,
221                                const SmallVectorImpl<ISD::InputArg> &Ins,
222                                DebugLoc dl, SelectionDAG &DAG,
223                                SmallVectorImpl<SDValue> &InVals) {
224
225  switch (CallConv) {
226  default:
227    llvm_unreachable("Unsupported calling convention");
228  case CallingConv::Fast:
229  case CallingConv::C:
230    return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
231                          Outs, Ins, dl, DAG, InVals);
232  }
233}
234
235/// LowerCCCArguments - transform physical registers into virtual registers and
236/// generate load operations for arguments places on the stack.
237// FIXME: struct return stuff
238// FIXME: varargs
239SDValue
240MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
241                                        CallingConv::ID CallConv,
242                                        bool isVarArg,
243                                        const SmallVectorImpl<ISD::InputArg>
244                                          &Ins,
245                                        DebugLoc dl,
246                                        SelectionDAG &DAG,
247                                        SmallVectorImpl<SDValue> &InVals) {
248  MachineFunction &MF = DAG.getMachineFunction();
249  MachineFrameInfo *MFI = MF.getFrameInfo();
250  MachineRegisterInfo &RegInfo = MF.getRegInfo();
251
252  // Assign locations to all of the incoming arguments.
253  SmallVector<CCValAssign, 16> ArgLocs;
254  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
255                 ArgLocs, *DAG.getContext());
256  CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
257
258  assert(!isVarArg && "Varargs not supported yet");
259
260  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
261    CCValAssign &VA = ArgLocs[i];
262    if (VA.isRegLoc()) {
263      // Arguments passed in registers
264      EVT RegVT = VA.getLocVT();
265      switch (RegVT.getSimpleVT().SimpleTy) {
266      default:
267        {
268#ifndef NDEBUG
269          errs() << "LowerFormalArguments Unhandled argument type: "
270               << RegVT.getSimpleVT().SimpleTy << "\n";
271#endif
272          llvm_unreachable(0);
273        }
274      case MVT::i16:
275        unsigned VReg =
276          RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
277        RegInfo.addLiveIn(VA.getLocReg(), VReg);
278        SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
279
280        // If this is an 8-bit value, it is really passed promoted to 16
281        // bits. Insert an assert[sz]ext to capture this, then truncate to the
282        // right size.
283        if (VA.getLocInfo() == CCValAssign::SExt)
284          ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
285                                 DAG.getValueType(VA.getValVT()));
286        else if (VA.getLocInfo() == CCValAssign::ZExt)
287          ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
288                                 DAG.getValueType(VA.getValVT()));
289
290        if (VA.getLocInfo() != CCValAssign::Full)
291          ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
292
293        InVals.push_back(ArgValue);
294      }
295    } else {
296      // Sanity check
297      assert(VA.isMemLoc());
298      // Load the argument to a virtual register
299      unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
300      if (ObjSize > 2) {
301        errs() << "LowerFormalArguments Unhandled argument type: "
302             << VA.getLocVT().getSimpleVT().SimpleTy
303             << "\n";
304      }
305      // Create the frame index object for this incoming parameter...
306      int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset());
307
308      // Create the SelectionDAG nodes corresponding to a load
309      //from this parameter
310      SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
311      InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
312                                   PseudoSourceValue::getFixedStack(FI), 0));
313    }
314  }
315
316  return Chain;
317}
318
319SDValue
320MSP430TargetLowering::LowerReturn(SDValue Chain,
321                                  CallingConv::ID CallConv, bool isVarArg,
322                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
323                                  DebugLoc dl, SelectionDAG &DAG) {
324
325  // CCValAssign - represent the assignment of the return value to a location
326  SmallVector<CCValAssign, 16> RVLocs;
327
328  // CCState - Info about the registers and stack slot.
329  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
330                 RVLocs, *DAG.getContext());
331
332  // Analize return values.
333  CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
334
335  // If this is the first return lowered for this function, add the regs to the
336  // liveout set for the function.
337  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
338    for (unsigned i = 0; i != RVLocs.size(); ++i)
339      if (RVLocs[i].isRegLoc())
340        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
341  }
342
343  SDValue Flag;
344
345  // Copy the result values into the output registers.
346  for (unsigned i = 0; i != RVLocs.size(); ++i) {
347    CCValAssign &VA = RVLocs[i];
348    assert(VA.isRegLoc() && "Can only return in registers!");
349
350    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
351                             Outs[i].Val, Flag);
352
353    // Guarantee that all emitted copies are stuck together,
354    // avoiding something bad.
355    Flag = Chain.getValue(1);
356  }
357
358  if (Flag.getNode())
359    return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
360
361  // Return Void
362  return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain);
363}
364
365/// LowerCCCCallTo - functions arguments are copied from virtual regs to
366/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
367/// TODO: sret.
368SDValue
369MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
370                                     CallingConv::ID CallConv, bool isVarArg,
371                                     bool isTailCall,
372                                     const SmallVectorImpl<ISD::OutputArg>
373                                       &Outs,
374                                     const SmallVectorImpl<ISD::InputArg> &Ins,
375                                     DebugLoc dl, SelectionDAG &DAG,
376                                     SmallVectorImpl<SDValue> &InVals) {
377  // Analyze operands of the call, assigning locations to each operand.
378  SmallVector<CCValAssign, 16> ArgLocs;
379  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
380                 ArgLocs, *DAG.getContext());
381
382  CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
383
384  // Get a count of how many bytes are to be pushed on the stack.
385  unsigned NumBytes = CCInfo.getNextStackOffset();
386
387  Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
388                                                      getPointerTy(), true));
389
390  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
391  SmallVector<SDValue, 12> MemOpChains;
392  SDValue StackPtr;
393
394  // Walk the register/memloc assignments, inserting copies/loads.
395  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
396    CCValAssign &VA = ArgLocs[i];
397
398    SDValue Arg = Outs[i].Val;
399
400    // Promote the value if needed.
401    switch (VA.getLocInfo()) {
402      default: llvm_unreachable("Unknown loc info!");
403      case CCValAssign::Full: break;
404      case CCValAssign::SExt:
405        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
406        break;
407      case CCValAssign::ZExt:
408        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
409        break;
410      case CCValAssign::AExt:
411        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
412        break;
413    }
414
415    // Arguments that can be passed on register must be kept at RegsToPass
416    // vector
417    if (VA.isRegLoc()) {
418      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
419    } else {
420      assert(VA.isMemLoc());
421
422      if (StackPtr.getNode() == 0)
423        StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
424
425      SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
426                                   StackPtr,
427                                   DAG.getIntPtrConstant(VA.getLocMemOffset()));
428
429
430      MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
431                                         PseudoSourceValue::getStack(),
432                                         VA.getLocMemOffset()));
433    }
434  }
435
436  // Transform all store nodes into one single node because all store nodes are
437  // independent of each other.
438  if (!MemOpChains.empty())
439    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
440                        &MemOpChains[0], MemOpChains.size());
441
442  // Build a sequence of copy-to-reg nodes chained together with token chain and
443  // flag operands which copy the outgoing args into registers.  The InFlag in
444  // necessary since all emited instructions must be stuck together.
445  SDValue InFlag;
446  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
447    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
448                             RegsToPass[i].second, InFlag);
449    InFlag = Chain.getValue(1);
450  }
451
452  // If the callee is a GlobalAddress node (quite common, every direct call is)
453  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
454  // Likewise ExternalSymbol -> TargetExternalSymbol.
455  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
456    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16);
457  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
458    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
459
460  // Returns a chain & a flag for retval copy to use.
461  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
462  SmallVector<SDValue, 8> Ops;
463  Ops.push_back(Chain);
464  Ops.push_back(Callee);
465
466  // Add argument registers to the end of the list so that they are
467  // known live into the call.
468  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
469    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
470                                  RegsToPass[i].second.getValueType()));
471
472  if (InFlag.getNode())
473    Ops.push_back(InFlag);
474
475  Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
476  InFlag = Chain.getValue(1);
477
478  // Create the CALLSEQ_END node.
479  Chain = DAG.getCALLSEQ_END(Chain,
480                             DAG.getConstant(NumBytes, getPointerTy(), true),
481                             DAG.getConstant(0, getPointerTy(), true),
482                             InFlag);
483  InFlag = Chain.getValue(1);
484
485  // Handle result values, copying them out of physregs into vregs that we
486  // return.
487  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
488                         DAG, InVals);
489}
490
491/// LowerCallResult - Lower the result values of a call into the
492/// appropriate copies out of appropriate physical registers.
493///
494SDValue
495MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
496                                      CallingConv::ID CallConv, bool isVarArg,
497                                      const SmallVectorImpl<ISD::InputArg> &Ins,
498                                      DebugLoc dl, SelectionDAG &DAG,
499                                      SmallVectorImpl<SDValue> &InVals) {
500
501  // Assign locations to each value returned by this call.
502  SmallVector<CCValAssign, 16> RVLocs;
503  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
504                 RVLocs, *DAG.getContext());
505
506  CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430);
507
508  // Copy all of the result registers out of their specified physreg.
509  for (unsigned i = 0; i != RVLocs.size(); ++i) {
510    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
511                               RVLocs[i].getValVT(), InFlag).getValue(1);
512    InFlag = Chain.getValue(2);
513    InVals.push_back(Chain.getValue(0));
514  }
515
516  return Chain;
517}
518
519SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
520                                          SelectionDAG &DAG) {
521  unsigned Opc = Op.getOpcode();
522  SDNode* N = Op.getNode();
523  EVT VT = Op.getValueType();
524  DebugLoc dl = N->getDebugLoc();
525
526  // We currently only lower shifts of constant argument.
527  if (!isa<ConstantSDNode>(N->getOperand(1)))
528    return SDValue();
529
530  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
531
532  // Expand the stuff into sequence of shifts.
533  // FIXME: for some shift amounts this might be done better!
534  // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
535  SDValue Victim = N->getOperand(0);
536
537  if (Opc == ISD::SRL && ShiftAmount) {
538    // Emit a special goodness here:
539    // srl A, 1 => clrc; rrc A
540    Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
541    ShiftAmount -= 1;
542  }
543
544  while (ShiftAmount--)
545    Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
546                         dl, VT, Victim);
547
548  return Victim;
549}
550
551SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
552  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
553  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
554
555  // Create the TargetGlobalAddress node, folding in the constant offset.
556  SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
557  return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
558                     getPointerTy(), Result);
559}
560
561SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
562                                                  SelectionDAG &DAG) {
563  DebugLoc dl = Op.getDebugLoc();
564  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
565  SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
566
567  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
568}
569
570static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, unsigned &TargetCC,
571                       ISD::CondCode CC,
572                       DebugLoc dl, SelectionDAG &DAG) {
573  // FIXME: Handle bittests someday
574  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
575
576  // FIXME: Handle jump negative someday
577  TargetCC = MSP430::COND_INVALID;
578  switch (CC) {
579  default: llvm_unreachable("Invalid integer condition!");
580  case ISD::SETEQ:
581    TargetCC = MSP430::COND_E;  // aka COND_Z
582    break;
583  case ISD::SETNE:
584    TargetCC = MSP430::COND_NE; // aka COND_NZ
585    break;
586  case ISD::SETULE:
587    std::swap(LHS, RHS);        // FALLTHROUGH
588  case ISD::SETUGE:
589    TargetCC = MSP430::COND_HS; // aka COND_C
590    break;
591  case ISD::SETUGT:
592    std::swap(LHS, RHS);        // FALLTHROUGH
593  case ISD::SETULT:
594    TargetCC = MSP430::COND_LO; // aka COND_NC
595    break;
596  case ISD::SETLE:
597    std::swap(LHS, RHS);        // FALLTHROUGH
598  case ISD::SETGE:
599    TargetCC = MSP430::COND_GE;
600    break;
601  case ISD::SETGT:
602    std::swap(LHS, RHS);        // FALLTHROUGH
603  case ISD::SETLT:
604    TargetCC = MSP430::COND_L;
605    break;
606  }
607
608  return DAG.getNode(MSP430ISD::CMP, dl, MVT::Flag, LHS, RHS);
609}
610
611
612SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
613  SDValue Chain = Op.getOperand(0);
614  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
615  SDValue LHS   = Op.getOperand(2);
616  SDValue RHS   = Op.getOperand(3);
617  SDValue Dest  = Op.getOperand(4);
618  DebugLoc dl   = Op.getDebugLoc();
619
620  unsigned TargetCC = MSP430::COND_INVALID;
621  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
622
623  return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
624                     Chain,
625                     Dest, DAG.getConstant(TargetCC, MVT::i8),
626                     Flag);
627}
628
629SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
630  SDValue LHS    = Op.getOperand(0);
631  SDValue RHS    = Op.getOperand(1);
632  SDValue TrueV  = Op.getOperand(2);
633  SDValue FalseV = Op.getOperand(3);
634  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
635  DebugLoc dl    = Op.getDebugLoc();
636
637  unsigned TargetCC = MSP430::COND_INVALID;
638  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
639
640  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
641  SmallVector<SDValue, 4> Ops;
642  Ops.push_back(TrueV);
643  Ops.push_back(FalseV);
644  Ops.push_back(DAG.getConstant(TargetCC, MVT::i8));
645  Ops.push_back(Flag);
646
647  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
648}
649
650SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
651                                               SelectionDAG &DAG) {
652  SDValue Val = Op.getOperand(0);
653  EVT VT      = Op.getValueType();
654  DebugLoc dl = Op.getDebugLoc();
655
656  assert(VT == MVT::i16 && "Only support i16 for now!");
657
658  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
659                     DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
660                     DAG.getValueType(Val.getValueType()));
661}
662
663const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
664  switch (Opcode) {
665  default: return NULL;
666  case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
667  case MSP430ISD::RRA:                return "MSP430ISD::RRA";
668  case MSP430ISD::RLA:                return "MSP430ISD::RLA";
669  case MSP430ISD::RRC:                return "MSP430ISD::RRC";
670  case MSP430ISD::CALL:               return "MSP430ISD::CALL";
671  case MSP430ISD::Wrapper:            return "MSP430ISD::Wrapper";
672  case MSP430ISD::BR_CC:              return "MSP430ISD::BR_CC";
673  case MSP430ISD::CMP:                return "MSP430ISD::CMP";
674  case MSP430ISD::SELECT_CC:          return "MSP430ISD::SELECT_CC";
675  }
676}
677
678//===----------------------------------------------------------------------===//
679//  Other Lowering Code
680//===----------------------------------------------------------------------===//
681
682MachineBasicBlock*
683MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
684                                                  MachineBasicBlock *BB) const {
685  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
686  DebugLoc dl = MI->getDebugLoc();
687  assert((MI->getOpcode() == MSP430::Select16 ||
688          MI->getOpcode() == MSP430::Select8) &&
689         "Unexpected instr type to insert");
690
691  // To "insert" a SELECT instruction, we actually have to insert the diamond
692  // control-flow pattern.  The incoming instruction knows the destination vreg
693  // to set, the condition code register to branch on, the true/false values to
694  // select between, and a branch opcode to use.
695  const BasicBlock *LLVM_BB = BB->getBasicBlock();
696  MachineFunction::iterator I = BB;
697  ++I;
698
699  //  thisMBB:
700  //  ...
701  //   TrueVal = ...
702  //   cmpTY ccX, r1, r2
703  //   jCC copy1MBB
704  //   fallthrough --> copy0MBB
705  MachineBasicBlock *thisMBB = BB;
706  MachineFunction *F = BB->getParent();
707  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
708  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
709  BuildMI(BB, dl, TII.get(MSP430::JCC))
710    .addMBB(copy1MBB)
711    .addImm(MI->getOperand(3).getImm());
712  F->insert(I, copy0MBB);
713  F->insert(I, copy1MBB);
714  // Update machine-CFG edges by transferring all successors of the current
715  // block to the new block which will contain the Phi node for the select.
716  copy1MBB->transferSuccessors(BB);
717  // Next, add the true and fallthrough blocks as its successors.
718  BB->addSuccessor(copy0MBB);
719  BB->addSuccessor(copy1MBB);
720
721  //  copy0MBB:
722  //   %FalseValue = ...
723  //   # fallthrough to copy1MBB
724  BB = copy0MBB;
725
726  // Update machine-CFG edges
727  BB->addSuccessor(copy1MBB);
728
729  //  copy1MBB:
730  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
731  //  ...
732  BB = copy1MBB;
733  BuildMI(BB, dl, TII.get(MSP430::PHI),
734          MI->getOperand(0).getReg())
735    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
736    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
737
738  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
739  return BB;
740}
741