MSP430ISelLowering.cpp revision 6bfcba7e137113e5f38cc4f937ad61cc7253ec74 
1//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MSP430TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "msp430-lower"
15
16#include "MSP430ISelLowering.h"
17#include "MSP430.h"
18#include "MSP430MachineFunctionInfo.h"
19#include "MSP430TargetMachine.h"
20#include "MSP430Subtarget.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
23#include "llvm/Intrinsics.h"
24#include "llvm/CallingConv.h"
25#include "llvm/GlobalVariable.h"
26#include "llvm/GlobalAlias.h"
27#include "llvm/CodeGen/CallingConvLower.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/PseudoSourceValue.h"
33#include "llvm/CodeGen/SelectionDAGISel.h"
34#include "llvm/CodeGen/ValueTypes.h"
35#include "llvm/Target/TargetLoweringObjectFile.h"
36#include "llvm/Support/CommandLine.h"
37#include "llvm/Support/Debug.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/raw_ostream.h"
40#include "llvm/ADT/VectorExtras.h"
41using namespace llvm;
42
43typedef enum {
44  NoHWMult,
45  HWMultIntr,
46  HWMultNoIntr
47} HWMultUseMode;
48
49static cl::opt<HWMultUseMode>
50HWMultMode("msp430-hwmult-mode",
51           cl::desc("Hardware multiplier use mode"),
52           cl::init(HWMultNoIntr),
53           cl::values(
54             clEnumValN(NoHWMult, "no",
55                "Do not use hardware multiplier"),
56             clEnumValN(HWMultIntr, "interrupts",
57                "Assume hardware multiplier can be used inside interrupts"),
58             clEnumValN(HWMultNoIntr, "use",
59                "Assume hardware multiplier cannot be used inside interrupts"),
60             clEnumValEnd));
61
62MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
63  TargetLowering(tm, new TargetLoweringObjectFileELF()),
64  Subtarget(*tm.getSubtargetImpl()), TM(tm) {
65
66  TD = getTargetData();
67
68  // Set up the register classes.
69  addRegisterClass(MVT::i8,  MSP430::GR8RegisterClass);
70  addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
71
72  // Compute derived properties from the register classes
73  computeRegisterProperties();
74
75  // Provide all sorts of operation actions
76
77  // Division is expensive
78  setIntDivIsCheap(false);
79
80  // Even if we have only 1 bit shift here, we can perform
81  // shifts of the whole bitwidth 1 bit per step.
82  setShiftAmountType(MVT::i8);
83
84  setStackPointerRegisterToSaveRestore(MSP430::SPW);
85  setBooleanContents(ZeroOrOneBooleanContent);
86  setSchedulingPreference(SchedulingForLatency);
87
88  // We have post-incremented loads / stores.
89  setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
90  setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
91
92  setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
93  setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
94  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
95  setLoadExtAction(ISD::SEXTLOAD, MVT::i8,  Expand);
96  setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
97
98  // We don't have any truncstores
99  setTruncStoreAction(MVT::i16, MVT::i8, Expand);
100
101  setOperationAction(ISD::SRA,              MVT::i8,    Custom);
102  setOperationAction(ISD::SHL,              MVT::i8,    Custom);
103  setOperationAction(ISD::SRL,              MVT::i8,    Custom);
104  setOperationAction(ISD::SRA,              MVT::i16,   Custom);
105  setOperationAction(ISD::SHL,              MVT::i16,   Custom);
106  setOperationAction(ISD::SRL,              MVT::i16,   Custom);
107  setOperationAction(ISD::ROTL,             MVT::i8,    Expand);
108  setOperationAction(ISD::ROTR,             MVT::i8,    Expand);
109  setOperationAction(ISD::ROTL,             MVT::i16,   Expand);
110  setOperationAction(ISD::ROTR,             MVT::i16,   Expand);
111  setOperationAction(ISD::GlobalAddress,    MVT::i16,   Custom);
112  setOperationAction(ISD::ExternalSymbol,   MVT::i16,   Custom);
113  setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
114  setOperationAction(ISD::BRIND,            MVT::Other, Expand);
115  setOperationAction(ISD::BR_CC,            MVT::i8,    Custom);
116  setOperationAction(ISD::BR_CC,            MVT::i16,   Custom);
117  setOperationAction(ISD::BRCOND,           MVT::Other, Expand);
118  setOperationAction(ISD::SETCC,            MVT::i8,    Expand);
119  setOperationAction(ISD::SETCC,            MVT::i16,   Expand);
120  setOperationAction(ISD::SELECT,           MVT::i8,    Expand);
121  setOperationAction(ISD::SELECT,           MVT::i16,   Expand);
122  setOperationAction(ISD::SELECT_CC,        MVT::i8,    Custom);
123  setOperationAction(ISD::SELECT_CC,        MVT::i16,   Custom);
124  setOperationAction(ISD::SIGN_EXTEND,      MVT::i16,   Custom);
125  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
126  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
127
128  setOperationAction(ISD::CTTZ,             MVT::i8,    Expand);
129  setOperationAction(ISD::CTTZ,             MVT::i16,   Expand);
130  setOperationAction(ISD::CTLZ,             MVT::i8,    Expand);
131  setOperationAction(ISD::CTLZ,             MVT::i16,   Expand);
132  setOperationAction(ISD::CTPOP,            MVT::i8,    Expand);
133  setOperationAction(ISD::CTPOP,            MVT::i16,   Expand);
134
135  setOperationAction(ISD::SHL_PARTS,        MVT::i8,    Expand);
136  setOperationAction(ISD::SHL_PARTS,        MVT::i16,   Expand);
137  setOperationAction(ISD::SRL_PARTS,        MVT::i8,    Expand);
138  setOperationAction(ISD::SRL_PARTS,        MVT::i16,   Expand);
139  setOperationAction(ISD::SRA_PARTS,        MVT::i8,    Expand);
140  setOperationAction(ISD::SRA_PARTS,        MVT::i16,   Expand);
141
142  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,   Expand);
143
144  // FIXME: Implement efficiently multiplication by a constant
145  setOperationAction(ISD::MUL,              MVT::i8,    Expand);
146  setOperationAction(ISD::MULHS,            MVT::i8,    Expand);
147  setOperationAction(ISD::MULHU,            MVT::i8,    Expand);
148  setOperationAction(ISD::SMUL_LOHI,        MVT::i8,    Expand);
149  setOperationAction(ISD::UMUL_LOHI,        MVT::i8,    Expand);
150  setOperationAction(ISD::MUL,              MVT::i16,   Expand);
151  setOperationAction(ISD::MULHS,            MVT::i16,   Expand);
152  setOperationAction(ISD::MULHU,            MVT::i16,   Expand);
153  setOperationAction(ISD::SMUL_LOHI,        MVT::i16,   Expand);
154  setOperationAction(ISD::UMUL_LOHI,        MVT::i16,   Expand);
155
156  setOperationAction(ISD::UDIV,             MVT::i8,    Expand);
157  setOperationAction(ISD::UDIVREM,          MVT::i8,    Expand);
158  setOperationAction(ISD::UREM,             MVT::i8,    Expand);
159  setOperationAction(ISD::SDIV,             MVT::i8,    Expand);
160  setOperationAction(ISD::SDIVREM,          MVT::i8,    Expand);
161  setOperationAction(ISD::SREM,             MVT::i8,    Expand);
162  setOperationAction(ISD::UDIV,             MVT::i16,   Expand);
163  setOperationAction(ISD::UDIVREM,          MVT::i16,   Expand);
164  setOperationAction(ISD::UREM,             MVT::i16,   Expand);
165  setOperationAction(ISD::SDIV,             MVT::i16,   Expand);
166  setOperationAction(ISD::SDIVREM,          MVT::i16,   Expand);
167  setOperationAction(ISD::SREM,             MVT::i16,   Expand);
168
169  // Libcalls names.
170  if (HWMultMode == HWMultIntr) {
171    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw");
172    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw");
173  } else if (HWMultMode == HWMultNoIntr) {
174    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw_noint");
175    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint");
176  }
177}
178
179SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
180  switch (Op.getOpcode()) {
181  case ISD::SHL: // FALLTHROUGH
182  case ISD::SRL:
183  case ISD::SRA:              return LowerShifts(Op, DAG);
184  case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
185  case ISD::ExternalSymbol:   return LowerExternalSymbol(Op, DAG);
186  case ISD::BR_CC:            return LowerBR_CC(Op, DAG);
187  case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
188  case ISD::SIGN_EXTEND:      return LowerSIGN_EXTEND(Op, DAG);
189  case ISD::RETURNADDR:       return LowerRETURNADDR(Op, DAG);
190  case ISD::FRAMEADDR:        return LowerFRAMEADDR(Op, DAG);
191  default:
192    llvm_unreachable("unimplemented operand");
193    return SDValue();
194  }
195}
196
197/// getFunctionAlignment - Return the Log2 alignment of this function.
198unsigned MSP430TargetLowering::getFunctionAlignment(const Function *F) const {
199  return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 2;
200}
201
202//===----------------------------------------------------------------------===//
203//                       MSP430 Inline Assembly Support
204//===----------------------------------------------------------------------===//
205
206/// getConstraintType - Given a constraint letter, return the type of
207/// constraint it is for this target.
208TargetLowering::ConstraintType
209MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
210  if (Constraint.size() == 1) {
211    switch (Constraint[0]) {
212    case 'r':
213      return C_RegisterClass;
214    default:
215      break;
216    }
217  }
218  return TargetLowering::getConstraintType(Constraint);
219}
220
221std::pair<unsigned, const TargetRegisterClass*>
222MSP430TargetLowering::
223getRegForInlineAsmConstraint(const std::string &Constraint,
224                             EVT VT) const {
225  if (Constraint.size() == 1) {
226    // GCC Constraint Letters
227    switch (Constraint[0]) {
228    default: break;
229    case 'r':   // GENERAL_REGS
230      if (VT == MVT::i8)
231        return std::make_pair(0U, MSP430::GR8RegisterClass);
232
233      return std::make_pair(0U, MSP430::GR16RegisterClass);
234    }
235  }
236
237  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
238}
239
240//===----------------------------------------------------------------------===//
241//                      Calling Convention Implementation
242//===----------------------------------------------------------------------===//
243
244#include "MSP430GenCallingConv.inc"
245
246SDValue
247MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
248                                           CallingConv::ID CallConv,
249                                           bool isVarArg,
250                                           const SmallVectorImpl<ISD::InputArg>
251                                             &Ins,
252                                           DebugLoc dl,
253                                           SelectionDAG &DAG,
254                                           SmallVectorImpl<SDValue> &InVals) {
255
256  switch (CallConv) {
257  default:
258    llvm_unreachable("Unsupported calling convention");
259  case CallingConv::C:
260  case CallingConv::Fast:
261    return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
262  case CallingConv::MSP430_INTR:
263   if (Ins.empty())
264     return Chain;
265   else {
266    llvm_report_error("ISRs cannot have arguments");
267    return SDValue();
268   }
269  }
270}
271
272SDValue
273MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
274                                CallingConv::ID CallConv, bool isVarArg,
275                                bool isTailCall,
276                                const SmallVectorImpl<ISD::OutputArg> &Outs,
277                                const SmallVectorImpl<ISD::InputArg> &Ins,
278                                DebugLoc dl, SelectionDAG &DAG,
279                                SmallVectorImpl<SDValue> &InVals) {
280
281  switch (CallConv) {
282  default:
283    llvm_unreachable("Unsupported calling convention");
284  case CallingConv::Fast:
285  case CallingConv::C:
286    return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
287                          Outs, Ins, dl, DAG, InVals);
288  case CallingConv::MSP430_INTR:
289    llvm_report_error("ISRs cannot be called directly");
290    return SDValue();
291  }
292}
293
294/// LowerCCCArguments - transform physical registers into virtual registers and
295/// generate load operations for arguments places on the stack.
296// FIXME: struct return stuff
297// FIXME: varargs
298SDValue
299MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
300                                        CallingConv::ID CallConv,
301                                        bool isVarArg,
302                                        const SmallVectorImpl<ISD::InputArg>
303                                          &Ins,
304                                        DebugLoc dl,
305                                        SelectionDAG &DAG,
306                                        SmallVectorImpl<SDValue> &InVals) {
307  MachineFunction &MF = DAG.getMachineFunction();
308  MachineFrameInfo *MFI = MF.getFrameInfo();
309  MachineRegisterInfo &RegInfo = MF.getRegInfo();
310
311  // Assign locations to all of the incoming arguments.
312  SmallVector<CCValAssign, 16> ArgLocs;
313  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
314                 ArgLocs, *DAG.getContext());
315  CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
316
317  assert(!isVarArg && "Varargs not supported yet");
318
319  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
320    CCValAssign &VA = ArgLocs[i];
321    if (VA.isRegLoc()) {
322      // Arguments passed in registers
323      EVT RegVT = VA.getLocVT();
324      switch (RegVT.getSimpleVT().SimpleTy) {
325      default:
326        {
327#ifndef NDEBUG
328          errs() << "LowerFormalArguments Unhandled argument type: "
329               << RegVT.getSimpleVT().SimpleTy << "\n";
330#endif
331          llvm_unreachable(0);
332        }
333      case MVT::i16:
334        unsigned VReg =
335          RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
336        RegInfo.addLiveIn(VA.getLocReg(), VReg);
337        SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
338
339        // If this is an 8-bit value, it is really passed promoted to 16
340        // bits. Insert an assert[sz]ext to capture this, then truncate to the
341        // right size.
342        if (VA.getLocInfo() == CCValAssign::SExt)
343          ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
344                                 DAG.getValueType(VA.getValVT()));
345        else if (VA.getLocInfo() == CCValAssign::ZExt)
346          ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
347                                 DAG.getValueType(VA.getValVT()));
348
349        if (VA.getLocInfo() != CCValAssign::Full)
350          ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
351
352        InVals.push_back(ArgValue);
353      }
354    } else {
355      // Sanity check
356      assert(VA.isMemLoc());
357      // Load the argument to a virtual register
358      unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
359      if (ObjSize > 2) {
360        errs() << "LowerFormalArguments Unhandled argument type: "
361             << VA.getLocVT().getSimpleVT().SimpleTy
362             << "\n";
363      }
364      // Create the frame index object for this incoming parameter...
365      int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true, false);
366
367      // Create the SelectionDAG nodes corresponding to a load
368      //from this parameter
369      SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
370      InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
371                                   PseudoSourceValue::getFixedStack(FI), 0));
372    }
373  }
374
375  return Chain;
376}
377
378SDValue
379MSP430TargetLowering::LowerReturn(SDValue Chain,
380                                  CallingConv::ID CallConv, bool isVarArg,
381                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
382                                  DebugLoc dl, SelectionDAG &DAG) {
383
384  // CCValAssign - represent the assignment of the return value to a location
385  SmallVector<CCValAssign, 16> RVLocs;
386
387  // ISRs cannot return any value.
388  if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) {
389    llvm_report_error("ISRs cannot return any value");
390    return SDValue();
391  }
392
393  // CCState - Info about the registers and stack slot.
394  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
395                 RVLocs, *DAG.getContext());
396
397  // Analize return values.
398  CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
399
400  // If this is the first return lowered for this function, add the regs to the
401  // liveout set for the function.
402  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
403    for (unsigned i = 0; i != RVLocs.size(); ++i)
404      if (RVLocs[i].isRegLoc())
405        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
406  }
407
408  SDValue Flag;
409
410  // Copy the result values into the output registers.
411  for (unsigned i = 0; i != RVLocs.size(); ++i) {
412    CCValAssign &VA = RVLocs[i];
413    assert(VA.isRegLoc() && "Can only return in registers!");
414
415    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
416                             Outs[i].Val, Flag);
417
418    // Guarantee that all emitted copies are stuck together,
419    // avoiding something bad.
420    Flag = Chain.getValue(1);
421  }
422
423  unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
424                  MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG);
425
426  if (Flag.getNode())
427    return DAG.getNode(Opc, dl, MVT::Other, Chain, Flag);
428
429  // Return Void
430  return DAG.getNode(Opc, dl, MVT::Other, Chain);
431}
432
433/// LowerCCCCallTo - functions arguments are copied from virtual regs to
434/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
435/// TODO: sret.
436SDValue
437MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
438                                     CallingConv::ID CallConv, bool isVarArg,
439                                     bool isTailCall,
440                                     const SmallVectorImpl<ISD::OutputArg>
441                                       &Outs,
442                                     const SmallVectorImpl<ISD::InputArg> &Ins,
443                                     DebugLoc dl, SelectionDAG &DAG,
444                                     SmallVectorImpl<SDValue> &InVals) {
445  // Analyze operands of the call, assigning locations to each operand.
446  SmallVector<CCValAssign, 16> ArgLocs;
447  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
448                 ArgLocs, *DAG.getContext());
449
450  CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
451
452  // Get a count of how many bytes are to be pushed on the stack.
453  unsigned NumBytes = CCInfo.getNextStackOffset();
454
455  Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
456                                                      getPointerTy(), true));
457
458  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
459  SmallVector<SDValue, 12> MemOpChains;
460  SDValue StackPtr;
461
462  // Walk the register/memloc assignments, inserting copies/loads.
463  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
464    CCValAssign &VA = ArgLocs[i];
465
466    SDValue Arg = Outs[i].Val;
467
468    // Promote the value if needed.
469    switch (VA.getLocInfo()) {
470      default: llvm_unreachable("Unknown loc info!");
471      case CCValAssign::Full: break;
472      case CCValAssign::SExt:
473        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
474        break;
475      case CCValAssign::ZExt:
476        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
477        break;
478      case CCValAssign::AExt:
479        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
480        break;
481    }
482
483    // Arguments that can be passed on register must be kept at RegsToPass
484    // vector
485    if (VA.isRegLoc()) {
486      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
487    } else {
488      assert(VA.isMemLoc());
489
490      if (StackPtr.getNode() == 0)
491        StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
492
493      SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
494                                   StackPtr,
495                                   DAG.getIntPtrConstant(VA.getLocMemOffset()));
496
497
498      MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
499                                         PseudoSourceValue::getStack(),
500                                         VA.getLocMemOffset()));
501    }
502  }
503
504  // Transform all store nodes into one single node because all store nodes are
505  // independent of each other.
506  if (!MemOpChains.empty())
507    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
508                        &MemOpChains[0], MemOpChains.size());
509
510  // Build a sequence of copy-to-reg nodes chained together with token chain and
511  // flag operands which copy the outgoing args into registers.  The InFlag in
512  // necessary since all emited instructions must be stuck together.
513  SDValue InFlag;
514  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
515    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
516                             RegsToPass[i].second, InFlag);
517    InFlag = Chain.getValue(1);
518  }
519
520  // If the callee is a GlobalAddress node (quite common, every direct call is)
521  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
522  // Likewise ExternalSymbol -> TargetExternalSymbol.
523  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
524    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16);
525  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
526    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
527
528  // Returns a chain & a flag for retval copy to use.
529  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
530  SmallVector<SDValue, 8> Ops;
531  Ops.push_back(Chain);
532  Ops.push_back(Callee);
533
534  // Add argument registers to the end of the list so that they are
535  // known live into the call.
536  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
537    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
538                                  RegsToPass[i].second.getValueType()));
539
540  if (InFlag.getNode())
541    Ops.push_back(InFlag);
542
543  Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
544  InFlag = Chain.getValue(1);
545
546  // Create the CALLSEQ_END node.
547  Chain = DAG.getCALLSEQ_END(Chain,
548                             DAG.getConstant(NumBytes, getPointerTy(), true),
549                             DAG.getConstant(0, getPointerTy(), true),
550                             InFlag);
551  InFlag = Chain.getValue(1);
552
553  // Handle result values, copying them out of physregs into vregs that we
554  // return.
555  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
556                         DAG, InVals);
557}
558
559/// LowerCallResult - Lower the result values of a call into the
560/// appropriate copies out of appropriate physical registers.
561///
562SDValue
563MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
564                                      CallingConv::ID CallConv, bool isVarArg,
565                                      const SmallVectorImpl<ISD::InputArg> &Ins,
566                                      DebugLoc dl, SelectionDAG &DAG,
567                                      SmallVectorImpl<SDValue> &InVals) {
568
569  // Assign locations to each value returned by this call.
570  SmallVector<CCValAssign, 16> RVLocs;
571  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
572                 RVLocs, *DAG.getContext());
573
574  CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430);
575
576  // Copy all of the result registers out of their specified physreg.
577  for (unsigned i = 0; i != RVLocs.size(); ++i) {
578    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
579                               RVLocs[i].getValVT(), InFlag).getValue(1);
580    InFlag = Chain.getValue(2);
581    InVals.push_back(Chain.getValue(0));
582  }
583
584  return Chain;
585}
586
587SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
588                                          SelectionDAG &DAG) {
589  unsigned Opc = Op.getOpcode();
590  SDNode* N = Op.getNode();
591  EVT VT = Op.getValueType();
592  DebugLoc dl = N->getDebugLoc();
593
594  // We currently only lower shifts of constant argument.
595  if (!isa<ConstantSDNode>(N->getOperand(1)))
596    return SDValue();
597
598  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
599
600  // Expand the stuff into sequence of shifts.
601  // FIXME: for some shift amounts this might be done better!
602  // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
603  SDValue Victim = N->getOperand(0);
604
605  if (Opc == ISD::SRL && ShiftAmount) {
606    // Emit a special goodness here:
607    // srl A, 1 => clrc; rrc A
608    Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
609    ShiftAmount -= 1;
610  }
611
612  while (ShiftAmount--)
613    Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
614                         dl, VT, Victim);
615
616  return Victim;
617}
618
619SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
620  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
621  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
622
623  // Create the TargetGlobalAddress node, folding in the constant offset.
624  SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
625  return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
626                     getPointerTy(), Result);
627}
628
629SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
630                                                  SelectionDAG &DAG) {
631  DebugLoc dl = Op.getDebugLoc();
632  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
633  SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
634
635  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
636}
637
638static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
639                       ISD::CondCode CC,
640                       DebugLoc dl, SelectionDAG &DAG) {
641  // FIXME: Handle bittests someday
642  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
643
644  // FIXME: Handle jump negative someday
645  MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
646  switch (CC) {
647  default: llvm_unreachable("Invalid integer condition!");
648  case ISD::SETEQ:
649    TCC = MSP430CC::COND_E;     // aka COND_Z
650    // Minor optimization: if RHS is a constant, swap operands, then the
651    // constant can be folded into comparison.
652    if (RHS.getOpcode() == ISD::Constant)
653      std::swap(LHS, RHS);
654    break;
655  case ISD::SETNE:
656    TCC = MSP430CC::COND_NE;    // aka COND_NZ
657    // Minor optimization: if RHS is a constant, swap operands, then the
658    // constant can be folded into comparison.
659    if (RHS.getOpcode() == ISD::Constant)
660      std::swap(LHS, RHS);
661    break;
662  case ISD::SETULE:
663    std::swap(LHS, RHS);        // FALLTHROUGH
664  case ISD::SETUGE:
665    TCC = MSP430CC::COND_HS;    // aka COND_C
666    break;
667  case ISD::SETUGT:
668    std::swap(LHS, RHS);        // FALLTHROUGH
669  case ISD::SETULT:
670    TCC = MSP430CC::COND_LO;    // aka COND_NC
671    break;
672  case ISD::SETLE:
673    std::swap(LHS, RHS);        // FALLTHROUGH
674  case ISD::SETGE:
675    TCC = MSP430CC::COND_GE;
676    break;
677  case ISD::SETGT:
678    std::swap(LHS, RHS);        // FALLTHROUGH
679  case ISD::SETLT:
680    TCC = MSP430CC::COND_L;
681    break;
682  }
683
684  TargetCC = DAG.getConstant(TCC, MVT::i8);
685  return DAG.getNode(MSP430ISD::CMP, dl, MVT::Flag, LHS, RHS);
686}
687
688
689SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
690  SDValue Chain = Op.getOperand(0);
691  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
692  SDValue LHS   = Op.getOperand(2);
693  SDValue RHS   = Op.getOperand(3);
694  SDValue Dest  = Op.getOperand(4);
695  DebugLoc dl   = Op.getDebugLoc();
696
697  SDValue TargetCC;
698  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
699
700  return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
701                     Chain, Dest, TargetCC, Flag);
702}
703
704SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
705  SDValue LHS    = Op.getOperand(0);
706  SDValue RHS    = Op.getOperand(1);
707  SDValue TrueV  = Op.getOperand(2);
708  SDValue FalseV = Op.getOperand(3);
709  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
710  DebugLoc dl    = Op.getDebugLoc();
711
712  SDValue TargetCC;
713  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
714
715  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
716  SmallVector<SDValue, 4> Ops;
717  Ops.push_back(TrueV);
718  Ops.push_back(FalseV);
719  Ops.push_back(TargetCC);
720  Ops.push_back(Flag);
721
722  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
723}
724
725SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
726                                               SelectionDAG &DAG) {
727  SDValue Val = Op.getOperand(0);
728  EVT VT      = Op.getValueType();
729  DebugLoc dl = Op.getDebugLoc();
730
731  assert(VT == MVT::i16 && "Only support i16 for now!");
732
733  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
734                     DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
735                     DAG.getValueType(Val.getValueType()));
736}
737
738SDValue MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
739  MachineFunction &MF = DAG.getMachineFunction();
740  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
741  int ReturnAddrIndex = FuncInfo->getRAIndex();
742
743  if (ReturnAddrIndex == 0) {
744    // Set up a frame object for the return address.
745    uint64_t SlotSize = TD->getPointerSize();
746    ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
747                                                           true, false);
748    FuncInfo->setRAIndex(ReturnAddrIndex);
749  }
750
751  return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
752}
753
754SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
755  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
756  DebugLoc dl = Op.getDebugLoc();
757
758  if (Depth > 0) {
759    SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
760    SDValue Offset =
761      DAG.getConstant(TD->getPointerSize(), MVT::i16);
762    return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
763                       DAG.getNode(ISD::ADD, dl, getPointerTy(),
764                                   FrameAddr, Offset),
765                       NULL, 0);
766  }
767
768  // Just load the return address.
769  SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
770  return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
771                     RetAddrFI, NULL, 0);
772}
773
774SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
775  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
776  MFI->setFrameAddressIsTaken(true);
777  EVT VT = Op.getValueType();
778  DebugLoc dl = Op.getDebugLoc();  // FIXME probably not meaningful
779  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
780  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
781                                         MSP430::FPW, VT);
782  while (Depth--)
783    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
784  return FrameAddr;
785}
786
787/// getPostIndexedAddressParts - returns true by value, base pointer and
788/// offset pointer and addressing mode by reference if this node can be
789/// combined with a load / store to form a post-indexed load / store.
790bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
791                                                      SDValue &Base,
792                                                      SDValue &Offset,
793                                                      ISD::MemIndexedMode &AM,
794                                                      SelectionDAG &DAG) const {
795
796  LoadSDNode *LD = cast<LoadSDNode>(N);
797  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
798    return false;
799
800  EVT VT = LD->getMemoryVT();
801  if (VT != MVT::i8 && VT != MVT::i16)
802    return false;
803
804  if (Op->getOpcode() != ISD::ADD)
805    return false;
806
807  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
808    uint64_t RHSC = RHS->getZExtValue();
809    if ((VT == MVT::i16 && RHSC != 2) ||
810        (VT == MVT::i8 && RHSC != 1))
811      return false;
812
813    Base = Op->getOperand(0);
814    Offset = DAG.getConstant(RHSC, VT);
815    AM = ISD::POST_INC;
816    return true;
817  }
818
819  return false;
820}
821
822
823const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
824  switch (Opcode) {
825  default: return NULL;
826  case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
827  case MSP430ISD::RETI_FLAG:          return "MSP430ISD::RETI_FLAG";
828  case MSP430ISD::RRA:                return "MSP430ISD::RRA";
829  case MSP430ISD::RLA:                return "MSP430ISD::RLA";
830  case MSP430ISD::RRC:                return "MSP430ISD::RRC";
831  case MSP430ISD::CALL:               return "MSP430ISD::CALL";
832  case MSP430ISD::Wrapper:            return "MSP430ISD::Wrapper";
833  case MSP430ISD::BR_CC:              return "MSP430ISD::BR_CC";
834  case MSP430ISD::CMP:                return "MSP430ISD::CMP";
835  case MSP430ISD::SELECT_CC:          return "MSP430ISD::SELECT_CC";
836  }
837}
838
839//===----------------------------------------------------------------------===//
840//  Other Lowering Code
841//===----------------------------------------------------------------------===//
842
843MachineBasicBlock*
844MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
845                                                  MachineBasicBlock *BB,
846                   DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
847  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
848  DebugLoc dl = MI->getDebugLoc();
849  assert((MI->getOpcode() == MSP430::Select16 ||
850          MI->getOpcode() == MSP430::Select8) &&
851         "Unexpected instr type to insert");
852
853  // To "insert" a SELECT instruction, we actually have to insert the diamond
854  // control-flow pattern.  The incoming instruction knows the destination vreg
855  // to set, the condition code register to branch on, the true/false values to
856  // select between, and a branch opcode to use.
857  const BasicBlock *LLVM_BB = BB->getBasicBlock();
858  MachineFunction::iterator I = BB;
859  ++I;
860
861  //  thisMBB:
862  //  ...
863  //   TrueVal = ...
864  //   cmpTY ccX, r1, r2
865  //   jCC copy1MBB
866  //   fallthrough --> copy0MBB
867  MachineBasicBlock *thisMBB = BB;
868  MachineFunction *F = BB->getParent();
869  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
870  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
871  BuildMI(BB, dl, TII.get(MSP430::JCC))
872    .addMBB(copy1MBB)
873    .addImm(MI->getOperand(3).getImm());
874  F->insert(I, copy0MBB);
875  F->insert(I, copy1MBB);
876  // Inform sdisel of the edge changes.
877  for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
878         SE = BB->succ_end(); SI != SE; ++SI)
879    EM->insert(std::make_pair(*SI, copy1MBB));
880  // Update machine-CFG edges by transferring all successors of the current
881  // block to the new block which will contain the Phi node for the select.
882  copy1MBB->transferSuccessors(BB);
883  // Next, add the true and fallthrough blocks as its successors.
884  BB->addSuccessor(copy0MBB);
885  BB->addSuccessor(copy1MBB);
886
887  //  copy0MBB:
888  //   %FalseValue = ...
889  //   # fallthrough to copy1MBB
890  BB = copy0MBB;
891
892  // Update machine-CFG edges
893  BB->addSuccessor(copy1MBB);
894
895  //  copy1MBB:
896  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
897  //  ...
898  BB = copy1MBB;
899  BuildMI(BB, dl, TII.get(MSP430::PHI),
900          MI->getOperand(0).getReg())
901    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
902    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
903
904  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
905  return BB;
906}
907