MSP430ISelLowering.cpp revision 968b667e27d7fc9a5bf5da52191a7af629e174dc 
1//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MSP430TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "msp430-lower"
15
16#include "MSP430ISelLowering.h"
17#include "MSP430.h"
18#include "MSP430MachineFunctionInfo.h"
19#include "MSP430Subtarget.h"
20#include "MSP430TargetMachine.h"
21#include "llvm/CallingConv.h"
22#include "llvm/CodeGen/CallingConvLower.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineFunction.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineRegisterInfo.h"
27#include "llvm/CodeGen/SelectionDAGISel.h"
28#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29#include "llvm/CodeGen/ValueTypes.h"
30#include "llvm/DerivedTypes.h"
31#include "llvm/Function.h"
32#include "llvm/GlobalAlias.h"
33#include "llvm/GlobalVariable.h"
34#include "llvm/Intrinsics.h"
35#include "llvm/Support/CommandLine.h"
36#include "llvm/Support/Debug.h"
37#include "llvm/Support/ErrorHandling.h"
38#include "llvm/Support/raw_ostream.h"
39using namespace llvm;
40
41typedef enum {
42  NoHWMult,
43  HWMultIntr,
44  HWMultNoIntr
45} HWMultUseMode;
46
47static cl::opt<HWMultUseMode>
48HWMultMode("msp430-hwmult-mode",
49           cl::desc("Hardware multiplier use mode"),
50           cl::init(HWMultNoIntr),
51           cl::values(
52             clEnumValN(NoHWMult, "no",
53                "Do not use hardware multiplier"),
54             clEnumValN(HWMultIntr, "interrupts",
55                "Assume hardware multiplier can be used inside interrupts"),
56             clEnumValN(HWMultNoIntr, "use",
57                "Assume hardware multiplier cannot be used inside interrupts"),
58             clEnumValEnd));
59
60MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
61  TargetLowering(tm, new TargetLoweringObjectFileELF()),
62  Subtarget(*tm.getSubtargetImpl()) {
63
64  TD = getDataLayout();
65
66  // Set up the register classes.
67  addRegisterClass(MVT::i8,  &MSP430::GR8RegClass);
68  addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
69
70  // Compute derived properties from the register classes
71  computeRegisterProperties();
72
73  // Provide all sorts of operation actions
74
75  // Division is expensive
76  setIntDivIsCheap(false);
77
78  setStackPointerRegisterToSaveRestore(MSP430::SPW);
79  setBooleanContents(ZeroOrOneBooleanContent);
80  setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
81
82  // We have post-incremented loads / stores.
83  setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
84  setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
85
86  setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
87  setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
88  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
89  setLoadExtAction(ISD::SEXTLOAD, MVT::i8,  Expand);
90  setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
91
92  // We don't have any truncstores
93  setTruncStoreAction(MVT::i16, MVT::i8, Expand);
94
95  setOperationAction(ISD::SRA,              MVT::i8,    Custom);
96  setOperationAction(ISD::SHL,              MVT::i8,    Custom);
97  setOperationAction(ISD::SRL,              MVT::i8,    Custom);
98  setOperationAction(ISD::SRA,              MVT::i16,   Custom);
99  setOperationAction(ISD::SHL,              MVT::i16,   Custom);
100  setOperationAction(ISD::SRL,              MVT::i16,   Custom);
101  setOperationAction(ISD::ROTL,             MVT::i8,    Expand);
102  setOperationAction(ISD::ROTR,             MVT::i8,    Expand);
103  setOperationAction(ISD::ROTL,             MVT::i16,   Expand);
104  setOperationAction(ISD::ROTR,             MVT::i16,   Expand);
105  setOperationAction(ISD::GlobalAddress,    MVT::i16,   Custom);
106  setOperationAction(ISD::ExternalSymbol,   MVT::i16,   Custom);
107  setOperationAction(ISD::BlockAddress,     MVT::i16,   Custom);
108  setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
109  setOperationAction(ISD::BR_CC,            MVT::i8,    Custom);
110  setOperationAction(ISD::BR_CC,            MVT::i16,   Custom);
111  setOperationAction(ISD::BRCOND,           MVT::Other, Expand);
112  setOperationAction(ISD::SETCC,            MVT::i8,    Custom);
113  setOperationAction(ISD::SETCC,            MVT::i16,   Custom);
114  setOperationAction(ISD::SELECT,           MVT::i8,    Expand);
115  setOperationAction(ISD::SELECT,           MVT::i16,   Expand);
116  setOperationAction(ISD::SELECT_CC,        MVT::i8,    Custom);
117  setOperationAction(ISD::SELECT_CC,        MVT::i16,   Custom);
118  setOperationAction(ISD::SIGN_EXTEND,      MVT::i16,   Custom);
119  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
120  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
121
122  setOperationAction(ISD::CTTZ,             MVT::i8,    Expand);
123  setOperationAction(ISD::CTTZ,             MVT::i16,   Expand);
124  setOperationAction(ISD::CTTZ_ZERO_UNDEF,  MVT::i8,    Expand);
125  setOperationAction(ISD::CTTZ_ZERO_UNDEF,  MVT::i16,   Expand);
126  setOperationAction(ISD::CTLZ,             MVT::i8,    Expand);
127  setOperationAction(ISD::CTLZ,             MVT::i16,   Expand);
128  setOperationAction(ISD::CTLZ_ZERO_UNDEF,  MVT::i8,    Expand);
129  setOperationAction(ISD::CTLZ_ZERO_UNDEF,  MVT::i16,   Expand);
130  setOperationAction(ISD::CTPOP,            MVT::i8,    Expand);
131  setOperationAction(ISD::CTPOP,            MVT::i16,   Expand);
132
133  setOperationAction(ISD::SHL_PARTS,        MVT::i8,    Expand);
134  setOperationAction(ISD::SHL_PARTS,        MVT::i16,   Expand);
135  setOperationAction(ISD::SRL_PARTS,        MVT::i8,    Expand);
136  setOperationAction(ISD::SRL_PARTS,        MVT::i16,   Expand);
137  setOperationAction(ISD::SRA_PARTS,        MVT::i8,    Expand);
138  setOperationAction(ISD::SRA_PARTS,        MVT::i16,   Expand);
139
140  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,   Expand);
141
142  // FIXME: Implement efficiently multiplication by a constant
143  setOperationAction(ISD::MUL,              MVT::i8,    Expand);
144  setOperationAction(ISD::MULHS,            MVT::i8,    Expand);
145  setOperationAction(ISD::MULHU,            MVT::i8,    Expand);
146  setOperationAction(ISD::SMUL_LOHI,        MVT::i8,    Expand);
147  setOperationAction(ISD::UMUL_LOHI,        MVT::i8,    Expand);
148  setOperationAction(ISD::MUL,              MVT::i16,   Expand);
149  setOperationAction(ISD::MULHS,            MVT::i16,   Expand);
150  setOperationAction(ISD::MULHU,            MVT::i16,   Expand);
151  setOperationAction(ISD::SMUL_LOHI,        MVT::i16,   Expand);
152  setOperationAction(ISD::UMUL_LOHI,        MVT::i16,   Expand);
153
154  setOperationAction(ISD::UDIV,             MVT::i8,    Expand);
155  setOperationAction(ISD::UDIVREM,          MVT::i8,    Expand);
156  setOperationAction(ISD::UREM,             MVT::i8,    Expand);
157  setOperationAction(ISD::SDIV,             MVT::i8,    Expand);
158  setOperationAction(ISD::SDIVREM,          MVT::i8,    Expand);
159  setOperationAction(ISD::SREM,             MVT::i8,    Expand);
160  setOperationAction(ISD::UDIV,             MVT::i16,   Expand);
161  setOperationAction(ISD::UDIVREM,          MVT::i16,   Expand);
162  setOperationAction(ISD::UREM,             MVT::i16,   Expand);
163  setOperationAction(ISD::SDIV,             MVT::i16,   Expand);
164  setOperationAction(ISD::SDIVREM,          MVT::i16,   Expand);
165  setOperationAction(ISD::SREM,             MVT::i16,   Expand);
166
167  // varargs support
168  setOperationAction(ISD::VASTART,          MVT::Other, Custom);
169  setOperationAction(ISD::VAARG,            MVT::Other, Expand);
170  setOperationAction(ISD::VAEND,            MVT::Other, Expand);
171  setOperationAction(ISD::VACOPY,           MVT::Other, Expand);
172
173  // Libcalls names.
174  if (HWMultMode == HWMultIntr) {
175    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw");
176    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw");
177  } else if (HWMultMode == HWMultNoIntr) {
178    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw_noint");
179    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint");
180  }
181
182  setMinFunctionAlignment(1);
183  setPrefFunctionAlignment(2);
184}
185
186SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
187                                             SelectionDAG &DAG) const {
188  switch (Op.getOpcode()) {
189  case ISD::SHL: // FALLTHROUGH
190  case ISD::SRL:
191  case ISD::SRA:              return LowerShifts(Op, DAG);
192  case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
193  case ISD::BlockAddress:     return LowerBlockAddress(Op, DAG);
194  case ISD::ExternalSymbol:   return LowerExternalSymbol(Op, DAG);
195  case ISD::SETCC:            return LowerSETCC(Op, DAG);
196  case ISD::BR_CC:            return LowerBR_CC(Op, DAG);
197  case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
198  case ISD::SIGN_EXTEND:      return LowerSIGN_EXTEND(Op, DAG);
199  case ISD::RETURNADDR:       return LowerRETURNADDR(Op, DAG);
200  case ISD::FRAMEADDR:        return LowerFRAMEADDR(Op, DAG);
201  case ISD::VASTART:          return LowerVASTART(Op, DAG);
202  default:
203    llvm_unreachable("unimplemented operand");
204  }
205}
206
207//===----------------------------------------------------------------------===//
208//                       MSP430 Inline Assembly Support
209//===----------------------------------------------------------------------===//
210
211/// getConstraintType - Given a constraint letter, return the type of
212/// constraint it is for this target.
213TargetLowering::ConstraintType
214MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
215  if (Constraint.size() == 1) {
216    switch (Constraint[0]) {
217    case 'r':
218      return C_RegisterClass;
219    default:
220      break;
221    }
222  }
223  return TargetLowering::getConstraintType(Constraint);
224}
225
226std::pair<unsigned, const TargetRegisterClass*>
227MSP430TargetLowering::
228getRegForInlineAsmConstraint(const std::string &Constraint,
229                             EVT VT) const {
230  if (Constraint.size() == 1) {
231    // GCC Constraint Letters
232    switch (Constraint[0]) {
233    default: break;
234    case 'r':   // GENERAL_REGS
235      if (VT == MVT::i8)
236        return std::make_pair(0U, &MSP430::GR8RegClass);
237
238      return std::make_pair(0U, &MSP430::GR16RegClass);
239    }
240  }
241
242  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
243}
244
245//===----------------------------------------------------------------------===//
246//                      Calling Convention Implementation
247//===----------------------------------------------------------------------===//
248
249#include "MSP430GenCallingConv.inc"
250
251SDValue
252MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
253                                           CallingConv::ID CallConv,
254                                           bool isVarArg,
255                                           const SmallVectorImpl<ISD::InputArg>
256                                             &Ins,
257                                           DebugLoc dl,
258                                           SelectionDAG &DAG,
259                                           SmallVectorImpl<SDValue> &InVals)
260                                             const {
261
262  switch (CallConv) {
263  default:
264    llvm_unreachable("Unsupported calling convention");
265  case CallingConv::C:
266  case CallingConv::Fast:
267    return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
268  case CallingConv::MSP430_INTR:
269    if (Ins.empty())
270      return Chain;
271    report_fatal_error("ISRs cannot have arguments");
272  }
273}
274
275SDValue
276MSP430TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
277                                SmallVectorImpl<SDValue> &InVals) const {
278  SelectionDAG &DAG                     = CLI.DAG;
279  DebugLoc &dl                          = CLI.DL;
280  SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
281  SmallVector<SDValue, 32> &OutVals     = CLI.OutVals;
282  SmallVector<ISD::InputArg, 32> &Ins   = CLI.Ins;
283  SDValue Chain                         = CLI.Chain;
284  SDValue Callee                        = CLI.Callee;
285  bool &isTailCall                      = CLI.IsTailCall;
286  CallingConv::ID CallConv              = CLI.CallConv;
287  bool isVarArg                         = CLI.IsVarArg;
288
289  // MSP430 target does not yet support tail call optimization.
290  isTailCall = false;
291
292  switch (CallConv) {
293  default:
294    llvm_unreachable("Unsupported calling convention");
295  case CallingConv::Fast:
296  case CallingConv::C:
297    return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
298                          Outs, OutVals, Ins, dl, DAG, InVals);
299  case CallingConv::MSP430_INTR:
300    report_fatal_error("ISRs cannot be called directly");
301  }
302}
303
304/// LowerCCCArguments - transform physical registers into virtual registers and
305/// generate load operations for arguments places on the stack.
306// FIXME: struct return stuff
307SDValue
308MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
309                                        CallingConv::ID CallConv,
310                                        bool isVarArg,
311                                        const SmallVectorImpl<ISD::InputArg>
312                                          &Ins,
313                                        DebugLoc dl,
314                                        SelectionDAG &DAG,
315                                        SmallVectorImpl<SDValue> &InVals)
316                                          const {
317  MachineFunction &MF = DAG.getMachineFunction();
318  MachineFrameInfo *MFI = MF.getFrameInfo();
319  MachineRegisterInfo &RegInfo = MF.getRegInfo();
320  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
321
322  // Assign locations to all of the incoming arguments.
323  SmallVector<CCValAssign, 16> ArgLocs;
324  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
325                 getTargetMachine(), ArgLocs, *DAG.getContext());
326  CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
327
328  // Create frame index for the start of the first vararg value
329  if (isVarArg) {
330    unsigned Offset = CCInfo.getNextStackOffset();
331    FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, Offset, true));
332  }
333
334  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
335    CCValAssign &VA = ArgLocs[i];
336    if (VA.isRegLoc()) {
337      // Arguments passed in registers
338      EVT RegVT = VA.getLocVT();
339      switch (RegVT.getSimpleVT().SimpleTy) {
340      default:
341        {
342#ifndef NDEBUG
343          errs() << "LowerFormalArguments Unhandled argument type: "
344               << RegVT.getSimpleVT().SimpleTy << "\n";
345#endif
346          llvm_unreachable(0);
347        }
348      case MVT::i16:
349        unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass);
350        RegInfo.addLiveIn(VA.getLocReg(), VReg);
351        SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
352
353        // If this is an 8-bit value, it is really passed promoted to 16
354        // bits. Insert an assert[sz]ext to capture this, then truncate to the
355        // right size.
356        if (VA.getLocInfo() == CCValAssign::SExt)
357          ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
358                                 DAG.getValueType(VA.getValVT()));
359        else if (VA.getLocInfo() == CCValAssign::ZExt)
360          ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
361                                 DAG.getValueType(VA.getValVT()));
362
363        if (VA.getLocInfo() != CCValAssign::Full)
364          ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
365
366        InVals.push_back(ArgValue);
367      }
368    } else {
369      // Sanity check
370      assert(VA.isMemLoc());
371
372      SDValue InVal;
373      ISD::ArgFlagsTy Flags = Ins[i].Flags;
374
375      if (Flags.isByVal()) {
376        int FI = MFI->CreateFixedObject(Flags.getByValSize(),
377                                        VA.getLocMemOffset(), true);
378        InVal = DAG.getFrameIndex(FI, getPointerTy());
379      } else {
380        // Load the argument to a virtual register
381        unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
382        if (ObjSize > 2) {
383            errs() << "LowerFormalArguments Unhandled argument type: "
384                << EVT(VA.getLocVT()).getEVTString()
385                << "\n";
386        }
387        // Create the frame index object for this incoming parameter...
388        int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
389
390        // Create the SelectionDAG nodes corresponding to a load
391        //from this parameter
392        SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
393        InVal = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
394                            MachinePointerInfo::getFixedStack(FI),
395                            false, false, false, 0);
396      }
397
398      InVals.push_back(InVal);
399    }
400  }
401
402  return Chain;
403}
404
405SDValue
406MSP430TargetLowering::LowerReturn(SDValue Chain,
407                                  CallingConv::ID CallConv, bool isVarArg,
408                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
409                                  const SmallVectorImpl<SDValue> &OutVals,
410                                  DebugLoc dl, SelectionDAG &DAG) const {
411
412  // CCValAssign - represent the assignment of the return value to a location
413  SmallVector<CCValAssign, 16> RVLocs;
414
415  // ISRs cannot return any value.
416  if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
417    report_fatal_error("ISRs cannot return any value");
418
419  // CCState - Info about the registers and stack slot.
420  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
421                 getTargetMachine(), RVLocs, *DAG.getContext());
422
423  // Analize return values.
424  CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
425
426  // If this is the first return lowered for this function, add the regs to the
427  // liveout set for the function.
428  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
429    for (unsigned i = 0; i != RVLocs.size(); ++i)
430      if (RVLocs[i].isRegLoc())
431        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
432  }
433
434  SDValue Flag;
435
436  // Copy the result values into the output registers.
437  for (unsigned i = 0; i != RVLocs.size(); ++i) {
438    CCValAssign &VA = RVLocs[i];
439    assert(VA.isRegLoc() && "Can only return in registers!");
440
441    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
442                             OutVals[i], Flag);
443
444    // Guarantee that all emitted copies are stuck together,
445    // avoiding something bad.
446    Flag = Chain.getValue(1);
447  }
448
449  unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
450                  MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG);
451
452  if (Flag.getNode())
453    return DAG.getNode(Opc, dl, MVT::Other, Chain, Flag);
454
455  // Return Void
456  return DAG.getNode(Opc, dl, MVT::Other, Chain);
457}
458
459/// LowerCCCCallTo - functions arguments are copied from virtual regs to
460/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
461/// TODO: sret.
462SDValue
463MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
464                                     CallingConv::ID CallConv, bool isVarArg,
465                                     bool isTailCall,
466                                     const SmallVectorImpl<ISD::OutputArg>
467                                       &Outs,
468                                     const SmallVectorImpl<SDValue> &OutVals,
469                                     const SmallVectorImpl<ISD::InputArg> &Ins,
470                                     DebugLoc dl, SelectionDAG &DAG,
471                                     SmallVectorImpl<SDValue> &InVals) const {
472  // Analyze operands of the call, assigning locations to each operand.
473  SmallVector<CCValAssign, 16> ArgLocs;
474  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
475                 getTargetMachine(), ArgLocs, *DAG.getContext());
476
477  CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
478
479  // Get a count of how many bytes are to be pushed on the stack.
480  unsigned NumBytes = CCInfo.getNextStackOffset();
481
482  Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
483                                                      getPointerTy(), true));
484
485  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
486  SmallVector<SDValue, 12> MemOpChains;
487  SDValue StackPtr;
488
489  // Walk the register/memloc assignments, inserting copies/loads.
490  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
491    CCValAssign &VA = ArgLocs[i];
492
493    SDValue Arg = OutVals[i];
494
495    // Promote the value if needed.
496    switch (VA.getLocInfo()) {
497      default: llvm_unreachable("Unknown loc info!");
498      case CCValAssign::Full: break;
499      case CCValAssign::SExt:
500        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
501        break;
502      case CCValAssign::ZExt:
503        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
504        break;
505      case CCValAssign::AExt:
506        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
507        break;
508    }
509
510    // Arguments that can be passed on register must be kept at RegsToPass
511    // vector
512    if (VA.isRegLoc()) {
513      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
514    } else {
515      assert(VA.isMemLoc());
516
517      if (StackPtr.getNode() == 0)
518        StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
519
520      SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
521                                   StackPtr,
522                                   DAG.getIntPtrConstant(VA.getLocMemOffset()));
523
524      SDValue MemOp;
525      ISD::ArgFlagsTy Flags = Outs[i].Flags;
526
527      if (Flags.isByVal()) {
528        SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i16);
529        MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode,
530                              Flags.getByValAlign(),
531                              /*isVolatile*/false,
532                              /*AlwaysInline=*/true,
533                              MachinePointerInfo(),
534                              MachinePointerInfo());
535      } else {
536        MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo(),
537                             false, false, 0);
538      }
539
540      MemOpChains.push_back(MemOp);
541    }
542  }
543
544  // Transform all store nodes into one single node because all store nodes are
545  // independent of each other.
546  if (!MemOpChains.empty())
547    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
548                        &MemOpChains[0], MemOpChains.size());
549
550  // Build a sequence of copy-to-reg nodes chained together with token chain and
551  // flag operands which copy the outgoing args into registers.  The InFlag in
552  // necessary since all emitted instructions must be stuck together.
553  SDValue InFlag;
554  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
555    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
556                             RegsToPass[i].second, InFlag);
557    InFlag = Chain.getValue(1);
558  }
559
560  // If the callee is a GlobalAddress node (quite common, every direct call is)
561  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
562  // Likewise ExternalSymbol -> TargetExternalSymbol.
563  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
564    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16);
565  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
566    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
567
568  // Returns a chain & a flag for retval copy to use.
569  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
570  SmallVector<SDValue, 8> Ops;
571  Ops.push_back(Chain);
572  Ops.push_back(Callee);
573
574  // Add argument registers to the end of the list so that they are
575  // known live into the call.
576  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
577    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
578                                  RegsToPass[i].second.getValueType()));
579
580  if (InFlag.getNode())
581    Ops.push_back(InFlag);
582
583  Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
584  InFlag = Chain.getValue(1);
585
586  // Create the CALLSEQ_END node.
587  Chain = DAG.getCALLSEQ_END(Chain,
588                             DAG.getConstant(NumBytes, getPointerTy(), true),
589                             DAG.getConstant(0, getPointerTy(), true),
590                             InFlag);
591  InFlag = Chain.getValue(1);
592
593  // Handle result values, copying them out of physregs into vregs that we
594  // return.
595  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
596                         DAG, InVals);
597}
598
599/// LowerCallResult - Lower the result values of a call into the
600/// appropriate copies out of appropriate physical registers.
601///
602SDValue
603MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
604                                      CallingConv::ID CallConv, bool isVarArg,
605                                      const SmallVectorImpl<ISD::InputArg> &Ins,
606                                      DebugLoc dl, SelectionDAG &DAG,
607                                      SmallVectorImpl<SDValue> &InVals) const {
608
609  // Assign locations to each value returned by this call.
610  SmallVector<CCValAssign, 16> RVLocs;
611  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
612                 getTargetMachine(), RVLocs, *DAG.getContext());
613
614  CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430);
615
616  // Copy all of the result registers out of their specified physreg.
617  for (unsigned i = 0; i != RVLocs.size(); ++i) {
618    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
619                               RVLocs[i].getValVT(), InFlag).getValue(1);
620    InFlag = Chain.getValue(2);
621    InVals.push_back(Chain.getValue(0));
622  }
623
624  return Chain;
625}
626
627SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
628                                          SelectionDAG &DAG) const {
629  unsigned Opc = Op.getOpcode();
630  SDNode* N = Op.getNode();
631  EVT VT = Op.getValueType();
632  DebugLoc dl = N->getDebugLoc();
633
634  // Expand non-constant shifts to loops:
635  if (!isa<ConstantSDNode>(N->getOperand(1)))
636    switch (Opc) {
637    default: llvm_unreachable("Invalid shift opcode!");
638    case ISD::SHL:
639      return DAG.getNode(MSP430ISD::SHL, dl,
640                         VT, N->getOperand(0), N->getOperand(1));
641    case ISD::SRA:
642      return DAG.getNode(MSP430ISD::SRA, dl,
643                         VT, N->getOperand(0), N->getOperand(1));
644    case ISD::SRL:
645      return DAG.getNode(MSP430ISD::SRL, dl,
646                         VT, N->getOperand(0), N->getOperand(1));
647    }
648
649  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
650
651  // Expand the stuff into sequence of shifts.
652  // FIXME: for some shift amounts this might be done better!
653  // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
654  SDValue Victim = N->getOperand(0);
655
656  if (Opc == ISD::SRL && ShiftAmount) {
657    // Emit a special goodness here:
658    // srl A, 1 => clrc; rrc A
659    Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
660    ShiftAmount -= 1;
661  }
662
663  while (ShiftAmount--)
664    Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
665                         dl, VT, Victim);
666
667  return Victim;
668}
669
670SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op,
671                                                 SelectionDAG &DAG) const {
672  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
673  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
674
675  // Create the TargetGlobalAddress node, folding in the constant offset.
676  SDValue Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
677                                              getPointerTy(), Offset);
678  return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
679                     getPointerTy(), Result);
680}
681
682SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
683                                                  SelectionDAG &DAG) const {
684  DebugLoc dl = Op.getDebugLoc();
685  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
686  SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
687
688  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);
689}
690
691SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op,
692                                                SelectionDAG &DAG) const {
693  DebugLoc dl = Op.getDebugLoc();
694  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
695  SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy());
696
697  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);
698}
699
700static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
701                       ISD::CondCode CC,
702                       DebugLoc dl, SelectionDAG &DAG) {
703  // FIXME: Handle bittests someday
704  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
705
706  // FIXME: Handle jump negative someday
707  MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
708  switch (CC) {
709  default: llvm_unreachable("Invalid integer condition!");
710  case ISD::SETEQ:
711    TCC = MSP430CC::COND_E;     // aka COND_Z
712    // Minor optimization: if LHS is a constant, swap operands, then the
713    // constant can be folded into comparison.
714    if (LHS.getOpcode() == ISD::Constant)
715      std::swap(LHS, RHS);
716    break;
717  case ISD::SETNE:
718    TCC = MSP430CC::COND_NE;    // aka COND_NZ
719    // Minor optimization: if LHS is a constant, swap operands, then the
720    // constant can be folded into comparison.
721    if (LHS.getOpcode() == ISD::Constant)
722      std::swap(LHS, RHS);
723    break;
724  case ISD::SETULE:
725    std::swap(LHS, RHS);        // FALLTHROUGH
726  case ISD::SETUGE:
727    // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
728    // fold constant into instruction.
729    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
730      LHS = RHS;
731      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
732      TCC = MSP430CC::COND_LO;
733      break;
734    }
735    TCC = MSP430CC::COND_HS;    // aka COND_C
736    break;
737  case ISD::SETUGT:
738    std::swap(LHS, RHS);        // FALLTHROUGH
739  case ISD::SETULT:
740    // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
741    // fold constant into instruction.
742    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
743      LHS = RHS;
744      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
745      TCC = MSP430CC::COND_HS;
746      break;
747    }
748    TCC = MSP430CC::COND_LO;    // aka COND_NC
749    break;
750  case ISD::SETLE:
751    std::swap(LHS, RHS);        // FALLTHROUGH
752  case ISD::SETGE:
753    // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
754    // fold constant into instruction.
755    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
756      LHS = RHS;
757      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
758      TCC = MSP430CC::COND_L;
759      break;
760    }
761    TCC = MSP430CC::COND_GE;
762    break;
763  case ISD::SETGT:
764    std::swap(LHS, RHS);        // FALLTHROUGH
765  case ISD::SETLT:
766    // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
767    // fold constant into instruction.
768    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
769      LHS = RHS;
770      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
771      TCC = MSP430CC::COND_GE;
772      break;
773    }
774    TCC = MSP430CC::COND_L;
775    break;
776  }
777
778  TargetCC = DAG.getConstant(TCC, MVT::i8);
779  return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS);
780}
781
782
783SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
784  SDValue Chain = Op.getOperand(0);
785  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
786  SDValue LHS   = Op.getOperand(2);
787  SDValue RHS   = Op.getOperand(3);
788  SDValue Dest  = Op.getOperand(4);
789  DebugLoc dl   = Op.getDebugLoc();
790
791  SDValue TargetCC;
792  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
793
794  return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
795                     Chain, Dest, TargetCC, Flag);
796}
797
798SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
799  SDValue LHS   = Op.getOperand(0);
800  SDValue RHS   = Op.getOperand(1);
801  DebugLoc dl   = Op.getDebugLoc();
802
803  // If we are doing an AND and testing against zero, then the CMP
804  // will not be generated.  The AND (or BIT) will generate the condition codes,
805  // but they are different from CMP.
806  // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
807  // lowering & isel wouldn't diverge.
808  bool andCC = false;
809  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
810    if (RHSC->isNullValue() && LHS.hasOneUse() &&
811        (LHS.getOpcode() == ISD::AND ||
812         (LHS.getOpcode() == ISD::TRUNCATE &&
813          LHS.getOperand(0).getOpcode() == ISD::AND))) {
814      andCC = true;
815    }
816  }
817  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
818  SDValue TargetCC;
819  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
820
821  // Get the condition codes directly from the status register, if its easy.
822  // Otherwise a branch will be generated.  Note that the AND and BIT
823  // instructions generate different flags than CMP, the carry bit can be used
824  // for NE/EQ.
825  bool Invert = false;
826  bool Shift = false;
827  bool Convert = true;
828  switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
829   default:
830    Convert = false;
831    break;
832   case MSP430CC::COND_HS:
833     // Res = SRW & 1, no processing is required
834     break;
835   case MSP430CC::COND_LO:
836     // Res = ~(SRW & 1)
837     Invert = true;
838     break;
839   case MSP430CC::COND_NE:
840     if (andCC) {
841       // C = ~Z, thus Res = SRW & 1, no processing is required
842     } else {
843       // Res = ~((SRW >> 1) & 1)
844       Shift = true;
845       Invert = true;
846     }
847     break;
848   case MSP430CC::COND_E:
849     Shift = true;
850     // C = ~Z for AND instruction, thus we can put Res = ~(SRW & 1), however,
851     // Res = (SRW >> 1) & 1 is 1 word shorter.
852     break;
853  }
854  EVT VT = Op.getValueType();
855  SDValue One  = DAG.getConstant(1, VT);
856  if (Convert) {
857    SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SRW,
858                                    MVT::i16, Flag);
859    if (Shift)
860      // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
861      SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
862    SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
863    if (Invert)
864      SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
865    return SR;
866  } else {
867    SDValue Zero = DAG.getConstant(0, VT);
868    SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
869    SmallVector<SDValue, 4> Ops;
870    Ops.push_back(One);
871    Ops.push_back(Zero);
872    Ops.push_back(TargetCC);
873    Ops.push_back(Flag);
874    return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
875  }
876}
877
878SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op,
879                                             SelectionDAG &DAG) const {
880  SDValue LHS    = Op.getOperand(0);
881  SDValue RHS    = Op.getOperand(1);
882  SDValue TrueV  = Op.getOperand(2);
883  SDValue FalseV = Op.getOperand(3);
884  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
885  DebugLoc dl    = Op.getDebugLoc();
886
887  SDValue TargetCC;
888  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
889
890  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
891  SmallVector<SDValue, 4> Ops;
892  Ops.push_back(TrueV);
893  Ops.push_back(FalseV);
894  Ops.push_back(TargetCC);
895  Ops.push_back(Flag);
896
897  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
898}
899
900SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
901                                               SelectionDAG &DAG) const {
902  SDValue Val = Op.getOperand(0);
903  EVT VT      = Op.getValueType();
904  DebugLoc dl = Op.getDebugLoc();
905
906  assert(VT == MVT::i16 && "Only support i16 for now!");
907
908  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
909                     DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
910                     DAG.getValueType(Val.getValueType()));
911}
912
913SDValue
914MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
915  MachineFunction &MF = DAG.getMachineFunction();
916  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
917  int ReturnAddrIndex = FuncInfo->getRAIndex();
918
919  if (ReturnAddrIndex == 0) {
920    // Set up a frame object for the return address.
921    uint64_t SlotSize = TD->getPointerSize();
922    ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
923                                                           true);
924    FuncInfo->setRAIndex(ReturnAddrIndex);
925  }
926
927  return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
928}
929
930SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op,
931                                              SelectionDAG &DAG) const {
932  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
933  MFI->setReturnAddressIsTaken(true);
934
935  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
936  DebugLoc dl = Op.getDebugLoc();
937
938  if (Depth > 0) {
939    SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
940    SDValue Offset =
941      DAG.getConstant(TD->getPointerSize(), MVT::i16);
942    return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
943                       DAG.getNode(ISD::ADD, dl, getPointerTy(),
944                                   FrameAddr, Offset),
945                       MachinePointerInfo(), false, false, false, 0);
946  }
947
948  // Just load the return address.
949  SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
950  return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
951                     RetAddrFI, MachinePointerInfo(), false, false, false, 0);
952}
953
954SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op,
955                                             SelectionDAG &DAG) const {
956  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
957  MFI->setFrameAddressIsTaken(true);
958
959  EVT VT = Op.getValueType();
960  DebugLoc dl = Op.getDebugLoc();  // FIXME probably not meaningful
961  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
962  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
963                                         MSP430::FPW, VT);
964  while (Depth--)
965    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
966                            MachinePointerInfo(),
967                            false, false, false, 0);
968  return FrameAddr;
969}
970
971SDValue MSP430TargetLowering::LowerVASTART(SDValue Op,
972                                           SelectionDAG &DAG) const {
973  MachineFunction &MF = DAG.getMachineFunction();
974  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
975
976  // Frame index of first vararg argument
977  SDValue FrameIndex = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
978                                         getPointerTy());
979  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
980
981  // Create a store of the frame index to the location operand
982  return DAG.getStore(Op.getOperand(0), Op.getDebugLoc(), FrameIndex,
983                      Op.getOperand(1), MachinePointerInfo(SV),
984                      false, false, 0);
985}
986
987/// getPostIndexedAddressParts - returns true by value, base pointer and
988/// offset pointer and addressing mode by reference if this node can be
989/// combined with a load / store to form a post-indexed load / store.
990bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
991                                                      SDValue &Base,
992                                                      SDValue &Offset,
993                                                      ISD::MemIndexedMode &AM,
994                                                      SelectionDAG &DAG) const {
995
996  LoadSDNode *LD = cast<LoadSDNode>(N);
997  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
998    return false;
999
1000  EVT VT = LD->getMemoryVT();
1001  if (VT != MVT::i8 && VT != MVT::i16)
1002    return false;
1003
1004  if (Op->getOpcode() != ISD::ADD)
1005    return false;
1006
1007  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
1008    uint64_t RHSC = RHS->getZExtValue();
1009    if ((VT == MVT::i16 && RHSC != 2) ||
1010        (VT == MVT::i8 && RHSC != 1))
1011      return false;
1012
1013    Base = Op->getOperand(0);
1014    Offset = DAG.getConstant(RHSC, VT);
1015    AM = ISD::POST_INC;
1016    return true;
1017  }
1018
1019  return false;
1020}
1021
1022
1023const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
1024  switch (Opcode) {
1025  default: return NULL;
1026  case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
1027  case MSP430ISD::RETI_FLAG:          return "MSP430ISD::RETI_FLAG";
1028  case MSP430ISD::RRA:                return "MSP430ISD::RRA";
1029  case MSP430ISD::RLA:                return "MSP430ISD::RLA";
1030  case MSP430ISD::RRC:                return "MSP430ISD::RRC";
1031  case MSP430ISD::CALL:               return "MSP430ISD::CALL";
1032  case MSP430ISD::Wrapper:            return "MSP430ISD::Wrapper";
1033  case MSP430ISD::BR_CC:              return "MSP430ISD::BR_CC";
1034  case MSP430ISD::CMP:                return "MSP430ISD::CMP";
1035  case MSP430ISD::SELECT_CC:          return "MSP430ISD::SELECT_CC";
1036  case MSP430ISD::SHL:                return "MSP430ISD::SHL";
1037  case MSP430ISD::SRA:                return "MSP430ISD::SRA";
1038  }
1039}
1040
1041bool MSP430TargetLowering::isTruncateFree(Type *Ty1,
1042                                          Type *Ty2) const {
1043  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
1044    return false;
1045
1046  return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
1047}
1048
1049bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1050  if (!VT1.isInteger() || !VT2.isInteger())
1051    return false;
1052
1053  return (VT1.getSizeInBits() > VT2.getSizeInBits());
1054}
1055
1056bool MSP430TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
1057  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1058  return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
1059}
1060
1061bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
1062  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1063  return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
1064}
1065
1066bool MSP430TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
1067  return isZExtFree(Val.getValueType(), VT2);
1068}
1069
1070//===----------------------------------------------------------------------===//
1071//  Other Lowering Code
1072//===----------------------------------------------------------------------===//
1073
1074MachineBasicBlock*
1075MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,
1076                                     MachineBasicBlock *BB) const {
1077  MachineFunction *F = BB->getParent();
1078  MachineRegisterInfo &RI = F->getRegInfo();
1079  DebugLoc dl = MI->getDebugLoc();
1080  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1081
1082  unsigned Opc;
1083  const TargetRegisterClass * RC;
1084  switch (MI->getOpcode()) {
1085  default: llvm_unreachable("Invalid shift opcode!");
1086  case MSP430::Shl8:
1087   Opc = MSP430::SHL8r1;
1088   RC = &MSP430::GR8RegClass;
1089   break;
1090  case MSP430::Shl16:
1091   Opc = MSP430::SHL16r1;
1092   RC = &MSP430::GR16RegClass;
1093   break;
1094  case MSP430::Sra8:
1095   Opc = MSP430::SAR8r1;
1096   RC = &MSP430::GR8RegClass;
1097   break;
1098  case MSP430::Sra16:
1099   Opc = MSP430::SAR16r1;
1100   RC = &MSP430::GR16RegClass;
1101   break;
1102  case MSP430::Srl8:
1103   Opc = MSP430::SAR8r1c;
1104   RC = &MSP430::GR8RegClass;
1105   break;
1106  case MSP430::Srl16:
1107   Opc = MSP430::SAR16r1c;
1108   RC = &MSP430::GR16RegClass;
1109   break;
1110  }
1111
1112  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1113  MachineFunction::iterator I = BB;
1114  ++I;
1115
1116  // Create loop block
1117  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1118  MachineBasicBlock *RemBB  = F->CreateMachineBasicBlock(LLVM_BB);
1119
1120  F->insert(I, LoopBB);
1121  F->insert(I, RemBB);
1122
1123  // Update machine-CFG edges by transferring all successors of the current
1124  // block to the block containing instructions after shift.
1125  RemBB->splice(RemBB->begin(), BB,
1126                llvm::next(MachineBasicBlock::iterator(MI)),
1127                BB->end());
1128  RemBB->transferSuccessorsAndUpdatePHIs(BB);
1129
1130  // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1131  BB->addSuccessor(LoopBB);
1132  BB->addSuccessor(RemBB);
1133  LoopBB->addSuccessor(RemBB);
1134  LoopBB->addSuccessor(LoopBB);
1135
1136  unsigned ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass);
1137  unsigned ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass);
1138  unsigned ShiftReg = RI.createVirtualRegister(RC);
1139  unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1140  unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg();
1141  unsigned SrcReg = MI->getOperand(1).getReg();
1142  unsigned DstReg = MI->getOperand(0).getReg();
1143
1144  // BB:
1145  // cmp 0, N
1146  // je RemBB
1147  BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1148    .addReg(ShiftAmtSrcReg).addImm(0);
1149  BuildMI(BB, dl, TII.get(MSP430::JCC))
1150    .addMBB(RemBB)
1151    .addImm(MSP430CC::COND_E);
1152
1153  // LoopBB:
1154  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1155  // ShiftAmt = phi [%N, BB],      [%ShiftAmt2, LoopBB]
1156  // ShiftReg2 = shift ShiftReg
1157  // ShiftAmt2 = ShiftAmt - 1;
1158  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1159    .addReg(SrcReg).addMBB(BB)
1160    .addReg(ShiftReg2).addMBB(LoopBB);
1161  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1162    .addReg(ShiftAmtSrcReg).addMBB(BB)
1163    .addReg(ShiftAmtReg2).addMBB(LoopBB);
1164  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1165    .addReg(ShiftReg);
1166  BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1167    .addReg(ShiftAmtReg).addImm(1);
1168  BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1169    .addMBB(LoopBB)
1170    .addImm(MSP430CC::COND_NE);
1171
1172  // RemBB:
1173  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1174  BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1175    .addReg(SrcReg).addMBB(BB)
1176    .addReg(ShiftReg2).addMBB(LoopBB);
1177
1178  MI->eraseFromParent();   // The pseudo instruction is gone now.
1179  return RemBB;
1180}
1181
1182MachineBasicBlock*
1183MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1184                                                  MachineBasicBlock *BB) const {
1185  unsigned Opc = MI->getOpcode();
1186
1187  if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1188      Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1189      Opc == MSP430::Srl8 || Opc == MSP430::Srl16)
1190    return EmitShiftInstr(MI, BB);
1191
1192  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1193  DebugLoc dl = MI->getDebugLoc();
1194
1195  assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1196         "Unexpected instr type to insert");
1197
1198  // To "insert" a SELECT instruction, we actually have to insert the diamond
1199  // control-flow pattern.  The incoming instruction knows the destination vreg
1200  // to set, the condition code register to branch on, the true/false values to
1201  // select between, and a branch opcode to use.
1202  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1203  MachineFunction::iterator I = BB;
1204  ++I;
1205
1206  //  thisMBB:
1207  //  ...
1208  //   TrueVal = ...
1209  //   cmpTY ccX, r1, r2
1210  //   jCC copy1MBB
1211  //   fallthrough --> copy0MBB
1212  MachineBasicBlock *thisMBB = BB;
1213  MachineFunction *F = BB->getParent();
1214  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1215  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1216  F->insert(I, copy0MBB);
1217  F->insert(I, copy1MBB);
1218  // Update machine-CFG edges by transferring all successors of the current
1219  // block to the new block which will contain the Phi node for the select.
1220  copy1MBB->splice(copy1MBB->begin(), BB,
1221                   llvm::next(MachineBasicBlock::iterator(MI)),
1222                   BB->end());
1223  copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
1224  // Next, add the true and fallthrough blocks as its successors.
1225  BB->addSuccessor(copy0MBB);
1226  BB->addSuccessor(copy1MBB);
1227
1228  BuildMI(BB, dl, TII.get(MSP430::JCC))
1229    .addMBB(copy1MBB)
1230    .addImm(MI->getOperand(3).getImm());
1231
1232  //  copy0MBB:
1233  //   %FalseValue = ...
1234  //   # fallthrough to copy1MBB
1235  BB = copy0MBB;
1236
1237  // Update machine-CFG edges
1238  BB->addSuccessor(copy1MBB);
1239
1240  //  copy1MBB:
1241  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1242  //  ...
1243  BB = copy1MBB;
1244  BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI),
1245          MI->getOperand(0).getReg())
1246    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1247    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1248
1249  MI->eraseFromParent();   // The pseudo instruction is gone now.
1250  return BB;
1251}
1252