MSP430ISelLowering.cpp revision c9403659a98bf6487ab6fbf40b81628b5695c02e 
1//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation  ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the MSP430TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "msp430-lower"
15
16#include "MSP430ISelLowering.h"
17#include "MSP430.h"
18#include "MSP430MachineFunctionInfo.h"
19#include "MSP430TargetMachine.h"
20#include "MSP430Subtarget.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
23#include "llvm/Intrinsics.h"
24#include "llvm/CallingConv.h"
25#include "llvm/GlobalVariable.h"
26#include "llvm/GlobalAlias.h"
27#include "llvm/CodeGen/CallingConvLower.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/PseudoSourceValue.h"
33#include "llvm/CodeGen/SelectionDAGISel.h"
34#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
35#include "llvm/CodeGen/ValueTypes.h"
36#include "llvm/Support/CommandLine.h"
37#include "llvm/Support/Debug.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/raw_ostream.h"
40#include "llvm/ADT/VectorExtras.h"
41using namespace llvm;
42
43typedef enum {
44  NoHWMult,
45  HWMultIntr,
46  HWMultNoIntr
47} HWMultUseMode;
48
49static cl::opt<HWMultUseMode>
50HWMultMode("msp430-hwmult-mode",
51           cl::desc("Hardware multiplier use mode"),
52           cl::init(HWMultNoIntr),
53           cl::values(
54             clEnumValN(NoHWMult, "no",
55                "Do not use hardware multiplier"),
56             clEnumValN(HWMultIntr, "interrupts",
57                "Assume hardware multiplier can be used inside interrupts"),
58             clEnumValN(HWMultNoIntr, "use",
59                "Assume hardware multiplier cannot be used inside interrupts"),
60             clEnumValEnd));
61
62MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
63  TargetLowering(tm, new TargetLoweringObjectFileELF()),
64  Subtarget(*tm.getSubtargetImpl()), TM(tm) {
65
66  TD = getTargetData();
67
68  // Set up the register classes.
69  addRegisterClass(MVT::i8,  MSP430::GR8RegisterClass);
70  addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
71
72  // Compute derived properties from the register classes
73  computeRegisterProperties();
74
75  // Provide all sorts of operation actions
76
77  // Division is expensive
78  setIntDivIsCheap(false);
79
80  // Even if we have only 1 bit shift here, we can perform
81  // shifts of the whole bitwidth 1 bit per step.
82  setShiftAmountType(MVT::i8);
83
84  setStackPointerRegisterToSaveRestore(MSP430::SPW);
85  setBooleanContents(ZeroOrOneBooleanContent);
86  setSchedulingPreference(Sched::Latency);
87
88  // We have post-incremented loads / stores.
89  setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
90  setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
91
92  setLoadExtAction(ISD::EXTLOAD,  MVT::i1,  Promote);
93  setLoadExtAction(ISD::SEXTLOAD, MVT::i1,  Promote);
94  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1,  Promote);
95  setLoadExtAction(ISD::SEXTLOAD, MVT::i8,  Expand);
96  setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
97
98  // We don't have any truncstores
99  setTruncStoreAction(MVT::i16, MVT::i8, Expand);
100
101  setOperationAction(ISD::SRA,              MVT::i8,    Custom);
102  setOperationAction(ISD::SHL,              MVT::i8,    Custom);
103  setOperationAction(ISD::SRL,              MVT::i8,    Custom);
104  setOperationAction(ISD::SRA,              MVT::i16,   Custom);
105  setOperationAction(ISD::SHL,              MVT::i16,   Custom);
106  setOperationAction(ISD::SRL,              MVT::i16,   Custom);
107  setOperationAction(ISD::ROTL,             MVT::i8,    Expand);
108  setOperationAction(ISD::ROTR,             MVT::i8,    Expand);
109  setOperationAction(ISD::ROTL,             MVT::i16,   Expand);
110  setOperationAction(ISD::ROTR,             MVT::i16,   Expand);
111  setOperationAction(ISD::GlobalAddress,    MVT::i16,   Custom);
112  setOperationAction(ISD::ExternalSymbol,   MVT::i16,   Custom);
113  setOperationAction(ISD::BlockAddress,     MVT::i16,   Custom);
114  setOperationAction(ISD::BR_JT,            MVT::Other, Expand);
115  setOperationAction(ISD::BR_CC,            MVT::i8,    Custom);
116  setOperationAction(ISD::BR_CC,            MVT::i16,   Custom);
117  setOperationAction(ISD::BRCOND,           MVT::Other, Expand);
118  setOperationAction(ISD::SETCC,            MVT::i8,    Custom);
119  setOperationAction(ISD::SETCC,            MVT::i16,   Custom);
120  setOperationAction(ISD::SELECT,           MVT::i8,    Expand);
121  setOperationAction(ISD::SELECT,           MVT::i16,   Expand);
122  setOperationAction(ISD::SELECT_CC,        MVT::i8,    Custom);
123  setOperationAction(ISD::SELECT_CC,        MVT::i16,   Custom);
124  setOperationAction(ISD::SIGN_EXTEND,      MVT::i16,   Custom);
125  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
126  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
127
128  setOperationAction(ISD::CTTZ,             MVT::i8,    Expand);
129  setOperationAction(ISD::CTTZ,             MVT::i16,   Expand);
130  setOperationAction(ISD::CTLZ,             MVT::i8,    Expand);
131  setOperationAction(ISD::CTLZ,             MVT::i16,   Expand);
132  setOperationAction(ISD::CTPOP,            MVT::i8,    Expand);
133  setOperationAction(ISD::CTPOP,            MVT::i16,   Expand);
134
135  setOperationAction(ISD::SHL_PARTS,        MVT::i8,    Expand);
136  setOperationAction(ISD::SHL_PARTS,        MVT::i16,   Expand);
137  setOperationAction(ISD::SRL_PARTS,        MVT::i8,    Expand);
138  setOperationAction(ISD::SRL_PARTS,        MVT::i16,   Expand);
139  setOperationAction(ISD::SRA_PARTS,        MVT::i8,    Expand);
140  setOperationAction(ISD::SRA_PARTS,        MVT::i16,   Expand);
141
142  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1,   Expand);
143
144  // FIXME: Implement efficiently multiplication by a constant
145  setOperationAction(ISD::MUL,              MVT::i8,    Expand);
146  setOperationAction(ISD::MULHS,            MVT::i8,    Expand);
147  setOperationAction(ISD::MULHU,            MVT::i8,    Expand);
148  setOperationAction(ISD::SMUL_LOHI,        MVT::i8,    Expand);
149  setOperationAction(ISD::UMUL_LOHI,        MVT::i8,    Expand);
150  setOperationAction(ISD::MUL,              MVT::i16,   Expand);
151  setOperationAction(ISD::MULHS,            MVT::i16,   Expand);
152  setOperationAction(ISD::MULHU,            MVT::i16,   Expand);
153  setOperationAction(ISD::SMUL_LOHI,        MVT::i16,   Expand);
154  setOperationAction(ISD::UMUL_LOHI,        MVT::i16,   Expand);
155
156  setOperationAction(ISD::UDIV,             MVT::i8,    Expand);
157  setOperationAction(ISD::UDIVREM,          MVT::i8,    Expand);
158  setOperationAction(ISD::UREM,             MVT::i8,    Expand);
159  setOperationAction(ISD::SDIV,             MVT::i8,    Expand);
160  setOperationAction(ISD::SDIVREM,          MVT::i8,    Expand);
161  setOperationAction(ISD::SREM,             MVT::i8,    Expand);
162  setOperationAction(ISD::UDIV,             MVT::i16,   Expand);
163  setOperationAction(ISD::UDIVREM,          MVT::i16,   Expand);
164  setOperationAction(ISD::UREM,             MVT::i16,   Expand);
165  setOperationAction(ISD::SDIV,             MVT::i16,   Expand);
166  setOperationAction(ISD::SDIVREM,          MVT::i16,   Expand);
167  setOperationAction(ISD::SREM,             MVT::i16,   Expand);
168
169  // Libcalls names.
170  if (HWMultMode == HWMultIntr) {
171    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw");
172    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw");
173  } else if (HWMultMode == HWMultNoIntr) {
174    setLibcallName(RTLIB::MUL_I8,  "__mulqi3hw_noint");
175    setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint");
176  }
177}
178
179SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
180                                             SelectionDAG &DAG) const {
181  switch (Op.getOpcode()) {
182  case ISD::SHL: // FALLTHROUGH
183  case ISD::SRL:
184  case ISD::SRA:              return LowerShifts(Op, DAG);
185  case ISD::GlobalAddress:    return LowerGlobalAddress(Op, DAG);
186  case ISD::BlockAddress:     return LowerBlockAddress(Op, DAG);
187  case ISD::ExternalSymbol:   return LowerExternalSymbol(Op, DAG);
188  case ISD::SETCC:            return LowerSETCC(Op, DAG);
189  case ISD::BR_CC:            return LowerBR_CC(Op, DAG);
190  case ISD::SELECT_CC:        return LowerSELECT_CC(Op, DAG);
191  case ISD::SIGN_EXTEND:      return LowerSIGN_EXTEND(Op, DAG);
192  case ISD::RETURNADDR:       return LowerRETURNADDR(Op, DAG);
193  case ISD::FRAMEADDR:        return LowerFRAMEADDR(Op, DAG);
194  default:
195    llvm_unreachable("unimplemented operand");
196    return SDValue();
197  }
198}
199
200/// getFunctionAlignment - Return the Log2 alignment of this function.
201unsigned MSP430TargetLowering::getFunctionAlignment(const Function *F) const {
202  return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 2;
203}
204
205//===----------------------------------------------------------------------===//
206//                       MSP430 Inline Assembly Support
207//===----------------------------------------------------------------------===//
208
209/// getConstraintType - Given a constraint letter, return the type of
210/// constraint it is for this target.
211TargetLowering::ConstraintType
212MSP430TargetLowering::getConstraintType(const std::string &Constraint) const {
213  if (Constraint.size() == 1) {
214    switch (Constraint[0]) {
215    case 'r':
216      return C_RegisterClass;
217    default:
218      break;
219    }
220  }
221  return TargetLowering::getConstraintType(Constraint);
222}
223
224std::pair<unsigned, const TargetRegisterClass*>
225MSP430TargetLowering::
226getRegForInlineAsmConstraint(const std::string &Constraint,
227                             EVT VT) const {
228  if (Constraint.size() == 1) {
229    // GCC Constraint Letters
230    switch (Constraint[0]) {
231    default: break;
232    case 'r':   // GENERAL_REGS
233      if (VT == MVT::i8)
234        return std::make_pair(0U, MSP430::GR8RegisterClass);
235
236      return std::make_pair(0U, MSP430::GR16RegisterClass);
237    }
238  }
239
240  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
241}
242
243//===----------------------------------------------------------------------===//
244//                      Calling Convention Implementation
245//===----------------------------------------------------------------------===//
246
247#include "MSP430GenCallingConv.inc"
248
249SDValue
250MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
251                                           CallingConv::ID CallConv,
252                                           bool isVarArg,
253                                           const SmallVectorImpl<ISD::InputArg>
254                                             &Ins,
255                                           DebugLoc dl,
256                                           SelectionDAG &DAG,
257                                           SmallVectorImpl<SDValue> &InVals)
258                                             const {
259
260  switch (CallConv) {
261  default:
262    llvm_unreachable("Unsupported calling convention");
263  case CallingConv::C:
264  case CallingConv::Fast:
265    return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
266  case CallingConv::MSP430_INTR:
267   if (Ins.empty())
268     return Chain;
269   else {
270    report_fatal_error("ISRs cannot have arguments");
271    return SDValue();
272   }
273  }
274}
275
276SDValue
277MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
278                                CallingConv::ID CallConv, bool isVarArg,
279                                bool &isTailCall,
280                                const SmallVectorImpl<ISD::OutputArg> &Outs,
281                                const SmallVectorImpl<SDValue> &OutVals,
282                                const SmallVectorImpl<ISD::InputArg> &Ins,
283                                DebugLoc dl, SelectionDAG &DAG,
284                                SmallVectorImpl<SDValue> &InVals) const {
285  // MSP430 target does not yet support tail call optimization.
286  isTailCall = false;
287
288  switch (CallConv) {
289  default:
290    llvm_unreachable("Unsupported calling convention");
291  case CallingConv::Fast:
292  case CallingConv::C:
293    return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
294                          Outs, OutVals, Ins, dl, DAG, InVals);
295  case CallingConv::MSP430_INTR:
296    report_fatal_error("ISRs cannot be called directly");
297    return SDValue();
298  }
299}
300
301/// LowerCCCArguments - transform physical registers into virtual registers and
302/// generate load operations for arguments places on the stack.
303// FIXME: struct return stuff
304// FIXME: varargs
305SDValue
306MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
307                                        CallingConv::ID CallConv,
308                                        bool isVarArg,
309                                        const SmallVectorImpl<ISD::InputArg>
310                                          &Ins,
311                                        DebugLoc dl,
312                                        SelectionDAG &DAG,
313                                        SmallVectorImpl<SDValue> &InVals)
314                                          const {
315  MachineFunction &MF = DAG.getMachineFunction();
316  MachineFrameInfo *MFI = MF.getFrameInfo();
317  MachineRegisterInfo &RegInfo = MF.getRegInfo();
318
319  // Assign locations to all of the incoming arguments.
320  SmallVector<CCValAssign, 16> ArgLocs;
321  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
322                 ArgLocs, *DAG.getContext());
323  CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
324
325  assert(!isVarArg && "Varargs not supported yet");
326
327  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
328    CCValAssign &VA = ArgLocs[i];
329    if (VA.isRegLoc()) {
330      // Arguments passed in registers
331      EVT RegVT = VA.getLocVT();
332      switch (RegVT.getSimpleVT().SimpleTy) {
333      default:
334        {
335#ifndef NDEBUG
336          errs() << "LowerFormalArguments Unhandled argument type: "
337               << RegVT.getSimpleVT().SimpleTy << "\n";
338#endif
339          llvm_unreachable(0);
340        }
341      case MVT::i16:
342        unsigned VReg =
343          RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
344        RegInfo.addLiveIn(VA.getLocReg(), VReg);
345        SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
346
347        // If this is an 8-bit value, it is really passed promoted to 16
348        // bits. Insert an assert[sz]ext to capture this, then truncate to the
349        // right size.
350        if (VA.getLocInfo() == CCValAssign::SExt)
351          ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
352                                 DAG.getValueType(VA.getValVT()));
353        else if (VA.getLocInfo() == CCValAssign::ZExt)
354          ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
355                                 DAG.getValueType(VA.getValVT()));
356
357        if (VA.getLocInfo() != CCValAssign::Full)
358          ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
359
360        InVals.push_back(ArgValue);
361      }
362    } else {
363      // Sanity check
364      assert(VA.isMemLoc());
365      // Load the argument to a virtual register
366      unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
367      if (ObjSize > 2) {
368        errs() << "LowerFormalArguments Unhandled argument type: "
369             << VA.getLocVT().getSimpleVT().SimpleTy
370             << "\n";
371      }
372      // Create the frame index object for this incoming parameter...
373      int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
374
375      // Create the SelectionDAG nodes corresponding to a load
376      //from this parameter
377      SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
378      InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
379                                   PseudoSourceValue::getFixedStack(FI), 0,
380                                   false, false, 0));
381    }
382  }
383
384  return Chain;
385}
386
387SDValue
388MSP430TargetLowering::LowerReturn(SDValue Chain,
389                                  CallingConv::ID CallConv, bool isVarArg,
390                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
391                                  const SmallVectorImpl<SDValue> &OutVals,
392                                  DebugLoc dl, SelectionDAG &DAG) const {
393
394  // CCValAssign - represent the assignment of the return value to a location
395  SmallVector<CCValAssign, 16> RVLocs;
396
397  // ISRs cannot return any value.
398  if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) {
399    report_fatal_error("ISRs cannot return any value");
400    return SDValue();
401  }
402
403  // CCState - Info about the registers and stack slot.
404  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
405                 RVLocs, *DAG.getContext());
406
407  // Analize return values.
408  CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
409
410  // If this is the first return lowered for this function, add the regs to the
411  // liveout set for the function.
412  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
413    for (unsigned i = 0; i != RVLocs.size(); ++i)
414      if (RVLocs[i].isRegLoc())
415        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
416  }
417
418  SDValue Flag;
419
420  // Copy the result values into the output registers.
421  for (unsigned i = 0; i != RVLocs.size(); ++i) {
422    CCValAssign &VA = RVLocs[i];
423    assert(VA.isRegLoc() && "Can only return in registers!");
424
425    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
426                             OutVals[i], Flag);
427
428    // Guarantee that all emitted copies are stuck together,
429    // avoiding something bad.
430    Flag = Chain.getValue(1);
431  }
432
433  unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
434                  MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG);
435
436  if (Flag.getNode())
437    return DAG.getNode(Opc, dl, MVT::Other, Chain, Flag);
438
439  // Return Void
440  return DAG.getNode(Opc, dl, MVT::Other, Chain);
441}
442
443/// LowerCCCCallTo - functions arguments are copied from virtual regs to
444/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
445/// TODO: sret.
446SDValue
447MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
448                                     CallingConv::ID CallConv, bool isVarArg,
449                                     bool isTailCall,
450                                     const SmallVectorImpl<ISD::OutputArg>
451                                       &Outs,
452                                     const SmallVectorImpl<SDValue> &OutVals,
453                                     const SmallVectorImpl<ISD::InputArg> &Ins,
454                                     DebugLoc dl, SelectionDAG &DAG,
455                                     SmallVectorImpl<SDValue> &InVals) const {
456  // Analyze operands of the call, assigning locations to each operand.
457  SmallVector<CCValAssign, 16> ArgLocs;
458  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
459                 ArgLocs, *DAG.getContext());
460
461  CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
462
463  // Get a count of how many bytes are to be pushed on the stack.
464  unsigned NumBytes = CCInfo.getNextStackOffset();
465
466  Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
467                                                      getPointerTy(), true));
468
469  SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
470  SmallVector<SDValue, 12> MemOpChains;
471  SDValue StackPtr;
472
473  // Walk the register/memloc assignments, inserting copies/loads.
474  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
475    CCValAssign &VA = ArgLocs[i];
476
477    SDValue Arg = OutVals[i];
478
479    // Promote the value if needed.
480    switch (VA.getLocInfo()) {
481      default: llvm_unreachable("Unknown loc info!");
482      case CCValAssign::Full: break;
483      case CCValAssign::SExt:
484        Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
485        break;
486      case CCValAssign::ZExt:
487        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
488        break;
489      case CCValAssign::AExt:
490        Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
491        break;
492    }
493
494    // Arguments that can be passed on register must be kept at RegsToPass
495    // vector
496    if (VA.isRegLoc()) {
497      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
498    } else {
499      assert(VA.isMemLoc());
500
501      if (StackPtr.getNode() == 0)
502        StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
503
504      SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
505                                   StackPtr,
506                                   DAG.getIntPtrConstant(VA.getLocMemOffset()));
507
508
509      MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
510                                         PseudoSourceValue::getStack(),
511                                         VA.getLocMemOffset(), false, false, 0));
512    }
513  }
514
515  // Transform all store nodes into one single node because all store nodes are
516  // independent of each other.
517  if (!MemOpChains.empty())
518    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
519                        &MemOpChains[0], MemOpChains.size());
520
521  // Build a sequence of copy-to-reg nodes chained together with token chain and
522  // flag operands which copy the outgoing args into registers.  The InFlag in
523  // necessary since all emited instructions must be stuck together.
524  SDValue InFlag;
525  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
526    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
527                             RegsToPass[i].second, InFlag);
528    InFlag = Chain.getValue(1);
529  }
530
531  // If the callee is a GlobalAddress node (quite common, every direct call is)
532  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
533  // Likewise ExternalSymbol -> TargetExternalSymbol.
534  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
535    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16);
536  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
537    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
538
539  // Returns a chain & a flag for retval copy to use.
540  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
541  SmallVector<SDValue, 8> Ops;
542  Ops.push_back(Chain);
543  Ops.push_back(Callee);
544
545  // Add argument registers to the end of the list so that they are
546  // known live into the call.
547  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
548    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
549                                  RegsToPass[i].second.getValueType()));
550
551  if (InFlag.getNode())
552    Ops.push_back(InFlag);
553
554  Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
555  InFlag = Chain.getValue(1);
556
557  // Create the CALLSEQ_END node.
558  Chain = DAG.getCALLSEQ_END(Chain,
559                             DAG.getConstant(NumBytes, getPointerTy(), true),
560                             DAG.getConstant(0, getPointerTy(), true),
561                             InFlag);
562  InFlag = Chain.getValue(1);
563
564  // Handle result values, copying them out of physregs into vregs that we
565  // return.
566  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
567                         DAG, InVals);
568}
569
570/// LowerCallResult - Lower the result values of a call into the
571/// appropriate copies out of appropriate physical registers.
572///
573SDValue
574MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
575                                      CallingConv::ID CallConv, bool isVarArg,
576                                      const SmallVectorImpl<ISD::InputArg> &Ins,
577                                      DebugLoc dl, SelectionDAG &DAG,
578                                      SmallVectorImpl<SDValue> &InVals) const {
579
580  // Assign locations to each value returned by this call.
581  SmallVector<CCValAssign, 16> RVLocs;
582  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
583                 RVLocs, *DAG.getContext());
584
585  CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430);
586
587  // Copy all of the result registers out of their specified physreg.
588  for (unsigned i = 0; i != RVLocs.size(); ++i) {
589    Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
590                               RVLocs[i].getValVT(), InFlag).getValue(1);
591    InFlag = Chain.getValue(2);
592    InVals.push_back(Chain.getValue(0));
593  }
594
595  return Chain;
596}
597
598SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
599                                          SelectionDAG &DAG) const {
600  unsigned Opc = Op.getOpcode();
601  SDNode* N = Op.getNode();
602  EVT VT = Op.getValueType();
603  DebugLoc dl = N->getDebugLoc();
604
605  // Expand non-constant shifts to loops:
606  if (!isa<ConstantSDNode>(N->getOperand(1)))
607    switch (Opc) {
608    default:
609      assert(0 && "Invalid shift opcode!");
610    case ISD::SHL:
611      return DAG.getNode(MSP430ISD::SHL, dl,
612                         VT, N->getOperand(0), N->getOperand(1));
613    case ISD::SRA:
614      return DAG.getNode(MSP430ISD::SRA, dl,
615                         VT, N->getOperand(0), N->getOperand(1));
616    case ISD::SRL:
617      return DAG.getNode(MSP430ISD::SRL, dl,
618                         VT, N->getOperand(0), N->getOperand(1));
619    }
620
621  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
622
623  // Expand the stuff into sequence of shifts.
624  // FIXME: for some shift amounts this might be done better!
625  // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
626  SDValue Victim = N->getOperand(0);
627
628  if (Opc == ISD::SRL && ShiftAmount) {
629    // Emit a special goodness here:
630    // srl A, 1 => clrc; rrc A
631    Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
632    ShiftAmount -= 1;
633  }
634
635  while (ShiftAmount--)
636    Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
637                         dl, VT, Victim);
638
639  return Victim;
640}
641
642SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op,
643                                                 SelectionDAG &DAG) const {
644  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
645  int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
646
647  // Create the TargetGlobalAddress node, folding in the constant offset.
648  SDValue Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
649                                              getPointerTy(), Offset);
650  return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
651                     getPointerTy(), Result);
652}
653
654SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
655                                                  SelectionDAG &DAG) const {
656  DebugLoc dl = Op.getDebugLoc();
657  const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
658  SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
659
660  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
661}
662
663SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op,
664                                                SelectionDAG &DAG) const {
665  DebugLoc dl = Op.getDebugLoc();
666  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
667  SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), /*isTarget=*/true);
668
669  return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
670}
671
672static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
673                       ISD::CondCode CC,
674                       DebugLoc dl, SelectionDAG &DAG) {
675  // FIXME: Handle bittests someday
676  assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
677
678  // FIXME: Handle jump negative someday
679  MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
680  switch (CC) {
681  default: llvm_unreachable("Invalid integer condition!");
682  case ISD::SETEQ:
683    TCC = MSP430CC::COND_E;     // aka COND_Z
684    // Minor optimization: if LHS is a constant, swap operands, then the
685    // constant can be folded into comparison.
686    if (LHS.getOpcode() == ISD::Constant)
687      std::swap(LHS, RHS);
688    break;
689  case ISD::SETNE:
690    TCC = MSP430CC::COND_NE;    // aka COND_NZ
691    // Minor optimization: if LHS is a constant, swap operands, then the
692    // constant can be folded into comparison.
693    if (LHS.getOpcode() == ISD::Constant)
694      std::swap(LHS, RHS);
695    break;
696  case ISD::SETULE:
697    std::swap(LHS, RHS);        // FALLTHROUGH
698  case ISD::SETUGE:
699    // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
700    // fold constant into instruction.
701    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
702      LHS = RHS;
703      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
704      TCC = MSP430CC::COND_LO;
705      break;
706    }
707    TCC = MSP430CC::COND_HS;    // aka COND_C
708    break;
709  case ISD::SETUGT:
710    std::swap(LHS, RHS);        // FALLTHROUGH
711  case ISD::SETULT:
712    // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
713    // fold constant into instruction.
714    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
715      LHS = RHS;
716      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
717      TCC = MSP430CC::COND_HS;
718      break;
719    }
720    TCC = MSP430CC::COND_LO;    // aka COND_NC
721    break;
722  case ISD::SETLE:
723    std::swap(LHS, RHS);        // FALLTHROUGH
724  case ISD::SETGE:
725    // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
726    // fold constant into instruction.
727    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
728      LHS = RHS;
729      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
730      TCC = MSP430CC::COND_L;
731      break;
732    }
733    TCC = MSP430CC::COND_GE;
734    break;
735  case ISD::SETGT:
736    std::swap(LHS, RHS);        // FALLTHROUGH
737  case ISD::SETLT:
738    // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
739    // fold constant into instruction.
740    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
741      LHS = RHS;
742      RHS = DAG.getConstant(C->getSExtValue() + 1, C->getValueType(0));
743      TCC = MSP430CC::COND_GE;
744      break;
745    }
746    TCC = MSP430CC::COND_L;
747    break;
748  }
749
750  TargetCC = DAG.getConstant(TCC, MVT::i8);
751  return DAG.getNode(MSP430ISD::CMP, dl, MVT::Flag, LHS, RHS);
752}
753
754
755SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
756  SDValue Chain = Op.getOperand(0);
757  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
758  SDValue LHS   = Op.getOperand(2);
759  SDValue RHS   = Op.getOperand(3);
760  SDValue Dest  = Op.getOperand(4);
761  DebugLoc dl   = Op.getDebugLoc();
762
763  SDValue TargetCC;
764  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
765
766  return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
767                     Chain, Dest, TargetCC, Flag);
768}
769
770SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
771  SDValue LHS   = Op.getOperand(0);
772  SDValue RHS   = Op.getOperand(1);
773  DebugLoc dl   = Op.getDebugLoc();
774
775  // If we are doing an AND and testing against zero, then the CMP
776  // will not be generated.  The AND (or BIT) will generate the condition codes,
777  // but they are different from CMP.
778  // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
779  // lowering & isel wouldn't diverge.
780  bool andCC = false;
781  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
782    if (RHSC->isNullValue() && LHS.hasOneUse() &&
783        (LHS.getOpcode() == ISD::AND ||
784         (LHS.getOpcode() == ISD::TRUNCATE &&
785          LHS.getOperand(0).getOpcode() == ISD::AND))) {
786      andCC = true;
787    }
788  }
789  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
790  SDValue TargetCC;
791  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
792
793  // Get the condition codes directly from the status register, if its easy.
794  // Otherwise a branch will be generated.  Note that the AND and BIT
795  // instructions generate different flags than CMP, the carry bit can be used
796  // for NE/EQ.
797  bool Invert = false;
798  bool Shift = false;
799  bool Convert = true;
800  switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
801   default:
802    Convert = false;
803    break;
804   case MSP430CC::COND_HS:
805     // Res = SRW & 1, no processing is required
806     break;
807   case MSP430CC::COND_LO:
808     // Res = ~(SRW & 1)
809     Invert = true;
810     break;
811   case MSP430CC::COND_NE:
812     if (andCC) {
813       // C = ~Z, thus Res = SRW & 1, no processing is required
814     } else {
815       // Res = ~((SRW >> 1) & 1)
816       Shift = true;
817       Invert = true;
818     }
819     break;
820   case MSP430CC::COND_E:
821     Shift = true;
822     // C = ~Z for AND instruction, thus we can put Res = ~(SRW & 1), however,
823     // Res = (SRW >> 1) & 1 is 1 word shorter.
824     break;
825  }
826  EVT VT = Op.getValueType();
827  SDValue One  = DAG.getConstant(1, VT);
828  if (Convert) {
829    SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SRW,
830                                    MVT::i16, Flag);
831    if (Shift)
832      // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
833      SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
834    SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
835    if (Invert)
836      SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
837    return SR;
838  } else {
839    SDValue Zero = DAG.getConstant(0, VT);
840    SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
841    SmallVector<SDValue, 4> Ops;
842    Ops.push_back(One);
843    Ops.push_back(Zero);
844    Ops.push_back(TargetCC);
845    Ops.push_back(Flag);
846    return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
847  }
848}
849
850SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op,
851                                             SelectionDAG &DAG) const {
852  SDValue LHS    = Op.getOperand(0);
853  SDValue RHS    = Op.getOperand(1);
854  SDValue TrueV  = Op.getOperand(2);
855  SDValue FalseV = Op.getOperand(3);
856  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
857  DebugLoc dl    = Op.getDebugLoc();
858
859  SDValue TargetCC;
860  SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
861
862  SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
863  SmallVector<SDValue, 4> Ops;
864  Ops.push_back(TrueV);
865  Ops.push_back(FalseV);
866  Ops.push_back(TargetCC);
867  Ops.push_back(Flag);
868
869  return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
870}
871
872SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
873                                               SelectionDAG &DAG) const {
874  SDValue Val = Op.getOperand(0);
875  EVT VT      = Op.getValueType();
876  DebugLoc dl = Op.getDebugLoc();
877
878  assert(VT == MVT::i16 && "Only support i16 for now!");
879
880  return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
881                     DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
882                     DAG.getValueType(Val.getValueType()));
883}
884
885SDValue
886MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
887  MachineFunction &MF = DAG.getMachineFunction();
888  MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
889  int ReturnAddrIndex = FuncInfo->getRAIndex();
890
891  if (ReturnAddrIndex == 0) {
892    // Set up a frame object for the return address.
893    uint64_t SlotSize = TD->getPointerSize();
894    ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
895                                                           true);
896    FuncInfo->setRAIndex(ReturnAddrIndex);
897  }
898
899  return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
900}
901
902SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op,
903                                              SelectionDAG &DAG) const {
904  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
905  MFI->setReturnAddressIsTaken(true);
906
907  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
908  DebugLoc dl = Op.getDebugLoc();
909
910  if (Depth > 0) {
911    SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
912    SDValue Offset =
913      DAG.getConstant(TD->getPointerSize(), MVT::i16);
914    return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
915                       DAG.getNode(ISD::ADD, dl, getPointerTy(),
916                                   FrameAddr, Offset),
917                       NULL, 0, false, false, 0);
918  }
919
920  // Just load the return address.
921  SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
922  return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
923                     RetAddrFI, NULL, 0, false, false, 0);
924}
925
926SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op,
927                                             SelectionDAG &DAG) const {
928  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
929  MFI->setFrameAddressIsTaken(true);
930
931  EVT VT = Op.getValueType();
932  DebugLoc dl = Op.getDebugLoc();  // FIXME probably not meaningful
933  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
934  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
935                                         MSP430::FPW, VT);
936  while (Depth--)
937    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
938                            false, false, 0);
939  return FrameAddr;
940}
941
942/// getPostIndexedAddressParts - returns true by value, base pointer and
943/// offset pointer and addressing mode by reference if this node can be
944/// combined with a load / store to form a post-indexed load / store.
945bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
946                                                      SDValue &Base,
947                                                      SDValue &Offset,
948                                                      ISD::MemIndexedMode &AM,
949                                                      SelectionDAG &DAG) const {
950
951  LoadSDNode *LD = cast<LoadSDNode>(N);
952  if (LD->getExtensionType() != ISD::NON_EXTLOAD)
953    return false;
954
955  EVT VT = LD->getMemoryVT();
956  if (VT != MVT::i8 && VT != MVT::i16)
957    return false;
958
959  if (Op->getOpcode() != ISD::ADD)
960    return false;
961
962  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
963    uint64_t RHSC = RHS->getZExtValue();
964    if ((VT == MVT::i16 && RHSC != 2) ||
965        (VT == MVT::i8 && RHSC != 1))
966      return false;
967
968    Base = Op->getOperand(0);
969    Offset = DAG.getConstant(RHSC, VT);
970    AM = ISD::POST_INC;
971    return true;
972  }
973
974  return false;
975}
976
977
978const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
979  switch (Opcode) {
980  default: return NULL;
981  case MSP430ISD::RET_FLAG:           return "MSP430ISD::RET_FLAG";
982  case MSP430ISD::RETI_FLAG:          return "MSP430ISD::RETI_FLAG";
983  case MSP430ISD::RRA:                return "MSP430ISD::RRA";
984  case MSP430ISD::RLA:                return "MSP430ISD::RLA";
985  case MSP430ISD::RRC:                return "MSP430ISD::RRC";
986  case MSP430ISD::CALL:               return "MSP430ISD::CALL";
987  case MSP430ISD::Wrapper:            return "MSP430ISD::Wrapper";
988  case MSP430ISD::BR_CC:              return "MSP430ISD::BR_CC";
989  case MSP430ISD::CMP:                return "MSP430ISD::CMP";
990  case MSP430ISD::SELECT_CC:          return "MSP430ISD::SELECT_CC";
991  case MSP430ISD::SHL:                return "MSP430ISD::SHL";
992  case MSP430ISD::SRA:                return "MSP430ISD::SRA";
993  }
994}
995
996bool MSP430TargetLowering::isTruncateFree(const Type *Ty1,
997                                          const Type *Ty2) const {
998  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
999    return false;
1000
1001  return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
1002}
1003
1004bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1005  if (!VT1.isInteger() || !VT2.isInteger())
1006    return false;
1007
1008  return (VT1.getSizeInBits() > VT2.getSizeInBits());
1009}
1010
1011bool MSP430TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
1012  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1013  return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
1014}
1015
1016bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
1017  // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1018  return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
1019}
1020
1021//===----------------------------------------------------------------------===//
1022//  Other Lowering Code
1023//===----------------------------------------------------------------------===//
1024
1025MachineBasicBlock*
1026MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,
1027                                     MachineBasicBlock *BB) const {
1028  MachineFunction *F = BB->getParent();
1029  MachineRegisterInfo &RI = F->getRegInfo();
1030  DebugLoc dl = MI->getDebugLoc();
1031  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1032
1033  unsigned Opc;
1034  const TargetRegisterClass * RC;
1035  switch (MI->getOpcode()) {
1036  default:
1037    assert(0 && "Invalid shift opcode!");
1038  case MSP430::Shl8:
1039   Opc = MSP430::SHL8r1;
1040   RC = MSP430::GR8RegisterClass;
1041   break;
1042  case MSP430::Shl16:
1043   Opc = MSP430::SHL16r1;
1044   RC = MSP430::GR16RegisterClass;
1045   break;
1046  case MSP430::Sra8:
1047   Opc = MSP430::SAR8r1;
1048   RC = MSP430::GR8RegisterClass;
1049   break;
1050  case MSP430::Sra16:
1051   Opc = MSP430::SAR16r1;
1052   RC = MSP430::GR16RegisterClass;
1053   break;
1054  case MSP430::Srl8:
1055   Opc = MSP430::SAR8r1c;
1056   RC = MSP430::GR8RegisterClass;
1057   break;
1058  case MSP430::Srl16:
1059   Opc = MSP430::SAR16r1c;
1060   RC = MSP430::GR16RegisterClass;
1061   break;
1062  }
1063
1064  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1065  MachineFunction::iterator I = BB;
1066  ++I;
1067
1068  // Create loop block
1069  MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1070  MachineBasicBlock *RemBB  = F->CreateMachineBasicBlock(LLVM_BB);
1071
1072  F->insert(I, LoopBB);
1073  F->insert(I, RemBB);
1074
1075  // Update machine-CFG edges by transferring all successors of the current
1076  // block to the block containing instructions after shift.
1077  RemBB->splice(RemBB->begin(), BB,
1078                llvm::next(MachineBasicBlock::iterator(MI)),
1079                BB->end());
1080  RemBB->transferSuccessorsAndUpdatePHIs(BB);
1081
1082  // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1083  BB->addSuccessor(LoopBB);
1084  BB->addSuccessor(RemBB);
1085  LoopBB->addSuccessor(RemBB);
1086  LoopBB->addSuccessor(LoopBB);
1087
1088  unsigned ShiftAmtReg = RI.createVirtualRegister(MSP430::GR8RegisterClass);
1089  unsigned ShiftAmtReg2 = RI.createVirtualRegister(MSP430::GR8RegisterClass);
1090  unsigned ShiftReg = RI.createVirtualRegister(RC);
1091  unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1092  unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg();
1093  unsigned SrcReg = MI->getOperand(1).getReg();
1094  unsigned DstReg = MI->getOperand(0).getReg();
1095
1096  // BB:
1097  // cmp 0, N
1098  // je RemBB
1099  BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1100    .addReg(ShiftAmtSrcReg).addImm(0);
1101  BuildMI(BB, dl, TII.get(MSP430::JCC))
1102    .addMBB(RemBB)
1103    .addImm(MSP430CC::COND_E);
1104
1105  // LoopBB:
1106  // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1107  // ShiftAmt = phi [%N, BB],      [%ShiftAmt2, LoopBB]
1108  // ShiftReg2 = shift ShiftReg
1109  // ShiftAmt2 = ShiftAmt - 1;
1110  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1111    .addReg(SrcReg).addMBB(BB)
1112    .addReg(ShiftReg2).addMBB(LoopBB);
1113  BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1114    .addReg(ShiftAmtSrcReg).addMBB(BB)
1115    .addReg(ShiftAmtReg2).addMBB(LoopBB);
1116  BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1117    .addReg(ShiftReg);
1118  BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1119    .addReg(ShiftAmtReg).addImm(1);
1120  BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1121    .addMBB(LoopBB)
1122    .addImm(MSP430CC::COND_NE);
1123
1124  // RemBB:
1125  // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1126  BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1127    .addReg(SrcReg).addMBB(BB)
1128    .addReg(ShiftReg2).addMBB(LoopBB);
1129
1130  MI->eraseFromParent();   // The pseudo instruction is gone now.
1131  return RemBB;
1132}
1133
1134MachineBasicBlock*
1135MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1136                                                  MachineBasicBlock *BB) const {
1137  unsigned Opc = MI->getOpcode();
1138
1139  if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1140      Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1141      Opc == MSP430::Srl8 || Opc == MSP430::Srl16)
1142    return EmitShiftInstr(MI, BB);
1143
1144  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1145  DebugLoc dl = MI->getDebugLoc();
1146
1147  assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1148         "Unexpected instr type to insert");
1149
1150  // To "insert" a SELECT instruction, we actually have to insert the diamond
1151  // control-flow pattern.  The incoming instruction knows the destination vreg
1152  // to set, the condition code register to branch on, the true/false values to
1153  // select between, and a branch opcode to use.
1154  const BasicBlock *LLVM_BB = BB->getBasicBlock();
1155  MachineFunction::iterator I = BB;
1156  ++I;
1157
1158  //  thisMBB:
1159  //  ...
1160  //   TrueVal = ...
1161  //   cmpTY ccX, r1, r2
1162  //   jCC copy1MBB
1163  //   fallthrough --> copy0MBB
1164  MachineBasicBlock *thisMBB = BB;
1165  MachineFunction *F = BB->getParent();
1166  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1167  MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1168  F->insert(I, copy0MBB);
1169  F->insert(I, copy1MBB);
1170  // Update machine-CFG edges by transferring all successors of the current
1171  // block to the new block which will contain the Phi node for the select.
1172  copy1MBB->splice(copy1MBB->begin(), BB,
1173                   llvm::next(MachineBasicBlock::iterator(MI)),
1174                   BB->end());
1175  copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
1176  // Next, add the true and fallthrough blocks as its successors.
1177  BB->addSuccessor(copy0MBB);
1178  BB->addSuccessor(copy1MBB);
1179
1180  BuildMI(BB, dl, TII.get(MSP430::JCC))
1181    .addMBB(copy1MBB)
1182    .addImm(MI->getOperand(3).getImm());
1183
1184  //  copy0MBB:
1185  //   %FalseValue = ...
1186  //   # fallthrough to copy1MBB
1187  BB = copy0MBB;
1188
1189  // Update machine-CFG edges
1190  BB->addSuccessor(copy1MBB);
1191
1192  //  copy1MBB:
1193  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1194  //  ...
1195  BB = copy1MBB;
1196  BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI),
1197          MI->getOperand(0).getReg())
1198    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1199    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1200
1201  MI->eraseFromParent();   // The pseudo instruction is gone now.
1202  return BB;
1203}
1204