1//===-- MSP430ISelLowering.h - MSP430 DAG Lowering Interface ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that MSP430 uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_TARGET_MSP430_MSP430ISELLOWERING_H
16#define LLVM_LIB_TARGET_MSP430_MSP430ISELLOWERING_H
17
18#include "MSP430.h"
19#include "llvm/CodeGen/SelectionDAG.h"
20#include "llvm/Target/TargetLowering.h"
21
22namespace llvm {
23  namespace MSP430ISD {
24    enum NodeType : unsigned {
25      FIRST_NUMBER = ISD::BUILTIN_OP_END,
26
27      /// Return with a flag operand. Operand 0 is the chain operand.
28      RET_FLAG,
29
30      /// Same as RET_FLAG, but used for returning from ISRs.
31      RETI_FLAG,
32
33      /// Y = R{R,L}A X, rotate right (left) arithmetically
34      RRA, RLA,
35
36      /// Y = RRC X, rotate right via carry
37      RRC,
38
39      /// CALL - These operations represent an abstract call
40      /// instruction, which includes a bunch of information.
41      CALL,
42
43      /// Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol,
44      /// and TargetGlobalAddress.
45      Wrapper,
46
47      /// CMP - Compare instruction.
48      CMP,
49
50      /// SetCC - Operand 0 is condition code, and operand 1 is the flag
51      /// operand produced by a CMP instruction.
52      SETCC,
53
54      /// MSP430 conditional branches. Operand 0 is the chain operand, operand 1
55      /// is the block to branch if condition is true, operand 2 is the
56      /// condition code, and operand 3 is the flag operand produced by a CMP
57      /// instruction.
58      BR_CC,
59
60      /// SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
61      /// is condition code and operand 4 is flag operand.
62      SELECT_CC,
63
64      /// SHL, SRA, SRL - Non-constant shifts.
65      SHL, SRA, SRL
66    };
67  }
68
69  class MSP430Subtarget;
70  class MSP430TargetLowering : public TargetLowering {
71  public:
72    explicit MSP430TargetLowering(const TargetMachine &TM,
73                                  const MSP430Subtarget &STI);
74
75    MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
76      return MVT::i8;
77    }
78
79    /// LowerOperation - Provide custom lowering hooks for some operations.
80    SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
81
82    /// getTargetNodeName - This method returns the name of a target specific
83    /// DAG node.
84    const char *getTargetNodeName(unsigned Opcode) const override;
85
86    SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
87    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
88    SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
89    SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
90    SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
91    SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
92    SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
93    SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
94    SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
95    SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
96    SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
97    SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
98    SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
99
100    TargetLowering::ConstraintType
101    getConstraintType(StringRef Constraint) const override;
102    std::pair<unsigned, const TargetRegisterClass *>
103    getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
104                                 StringRef Constraint, MVT VT) const override;
105
106    /// isTruncateFree - Return true if it's free to truncate a value of type
107    /// Ty1 to type Ty2. e.g. On msp430 it's free to truncate a i16 value in
108    /// register R15W to i8 by referencing its sub-register R15B.
109    bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
110    bool isTruncateFree(EVT VT1, EVT VT2) const override;
111
112    /// isZExtFree - Return true if any actual instruction that defines a value
113    /// of type Ty1 implicit zero-extends the value to Ty2 in the result
114    /// register. This does not necessarily include registers defined in unknown
115    /// ways, such as incoming arguments, or copies from unknown virtual
116    /// registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not
117    /// necessarily apply to truncate instructions. e.g. on msp430, all
118    /// instructions that define 8-bit values implicit zero-extend the result
119    /// out to 16 bits.
120    bool isZExtFree(Type *Ty1, Type *Ty2) const override;
121    bool isZExtFree(EVT VT1, EVT VT2) const override;
122    bool isZExtFree(SDValue Val, EVT VT2) const override;
123
124    MachineBasicBlock *
125    EmitInstrWithCustomInserter(MachineInstr &MI,
126                                MachineBasicBlock *BB) const override;
127    MachineBasicBlock *EmitShiftInstr(MachineInstr &MI,
128                                      MachineBasicBlock *BB) const;
129
130  private:
131    SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
132                           CallingConv::ID CallConv, bool isVarArg,
133                           bool isTailCall,
134                           const SmallVectorImpl<ISD::OutputArg> &Outs,
135                           const SmallVectorImpl<SDValue> &OutVals,
136                           const SmallVectorImpl<ISD::InputArg> &Ins,
137                           const SDLoc &dl, SelectionDAG &DAG,
138                           SmallVectorImpl<SDValue> &InVals) const;
139
140    SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
141                              bool isVarArg,
142                              const SmallVectorImpl<ISD::InputArg> &Ins,
143                              const SDLoc &dl, SelectionDAG &DAG,
144                              SmallVectorImpl<SDValue> &InVals) const;
145
146    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
147                            CallingConv::ID CallConv, bool isVarArg,
148                            const SmallVectorImpl<ISD::InputArg> &Ins,
149                            const SDLoc &dl, SelectionDAG &DAG,
150                            SmallVectorImpl<SDValue> &InVals) const;
151
152    SDValue
153    LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
154                         const SmallVectorImpl<ISD::InputArg> &Ins,
155                         const SDLoc &dl, SelectionDAG &DAG,
156                         SmallVectorImpl<SDValue> &InVals) const override;
157    SDValue
158      LowerCall(TargetLowering::CallLoweringInfo &CLI,
159                SmallVectorImpl<SDValue> &InVals) const override;
160
161    SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
162                        const SmallVectorImpl<ISD::OutputArg> &Outs,
163                        const SmallVectorImpl<SDValue> &OutVals,
164                        const SDLoc &dl, SelectionDAG &DAG) const override;
165
166    bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
167                                    SDValue &Base,
168                                    SDValue &Offset,
169                                    ISD::MemIndexedMode &AM,
170                                    SelectionDAG &DAG) const override;
171  };
172} // namespace llvm
173
174#endif
175