131d157ae1ac2cd9c787dc3c1d28e64c682803844Jia Liu//===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===// 233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov// 333464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov// The LLVM Compiler Infrastructure 433464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov// 533464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov// This file is distributed under the University of Illinois Open Source 633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov// License. See LICENSE.TXT for details. 733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov// 833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov//===----------------------------------------------------------------------===// 933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov// 1016c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov// This file contains the PPC implementation of TargetFrameLowering class. 1133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov// 1233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov//===----------------------------------------------------------------------===// 1333464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 1416c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov#include "PPCFrameLowering.h" 159d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky#include "PPCInstrBuilder.h" 16d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "PPCInstrInfo.h" 1733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov#include "PPCMachineFunctionInfo.h" 18c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines#include "PPCSubtarget.h" 19ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines#include "PPCTargetMachine.h" 2033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov#include "llvm/CodeGen/MachineFrameInfo.h" 2133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov#include "llvm/CodeGen/MachineFunction.h" 2233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov#include "llvm/CodeGen/MachineInstrBuilder.h" 2333464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov#include "llvm/CodeGen/MachineModuleInfo.h" 2433464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov#include "llvm/CodeGen/MachineRegisterInfo.h" 2594c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov#include "llvm/CodeGen/RegisterScavenging.h" 260b8c9a80f20772c3793201ab5b251d3520b9cea3Chandler Carruth#include "llvm/IR/Function.h" 2733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov#include "llvm/Target/TargetOptions.h" 2833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 2933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikovusing namespace llvm; 3033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 3133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov/// VRRegNo - Map from a numbered VR register to its enum value. 3233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov/// 33f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainarstatic const MCPhysReg VRRegNo[] = { 3433464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 3533464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 3633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 3733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 3833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov}; 3933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 40ebe69fe11e48d322045d5949c83283927a0d790bStephen Hinesstatic unsigned computeReturnSaveOffset(const PPCSubtarget &STI) { 41ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines if (STI.isDarwinABI()) 42ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines return STI.isPPC64() ? 16 : 8; 43ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // SVR4 ABI: 44ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines return STI.isPPC64() ? 16 : 4; 45ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines} 46ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 47ebe69fe11e48d322045d5949c83283927a0d790bStephen Hinesstatic unsigned computeTOCSaveOffset(const PPCSubtarget &STI) { 48ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines return STI.isELFv2ABI() ? 24 : 40; 49ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines} 50ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 51ebe69fe11e48d322045d5949c83283927a0d790bStephen Hinesstatic unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI) { 52ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // For the Darwin ABI: 53ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area 54ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // for saving the frame pointer (if needed.) While the published ABI has 55ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // not used this slot since at least MacOSX 10.2, there is older code 56ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // around that does use it, and that needs to continue to work. 57ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines if (STI.isDarwinABI()) 58ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines return STI.isPPC64() ? -8U : -4U; 59ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 60ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // SVR4 ABI: First slot in the general register save area. 61ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines return STI.isPPC64() ? -8U : -4U; 62ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines} 63ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 64ebe69fe11e48d322045d5949c83283927a0d790bStephen Hinesstatic unsigned computeLinkageSize(const PPCSubtarget &STI) { 65ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines if (STI.isDarwinABI() || STI.isPPC64()) 66ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines return (STI.isELFv2ABI() ? 4 : 6) * (STI.isPPC64() ? 8 : 4); 67ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 68ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // SVR4 ABI: 69ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines return 8; 70ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines} 71ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 72ebe69fe11e48d322045d5949c83283927a0d790bStephen Hinesstatic unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI) { 73ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines if (STI.isDarwinABI()) 74ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines return STI.isPPC64() ? -16U : -8U; 75ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 76ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // SVR4 ABI: First slot in the general register save area. 77ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines return STI.isPPC64() 78ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines ? -16U 79de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar : STI.getTargetMachine().isPositionIndependent() ? -12U : -8U; 80ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines} 81ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 82c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen HinesPPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI) 83c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 84ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines STI.getPlatformStackAlignment(), 0), 85ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)), 86ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines TOCSaveOffset(computeTOCSaveOffset(Subtarget)), 87ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)), 88ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines LinkageSize(computeLinkageSize(Subtarget)), 89ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines BasePointerSaveOffset(computeBasePointerSaveOffset(STI)) {} 90c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines 91c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines// With the SVR4 ABI, callee-saved registers have fixed offsets on the stack. 92c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hinesconst PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots( 93c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines unsigned &NumEntries) const { 94c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines if (Subtarget.isDarwinABI()) { 95c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines NumEntries = 1; 96c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines if (Subtarget.isPPC64()) { 97c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines static const SpillSlot darwin64Offsets = {PPC::X31, -8}; 98c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines return &darwin64Offsets; 99c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines } else { 100c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines static const SpillSlot darwinOffsets = {PPC::R31, -4}; 101c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines return &darwinOffsets; 102c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines } 103c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines } 104c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines 105c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines // Early exit if not using the SVR4 ABI. 106c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines if (!Subtarget.isSVR4ABI()) { 107c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines NumEntries = 0; 108c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines return nullptr; 109c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines } 110c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines 111c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines // Note that the offsets here overlap, but this is fixed up in 112c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines // processFunctionBeforeFrameFinalized. 113c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines 114c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines static const SpillSlot Offsets[] = { 115c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines // Floating-point register save area offsets. 116c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F31, -8}, 117c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F30, -16}, 118c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F29, -24}, 119c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F28, -32}, 120c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F27, -40}, 121c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F26, -48}, 122c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F25, -56}, 123c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F24, -64}, 124c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F23, -72}, 125c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F22, -80}, 126c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F21, -88}, 127c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F20, -96}, 128c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F19, -104}, 129c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F18, -112}, 130c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F17, -120}, 131c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F16, -128}, 132c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F15, -136}, 133c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F14, -144}, 134c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines 135c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines // General register save area offsets. 136c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::R31, -4}, 137c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::R30, -8}, 138c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::R29, -12}, 139c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::R28, -16}, 140c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::R27, -20}, 141c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::R26, -24}, 142c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::R25, -28}, 143c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::R24, -32}, 144c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::R23, -36}, 145c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::R22, -40}, 146c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::R21, -44}, 147c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::R20, -48}, 148c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::R19, -52}, 149c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::R18, -56}, 150c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::R17, -60}, 151c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::R16, -64}, 152c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::R15, -68}, 153c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::R14, -72}, 154c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines 155c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines // CR save area offset. We map each of the nonvolatile CR fields 156c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines // to the slot for CR2, which is the first of the nonvolatile CR 157c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines // fields to be assigned, so that we only allocate one save slot. 158c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines // See PPCRegisterInfo::hasReservedSpillSlot() for more information. 159c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::CR2, -4}, 160c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines 161c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines // VRSAVE save area offset. 162c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::VRSAVE, -4}, 163c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines 164c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines // Vector register save area 165c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::V31, -16}, 166c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::V30, -32}, 167c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::V29, -48}, 168c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::V28, -64}, 169c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::V27, -80}, 170c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::V26, -96}, 171c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::V25, -112}, 172c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::V24, -128}, 173c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::V23, -144}, 174c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::V22, -160}, 175c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::V21, -176}, 176c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::V20, -192}}; 177c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines 178c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines static const SpillSlot Offsets64[] = { 179c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines // Floating-point register save area offsets. 180c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F31, -8}, 181c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F30, -16}, 182c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F29, -24}, 183c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F28, -32}, 184c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F27, -40}, 185c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F26, -48}, 186c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F25, -56}, 187c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F24, -64}, 188c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F23, -72}, 189c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F22, -80}, 190c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F21, -88}, 191c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F20, -96}, 192c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F19, -104}, 193c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F18, -112}, 194c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F17, -120}, 195c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F16, -128}, 196c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F15, -136}, 197c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::F14, -144}, 198c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines 199c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines // General register save area offsets. 200c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::X31, -8}, 201c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::X30, -16}, 202c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::X29, -24}, 203c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::X28, -32}, 204c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::X27, -40}, 205c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::X26, -48}, 206c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::X25, -56}, 207c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::X24, -64}, 208c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::X23, -72}, 209c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::X22, -80}, 210c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::X21, -88}, 211c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::X20, -96}, 212c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::X19, -104}, 213c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::X18, -112}, 214c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::X17, -120}, 215c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::X16, -128}, 216c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::X15, -136}, 217c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::X14, -144}, 218c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines 219c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines // VRSAVE save area offset. 220c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::VRSAVE, -4}, 221c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines 222c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines // Vector register save area 223c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::V31, -16}, 224c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::V30, -32}, 225c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::V29, -48}, 226c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::V28, -64}, 227c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::V27, -80}, 228c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::V26, -96}, 229c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::V25, -112}, 230c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::V24, -128}, 231c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::V23, -144}, 232c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::V22, -160}, 233c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::V21, -176}, 234c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines {PPC::V20, -192}}; 235c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines 236c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines if (Subtarget.isPPC64()) { 237c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines NumEntries = array_lengthof(Offsets64); 238c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines 239c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines return Offsets64; 240c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines } else { 241c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines NumEntries = array_lengthof(Offsets); 242c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines 243c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines return Offsets; 244c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines } 245c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines} 246c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines 24733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov/// RemoveVRSaveCode - We have found that this function does not need any code 24833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov/// to manipulate the VRSAVE register, even though it uses vector registers. 24933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov/// This can happen when the only registers used are known to be live in or out 25033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov/// of the function. Remove all of the VRSAVE related code from the function. 251a5d0ab555384baa293b06686bec5a01fb9638ca3Bill Schmidt/// FIXME: The removal of the code results in a compile failure at -O0 when the 252a5d0ab555384baa293b06686bec5a01fb9638ca3Bill Schmidt/// function contains a function call, as the GPR containing original VRSAVE 253a5d0ab555384baa293b06686bec5a01fb9638ca3Bill Schmidt/// contents is spilled and reloaded around the call. Without the prolog code, 254a5d0ab555384baa293b06686bec5a01fb9638ca3Bill Schmidt/// the spill instruction refers to an undefined register. This code needs 255a5d0ab555384baa293b06686bec5a01fb9638ca3Bill Schmidt/// to account for all uses of that GPR. 25633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikovstatic void RemoveVRSaveCode(MachineInstr *MI) { 25733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov MachineBasicBlock *Entry = MI->getParent(); 25833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov MachineFunction *MF = Entry->getParent(); 25933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 26033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 26133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov MachineBasicBlock::iterator MBBI = MI; 26233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov ++MBBI; 26333464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 26433464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov MBBI->eraseFromParent(); 26533464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 26633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov bool RemovedAllMTVRSAVEs = true; 26733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // See if we can find and remove the MTVRSAVE instruction from all of the 26833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // epilog blocks. 26933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 27033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // If last instruction is a return instruction, add an epilogue 271f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (I->isReturnBlock()) { 27233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov bool FoundIt = false; 27333464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov for (MBBI = I->end(); MBBI != I->begin(); ) { 27433464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov --MBBI; 27533464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov if (MBBI->getOpcode() == PPC::MTVRSAVE) { 27633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov MBBI->eraseFromParent(); // remove it. 27733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov FoundIt = true; 27833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov break; 27933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 28033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 28133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov RemovedAllMTVRSAVEs &= FoundIt; 28233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 28333464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 28433464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 28533464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // If we found and removed all MTVRSAVE instructions, remove the read of 28633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // VRSAVE as well. 28733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov if (RemovedAllMTVRSAVEs) { 28833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov MBBI = MI; 28933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 29033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov --MBBI; 29133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 29233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov MBBI->eraseFromParent(); 29333464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 29433464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 29533464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // Finally, nuke the UPDATE_VRSAVE. 29633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov MI->eraseFromParent(); 29733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov} 29833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 29933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 30033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov// instruction selector. Based on the vector registers that have been used, 30133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov// transform this into the appropriate ORI instruction. 30233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikovstatic void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 30333464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov MachineFunction *MF = MI->getParent()->getParent(); 30437ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); 30533464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov DebugLoc dl = MI->getDebugLoc(); 30633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 307f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar const MachineRegisterInfo &MRI = MF->getRegInfo(); 30833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov unsigned UsedRegMask = 0; 30933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov for (unsigned i = 0; i != 32; ++i) 310f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (MRI.isPhysRegModified(VRRegNo[i])) 31133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov UsedRegMask |= 1 << (31-i); 31233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 31333464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // Live in and live out values already must be in the mask, so don't bother 31433464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // marking them. 31533464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov for (MachineRegisterInfo::livein_iterator 31633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov I = MF->getRegInfo().livein_begin(), 31733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov E = MF->getRegInfo().livein_end(); I != E; ++I) { 318aa6047d23d8ed55abd8545f5cbe82cd13cbd756aHal Finkel unsigned RegNo = TRI->getEncodingValue(I->first); 31933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 32033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 32133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 3220a9d1d31e9b3239b1dc38a67d31810c4bb405d0aJakob Stoklund Olesen 3230a9d1d31e9b3239b1dc38a67d31810c4bb405d0aJakob Stoklund Olesen // Live out registers appear as use operands on return instructions. 3240a9d1d31e9b3239b1dc38a67d31810c4bb405d0aJakob Stoklund Olesen for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end(); 3250a9d1d31e9b3239b1dc38a67d31810c4bb405d0aJakob Stoklund Olesen UsedRegMask != 0 && BI != BE; ++BI) { 3260a9d1d31e9b3239b1dc38a67d31810c4bb405d0aJakob Stoklund Olesen const MachineBasicBlock &MBB = *BI; 327f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (!MBB.isReturnBlock()) 3280a9d1d31e9b3239b1dc38a67d31810c4bb405d0aJakob Stoklund Olesen continue; 3290a9d1d31e9b3239b1dc38a67d31810c4bb405d0aJakob Stoklund Olesen const MachineInstr &Ret = MBB.back(); 3300a9d1d31e9b3239b1dc38a67d31810c4bb405d0aJakob Stoklund Olesen for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) { 3310a9d1d31e9b3239b1dc38a67d31810c4bb405d0aJakob Stoklund Olesen const MachineOperand &MO = Ret.getOperand(I); 3320a9d1d31e9b3239b1dc38a67d31810c4bb405d0aJakob Stoklund Olesen if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg())) 3330a9d1d31e9b3239b1dc38a67d31810c4bb405d0aJakob Stoklund Olesen continue; 334aa6047d23d8ed55abd8545f5cbe82cd13cbd756aHal Finkel unsigned RegNo = TRI->getEncodingValue(MO.getReg()); 3350a9d1d31e9b3239b1dc38a67d31810c4bb405d0aJakob Stoklund Olesen UsedRegMask &= ~(1 << (31-RegNo)); 3360a9d1d31e9b3239b1dc38a67d31810c4bb405d0aJakob Stoklund Olesen } 33733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 33833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 33933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // If no registers are used, turn this into a copy. 34033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov if (UsedRegMask == 0) { 34133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // Remove all VRSAVE code. 34233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov RemoveVRSaveCode(MI); 34333464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov return; 34433464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 34533464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 34633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov unsigned SrcReg = MI->getOperand(1).getReg(); 34733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov unsigned DstReg = MI->getOperand(0).getReg(); 34833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 34933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 35033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov if (DstReg != SrcReg) 35133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 35233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov .addReg(SrcReg) 35333464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov .addImm(UsedRegMask); 35433464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov else 35533464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 35633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov .addReg(SrcReg, RegState::Kill) 35733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov .addImm(UsedRegMask); 35833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 35933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov if (DstReg != SrcReg) 36033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 36133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov .addReg(SrcReg) 36233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov .addImm(UsedRegMask >> 16); 36333464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov else 36433464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 36533464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov .addReg(SrcReg, RegState::Kill) 36633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov .addImm(UsedRegMask >> 16); 36733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } else { 36833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov if (DstReg != SrcReg) 36933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 37033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov .addReg(SrcReg) 37133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov .addImm(UsedRegMask >> 16); 37233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov else 37333464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 37433464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov .addReg(SrcReg, RegState::Kill) 37533464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov .addImm(UsedRegMask >> 16); 37633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 37733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 37833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov .addReg(DstReg, RegState::Kill) 37933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov .addImm(UsedRegMask & 0xFFFF); 38033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 38133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 38233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // Remove the old UPDATE_VRSAVE instruction. 38333464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov MI->eraseFromParent(); 38433464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov} 38533464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 3869d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divackystatic bool spillsCR(const MachineFunction &MF) { 3879d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 3889d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky return FuncInfo->isCRSpilled(); 3899d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky} 3909d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky 3913f2c047f32c9b488d9c49bb2dc87b979530dab3fHal Finkelstatic bool spillsVRSAVE(const MachineFunction &MF) { 3923f2c047f32c9b488d9c49bb2dc87b979530dab3fHal Finkel const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 3933f2c047f32c9b488d9c49bb2dc87b979530dab3fHal Finkel return FuncInfo->isVRSAVESpilled(); 3943f2c047f32c9b488d9c49bb2dc87b979530dab3fHal Finkel} 3953f2c047f32c9b488d9c49bb2dc87b979530dab3fHal Finkel 3960cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkelstatic bool hasSpills(const MachineFunction &MF) { 3970cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 3980cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel return FuncInfo->hasSpills(); 3990cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel} 4000cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel 401324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkelstatic bool hasNonRISpills(const MachineFunction &MF) { 402324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 403324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel return FuncInfo->hasNonRISpills(); 404324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel} 405324972904353594ad4a0cdfc79370f85e9fb9c8fHal Finkel 406ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines/// MustSaveLR - Return true if this function requires that we save the LR 407ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines/// register onto the stack in the prolog and restore it in the epilog of the 408ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines/// function. 409ebe69fe11e48d322045d5949c83283927a0d790bStephen Hinesstatic bool MustSaveLR(const MachineFunction &MF, unsigned LR) { 410ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 411ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 412ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // We need a save/restore of LR if there is any def of LR (which is 413ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // defined by calls, including the PIC setup sequence), or if there is 414ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // some use of the LR stack slot (e.g. for builtin_return_address). 415ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // (LR comes in 32 and 64 bit versions.) 416ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); 417ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); 418ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines} 419ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 42033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov/// determineFrameLayout - Determine the size of the frame and maximum call 42133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov/// frame size. 4220cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkelunsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF, 4230cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel bool UpdateMF, 4240cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel bool UseEstimate) const { 42533464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov MachineFrameInfo *MFI = MF.getFrameInfo(); 42633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 42733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // Get the number of bytes to allocate from the FrameInfo 4280cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel unsigned FrameSize = 4290cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize(); 43033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 4319bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt // Get stack alignments. The frame must be aligned to the greatest of these: 4329bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI 4339bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame 434fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1; 435fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel 436fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel const PPCRegisterInfo *RegInfo = 437ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 43833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 43933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // If we are a leaf function, and use up to 224 bytes of stack space, 44033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // don't have a frame pointer, calls, or dynamic alloca then we do not need 441fb6fe0aea2d1adde6d5e86f43797b5795ff2dc36Hal Finkel // to adjust the stack pointer (we fit in the Red Zone). 44265396823305326bcb379e88a95ded318e1da875cBill Schmidt // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate 44365396823305326bcb379e88a95ded318e1da875cBill Schmidt // stackless code if all local vars are reg-allocated. 444ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines bool DisableRedZone = MF.getFunction()->hasFnAttribute(Attribute::NoRedZone); 445ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines unsigned LR = RegInfo->getRARegister(); 44633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov if (!DisableRedZone && 44765396823305326bcb379e88a95ded318e1da875cBill Schmidt (Subtarget.isPPC64() || // 32-bit SVR4, no stack- 44865396823305326bcb379e88a95ded318e1da875cBill Schmidt !Subtarget.isSVR4ABI() || // allocated locals. 449dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines FrameSize == 0) && 45033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov FrameSize <= 224 && // Fits in red zone. 45133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov !MFI->hasVarSizedObjects() && // No dynamic alloca. 45233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov !MFI->adjustsStack() && // No calls. 453ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines !MustSaveLR(MF, LR) && 454fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel !RegInfo->hasBasePointer(MF)) { // No special alignment. 45533464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // No need for frame 4560cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel if (UpdateMF) 4570cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel MFI->setStackSize(0); 4580cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel return 0; 45933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 46033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 46133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // Get the maximum call frame size of all the calls. 46233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 46333464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 464c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines // Maximum call frame needs to be at least big enough for linkage area. 465ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines unsigned minCallFrameSize = getLinkageSize(); 46633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 46733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 46833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 46933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // that allocations will be aligned. 47033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov if (MFI->hasVarSizedObjects()) 47133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 47233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 47333464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // Update maximum call frame size. 4740cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel if (UpdateMF) 4750cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel MFI->setMaxCallFrameSize(maxCallFrameSize); 47633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 47733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // Include call frame size in total. 47833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov FrameSize += maxCallFrameSize; 47933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 48033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // Make sure the frame is aligned. 48133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov FrameSize = (FrameSize + AlignMask) & ~AlignMask; 48233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 48333464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // Update frame info. 4840cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel if (UpdateMF) 4850cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel MFI->setStackSize(FrameSize); 4860cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel 4870cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel return FrameSize; 48833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov} 48933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 490d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov// hasFP - Return true if the specified function actually has a dedicated frame 491d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov// pointer register. 49216c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikovbool PPCFrameLowering::hasFP(const MachineFunction &MF) const { 493d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov const MachineFrameInfo *MFI = MF.getFrameInfo(); 494c8bd78c16ba0489835f2eb6101d9bdb96301cfe7Anton Korobeynikov // FIXME: This is pretty much broken by design: hasFP() might be called really 495c8bd78c16ba0489835f2eb6101d9bdb96301cfe7Anton Korobeynikov // early, before the stack layout was calculated and thus hasFP() might return 496c8bd78c16ba0489835f2eb6101d9bdb96301cfe7Anton Korobeynikov // true or false here depending on the time of call. 497c8bd78c16ba0489835f2eb6101d9bdb96301cfe7Anton Korobeynikov return (MFI->getStackSize()) && needsFP(MF); 498c8bd78c16ba0489835f2eb6101d9bdb96301cfe7Anton Korobeynikov} 499c8bd78c16ba0489835f2eb6101d9bdb96301cfe7Anton Korobeynikov 500c8bd78c16ba0489835f2eb6101d9bdb96301cfe7Anton Korobeynikov// needsFP - Return true if the specified function should have a dedicated frame 501c8bd78c16ba0489835f2eb6101d9bdb96301cfe7Anton Korobeynikov// pointer register. This is true if the function has variable sized allocas or 502c8bd78c16ba0489835f2eb6101d9bdb96301cfe7Anton Korobeynikov// if frame pointer elimination is disabled. 50316c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikovbool PPCFrameLowering::needsFP(const MachineFunction &MF) const { 504c8bd78c16ba0489835f2eb6101d9bdb96301cfe7Anton Korobeynikov const MachineFrameInfo *MFI = MF.getFrameInfo(); 505d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov 506d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov // Naked functions have no stack frame pushed, so we don't have a frame 507d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov // pointer. 508ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines if (MF.getFunction()->hasFnAttribute(Attribute::Naked)) 509d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov return false; 510d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov 5118a8d479214745c82ef00f08d4e4f1c173b5f9ce2Nick Lewycky return MF.getTarget().Options.DisableFramePointerElim(MF) || 5128a8d479214745c82ef00f08d4e4f1c173b5f9ce2Nick Lewycky MFI->hasVarSizedObjects() || 513ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines MFI->hasStackMap() || MFI->hasPatchPoint() || 5148a8d479214745c82ef00f08d4e4f1c173b5f9ce2Nick Lewycky (MF.getTarget().Options.GuaranteedTailCallOpt && 5158a8d479214745c82ef00f08d4e4f1c173b5f9ce2Nick Lewycky MF.getInfo<PPCFunctionInfo>()->hasFastCall()); 516d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov} 517d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov 518e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkelvoid PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const { 519e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkel bool is31 = needsFP(MF); 520e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkel unsigned FPReg = is31 ? PPC::R31 : PPC::R1; 521e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkel unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1; 522e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkel 5230541722de4beb2e53058dbf4ed1ebf0d96ddd6cbHal Finkel const PPCRegisterInfo *RegInfo = 524ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 5250541722de4beb2e53058dbf4ed1ebf0d96ddd6cbHal Finkel bool HasBP = RegInfo->hasBasePointer(MF); 52637ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg; 5270541722de4beb2e53058dbf4ed1ebf0d96ddd6cbHal Finkel unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg; 5280541722de4beb2e53058dbf4ed1ebf0d96ddd6cbHal Finkel 529e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkel for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); 530e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkel BI != BE; ++BI) 531e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkel for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) { 532e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkel --MBBI; 533e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkel for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) { 534e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkel MachineOperand &MO = MBBI->getOperand(I); 535e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkel if (!MO.isReg()) 536e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkel continue; 537e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkel 538e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkel switch (MO.getReg()) { 539e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkel case PPC::FP: 540e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkel MO.setReg(FPReg); 541e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkel break; 542e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkel case PPC::FP8: 543e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkel MO.setReg(FP8Reg); 544e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkel break; 5450541722de4beb2e53058dbf4ed1ebf0d96ddd6cbHal Finkel case PPC::BP: 5460541722de4beb2e53058dbf4ed1ebf0d96ddd6cbHal Finkel MO.setReg(BPReg); 5470541722de4beb2e53058dbf4ed1ebf0d96ddd6cbHal Finkel break; 5480541722de4beb2e53058dbf4ed1ebf0d96ddd6cbHal Finkel case PPC::BP8: 5490541722de4beb2e53058dbf4ed1ebf0d96ddd6cbHal Finkel MO.setReg(BP8Reg); 5500541722de4beb2e53058dbf4ed1ebf0d96ddd6cbHal Finkel break; 5510541722de4beb2e53058dbf4ed1ebf0d96ddd6cbHal Finkel 552e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkel } 553e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkel } 554e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkel } 555e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkel} 556d0c38176690e9602a93a20a43f1bd084564a8116Anton Korobeynikov 557de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/* This function will do the following: 558de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar - If MBB is an entry or exit block, set SR1 and SR2 to R0 and R12 559de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar respectively (defaults recommended by the ABI) and return true 560de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar - If MBB is not an entry block, initialize the register scavenger and look 561de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for available registers. 562de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar - If the defaults (R0/R12) are available, return true 563de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar - If TwoUniqueRegsRequired is set to true, it looks for two unique 564de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar registers. Otherwise, look for a single available register. 565de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar - If the required registers are found, set SR1 and SR2 and return true. 566de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar - If the required registers are not found, set SR2 or both SR1 and SR2 to 567de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar PPC::NoRegister and return false. 568de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 569de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar Note that if both SR1 and SR2 are valid parameters and TwoUniqueRegsRequired 570de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar is not set, this function will attempt to find two different registers, but 571de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar still return true if only one register is available (and set SR1 == SR2). 572de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar*/ 573de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarbool 574de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga NainarPPCFrameLowering::findScratchRegister(MachineBasicBlock *MBB, 575de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool UseAtEnd, 576de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool TwoUniqueRegsRequired, 577de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned *SR1, 578de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned *SR2) const { 579f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar RegScavenger RS; 580de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned R0 = Subtarget.isPPC64() ? PPC::X0 : PPC::R0; 581de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned R12 = Subtarget.isPPC64() ? PPC::X12 : PPC::R12; 582de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 583de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Set the defaults for the two scratch registers. 584de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (SR1) 585de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar *SR1 = R0; 586f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 587de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (SR2) { 588de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar assert (SR1 && "Asking for the second scratch register but not the first?"); 589de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar *SR2 = R12; 590de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 591f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 592de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // If MBB is an entry or exit block, use R0 and R12 as the scratch registers. 593f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if ((UseAtEnd && MBB->isReturnBlock()) || 594f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar (!UseAtEnd && (&MBB->getParent()->front() == MBB))) 595f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar return true; 596f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 597de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar RS.enterBasicBlock(*MBB); 598f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 599f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (UseAtEnd && !MBB->empty()) { 600de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // The scratch register will be used at the end of the block, so must 601de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // consider all registers used within the block 602f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 603f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar MachineBasicBlock::iterator MBBI = MBB->getFirstTerminator(); 604f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar // If no terminator, back iterator up to previous instruction. 605f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (MBBI == MBB->end()) 606f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar MBBI = std::prev(MBBI); 607f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 608f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (MBBI != MBB->begin()) 609f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar RS.forward(MBBI); 610f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar } 611de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 612de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // If the two registers are available, we're all good. 613de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Note that we only return here if both R0 and R12 are available because 614de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // although the function may not require two unique registers, it may benefit 615de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // from having two so we should try to provide them. 616de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (!RS.isRegUsed(R0) && !RS.isRegUsed(R12)) 617f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar return true; 618f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 619de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Get the list of callee-saved registers for the target. 620de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar const PPCRegisterInfo *RegInfo = 621de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 622de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(MBB->getParent()); 623de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 624de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Get all the available registers in the block. 625de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar BitVector BV = RS.getRegsAvailable(Subtarget.isPPC64() ? &PPC::G8RCRegClass : 626de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar &PPC::GPRCRegClass); 627de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 628de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // We shouldn't use callee-saved registers as scratch registers as they may be 629de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // available when looking for a candidate block for shrink wrapping but not 630de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // available when the actual prologue/epilogue is being emitted because they 631de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // were added as live-in to the prologue block by PrologueEpilogueInserter. 632de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (int i = 0; CSRegs[i]; ++i) 633de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar BV.reset(CSRegs[i]); 634de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 635de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Set the first scratch register to the first available one. 636de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (SR1) { 637de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar int FirstScratchReg = BV.find_first(); 638de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar *SR1 = FirstScratchReg == -1 ? (unsigned)PPC::NoRegister : FirstScratchReg; 639de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 640f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 641de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // If there is another one available, set the second scratch register to that. 642de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Otherwise, set it to either PPC::NoRegister if this function requires two 643de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // or to whatever SR1 is set to if this function doesn't require two. 644de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (SR2) { 645de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar int SecondScratchReg = BV.find_next(*SR1); 646de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (SecondScratchReg != -1) 647de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar *SR2 = SecondScratchReg; 648de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar else 649de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar *SR2 = TwoUniqueRegsRequired ? (unsigned)PPC::NoRegister : *SR1; 650de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 651de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 652de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Now that we've done our best to provide both registers, double check 653de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // whether we were unable to provide enough. 654de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (BV.count() < (TwoUniqueRegsRequired ? 2U : 1U)) 655de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return false; 656f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 657f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar return true; 658f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar} 659f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 660de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// We need a scratch register for spilling LR and for spilling CR. By default, 661de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// we use two scratch registers to hide latency. However, if only one scratch 662de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// register is available, we can adjust for that by not overlapping the spill 663de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// code. However, if we need to realign the stack (i.e. have a base pointer) 664de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// and the stack frame is large, we need two scratch registers. 665de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarbool 666de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga NainarPPCFrameLowering::twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const { 667de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar const PPCRegisterInfo *RegInfo = 668de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 669de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineFunction &MF = *(MBB->getParent()); 670de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool HasBP = RegInfo->hasBasePointer(MF); 671de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned FrameSize = determineFrameLayout(MF, false); 672de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar int NegFrameSize = -FrameSize; 673de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool IsLargeFrame = !isInt<16>(NegFrameSize); 674de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineFrameInfo *MFI = MF.getFrameInfo(); 675de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned MaxAlign = MFI->getMaxAlignment(); 676de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 677de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return IsLargeFrame && HasBP && MaxAlign > 1; 678de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar} 679de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 680f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainarbool PPCFrameLowering::canUseAsPrologue(const MachineBasicBlock &MBB) const { 681f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB); 682f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 683de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return findScratchRegister(TmpMBB, false, 684de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar twoUniqueScratchRegsRequired(TmpMBB)); 685f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar} 686f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 687f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainarbool PPCFrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const { 688f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB); 689f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 690de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return findScratchRegister(TmpMBB, true); 691f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar} 692f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 6936948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainarvoid PPCFrameLowering::emitPrologue(MachineFunction &MF, 6946948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar MachineBasicBlock &MBB) const { 69533464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov MachineBasicBlock::iterator MBBI = MBB.begin(); 69633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov MachineFrameInfo *MFI = MF.getFrameInfo(); 69733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov const PPCInstrInfo &TII = 698ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 699fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel const PPCRegisterInfo *RegInfo = 700ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 70133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 70233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov MachineModuleInfo &MMI = MF.getMMI(); 70399cb622041a0839c7dfcf0263c5102a305a0fdb5Bill Wendling const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); 70433464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov DebugLoc dl; 705ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines bool needsCFI = MMI.hasDebugInfo() || 706fc2bb8c4448fa884d79e437cc2d2627a7d7740a8Rafael Espindola MF.getFunction()->needsUnwindTableEntry(); 70733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 7089bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt // Get processor type. 7099bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt bool isPPC64 = Subtarget.isPPC64(); 7109bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt // Get the ABI. 7119bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt bool isSVR4ABI = Subtarget.isSVR4ABI(); 71237ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines bool isELFv2ABI = Subtarget.isELFv2ABI(); 713ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines assert((Subtarget.isDarwinABI() || isSVR4ABI) && 7149bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt "Currently only Darwin and SVR4 ABIs are supported for PowerPC."); 7159bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt 71633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 71733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // process it. 7189bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt if (!isSVR4ABI) 719a5d0ab555384baa293b06686bec5a01fb9638ca3Bill Schmidt for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 720a5d0ab555384baa293b06686bec5a01fb9638ca3Bill Schmidt if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 721a5d0ab555384baa293b06686bec5a01fb9638ca3Bill Schmidt HandleVRSaveUpdate(MBBI, TII); 722a5d0ab555384baa293b06686bec5a01fb9638ca3Bill Schmidt break; 723a5d0ab555384baa293b06686bec5a01fb9638ca3Bill Schmidt } 72433464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 72533464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 726f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar // Move MBBI back to the beginning of the prologue block. 72733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov MBBI = MBB.begin(); 72833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 72933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // Work out frame sizes. 7300cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel unsigned FrameSize = determineFrameLayout(MF); 73133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov int NegFrameSize = -FrameSize; 732fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel if (!isInt<32>(NegFrameSize)) 733fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel llvm_unreachable("Unhandled stack size!"); 73433464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 735e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkel if (MFI->isFrameAddressTaken()) 736e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkel replaceFPWithRealFP(MF); 737e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6Hal Finkel 73833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // Check if the link register (LR) must be saved. 73933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 74033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov bool MustSaveLR = FI->mustSaveLR(); 741a0ec3f9b7b826b9b40b80199923b664bad808cceCraig Topper const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs(); 742de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool MustSaveCR = !MustSaveCRs.empty(); 7436af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt // Do we have a frame pointer and/or base pointer for this function? 744c8bd78c16ba0489835f2eb6101d9bdb96301cfe7Anton Korobeynikov bool HasFP = hasFP(MF); 745fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel bool HasBP = RegInfo->hasBasePointer(MF); 74633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 7476af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1; 74837ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines unsigned BPReg = RegInfo->getBaseRegister(MF); 7496af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 7506af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR; 751f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar unsigned ScratchReg = 0; 7526af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg 7536af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.) 7546af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8 7556af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt : PPC::MFLR ); 7566af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD 7576af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt : PPC::STW ); 7586af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU 7596af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt : PPC::STWU ); 7606af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX 7616af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt : PPC::STWUX); 7626af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8 7636af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt : PPC::LIS ); 7646af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8 7656af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt : PPC::ORI ); 7666af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8 7676af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt : PPC::OR ); 7686af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8 7696af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt : PPC::SUBFC); 7706af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8 7716af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt : PPC::SUBFIC); 7726af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt 7739bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt // Regarding this assert: Even though LR is saved in the caller's frame (i.e., 7749bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no 7759bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt // Red Zone, an asynchronous event (a form of "callee") could claim a frame & 7769bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR. 7779bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) && 7789bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4."); 7799bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt 780de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Using the same bool variable as below to supress compiler warnings. 781de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool SingleScratchReg = 782de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar findScratchRegister(&MBB, false, twoUniqueScratchRegsRequired(&MBB), 783de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar &ScratchReg, &TempReg); 784de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar assert(SingleScratchReg && 785de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar "Required number of registers not available in this block"); 786de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 787de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar SingleScratchReg = ScratchReg == TempReg; 788de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 789ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines int LROffset = getReturnSaveOffset(); 79033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 79133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov int FPOffset = 0; 79233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov if (HasFP) { 7939bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt if (isSVR4ABI) { 79433464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov MachineFrameInfo *FFI = MF.getFrameInfo(); 79533464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov int FPIndex = FI->getFramePointerSaveIndex(); 79633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov assert(FPIndex && "No Frame Pointer Save Slot!"); 79733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov FPOffset = FFI->getObjectOffset(FPIndex); 79833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } else { 799ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines FPOffset = getFramePointerSaveOffset(); 80033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 80133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 80233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 803fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel int BPOffset = 0; 804fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel if (HasBP) { 8059bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt if (isSVR4ABI) { 806fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel MachineFrameInfo *FFI = MF.getFrameInfo(); 807fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel int BPIndex = FI->getBasePointerSaveIndex(); 808fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel assert(BPIndex && "No Base Pointer Save Slot!"); 809fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel BPOffset = FFI->getObjectOffset(BPIndex); 810fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel } else { 811ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines BPOffset = getBasePointerSaveOffset(); 812fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel } 813fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel } 814fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel 815ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines int PBPOffset = 0; 816ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines if (FI->usesPICBase()) { 817ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines MachineFrameInfo *FFI = MF.getFrameInfo(); 818ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines int PBPIndex = FI->getPICBasePointerSaveIndex(); 819ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines assert(PBPIndex && "No PIC Base Pointer Save Slot!"); 820ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines PBPOffset = FFI->getObjectOffset(PBPIndex); 821ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines } 822ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 8239bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt // Get stack alignments. 8249bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt unsigned MaxAlign = MFI->getMaxAlignment(); 8259bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt if (HasBP && MaxAlign > 1) 8269bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 8279bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt "Invalid alignment!"); 8289bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt 8299bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt // Frames of 32KB & larger require special handling because they cannot be 8309bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt // indexed into with a simple STDU/STWU/STD/STW immediate offset operand. 8319bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt bool isLargeFrame = !isInt<16>(NegFrameSize); 8329bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt 833de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar assert((isPPC64 || !MustSaveCR) && 834de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar "Prologue CR saving supported only in 64-bit mode"); 835de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 836de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // If we need to spill the CR and the LR but we don't have two separate 837de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // registers available, we must spill them one at a time 838de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (MustSaveCR && SingleScratchReg && MustSaveLR) { 839de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // In the ELFv2 ABI, we are not required to save all CR fields. 840de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // If only one or two CR fields are clobbered, it is more efficient to use 841de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // mfocrf to selectively save just those fields, because mfocrf has short 842de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // latency compares to mfcr. 843de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned MfcrOpcode = PPC::MFCR8; 844de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned CrState = RegState::ImplicitKill; 845de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (isELFv2ABI && MustSaveCRs.size() == 1) { 846de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MfcrOpcode = PPC::MFOCRF8; 847de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar CrState = RegState::Kill; 848de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 849de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineInstrBuilder MIB = 850de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg); 851de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 852de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MIB.addReg(MustSaveCRs[i], CrState); 853de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8)) 854de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar .addReg(TempReg, getKillRegState(true)) 855de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar .addImm(8) 856de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar .addReg(SPReg); 857de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 858de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 8596af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt if (MustSaveLR) 8606af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg); 86133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 862de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (MustSaveCR && 863de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar !(SingleScratchReg && MustSaveLR)) { // will only occur for PPC64 864de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // In the ELFv2 ABI, we are not required to save all CR fields. 865de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // If only one or two CR fields are clobbered, it is more efficient to use 866de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // mfocrf to selectively save just those fields, because mfocrf has short 867de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // latency compares to mfcr. 868de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned MfcrOpcode = PPC::MFCR8; 869de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned CrState = RegState::ImplicitKill; 870de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (isELFv2ABI && MustSaveCRs.size() == 1) { 871de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MfcrOpcode = PPC::MFOCRF8; 872de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar CrState = RegState::Kill; 873de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 8746af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt MachineInstrBuilder MIB = 875de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg); 8766af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 877de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MIB.addReg(MustSaveCRs[i], CrState); 87833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 87933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 8806af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt if (HasFP) 8816af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 8826af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, StoreInst) 8836af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(FPReg) 8846af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addImm(FPOffset) 8856af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(SPReg); 8866af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt 887ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines if (FI->usesPICBase()) 888ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 889ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines BuildMI(MBB, MBBI, dl, StoreInst) 890ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines .addReg(PPC::R30) 891ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines .addImm(PBPOffset) 892ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines .addReg(SPReg); 893ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 8946af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt if (HasBP) 8956af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 8966af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, StoreInst) 8976af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(BPReg) 8986af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addImm(BPOffset) 8996af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(SPReg); 9006af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt 9016af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt if (MustSaveLR) 9026af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 9036af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, StoreInst) 9046af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(ScratchReg) 9056af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addImm(LROffset) 9066af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(SPReg); 9076af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt 908de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (MustSaveCR && 909de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64 9106af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8)) 9116af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(TempReg, getKillRegState(true)) 9126af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addImm(8) 9136af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(SPReg); 9146af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt 9159bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt // Skip the rest if this is a leaf function & all spills fit in the Red Zone. 91633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov if (!FrameSize) return; 91733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 91833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // Adjust stack pointer: r1 += NegFrameSize. 91933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // If there is a preferred stack alignment, align R1 now 920fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel 9216af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt if (HasBP) { 9226af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt // Save a copy of r1 as the base pointer. 9236af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, OrInst, BPReg) 9246af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(SPReg) 9256af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(SPReg); 9266af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt } 9276af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt 928de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // This condition must be kept in sync with canUseAsPrologue. 9296af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt if (HasBP && MaxAlign > 1) { 9306af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt if (isPPC64) 9316af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg) 9326af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(SPReg) 9336af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addImm(0) 9346af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addImm(64 - Log2_32(MaxAlign)); 9356af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt else // PPC32... 9366af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg) 9376af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(SPReg) 93833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov .addImm(0) 93933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov .addImm(32 - Log2_32(MaxAlign)) 94033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov .addImm(31); 9416af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt if (!isLargeFrame) { 9426af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg) 9436af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(ScratchReg, RegState::Kill) 9446af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addImm(NegFrameSize); 94533464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } else { 946de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar assert(!SingleScratchReg && "Only a single scratch reg available"); 9476af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg) 94833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov .addImm(NegFrameSize >> 16); 9496af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, OrImmInst, TempReg) 9506af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(TempReg, RegState::Kill) 95133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov .addImm(NegFrameSize & 0xFFFF); 9526af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg) 9536af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(ScratchReg, RegState::Kill) 9546af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(TempReg, RegState::Kill); 955fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel } 9566af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg) 9576af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(SPReg, RegState::Kill) 9586af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(SPReg) 9596af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(ScratchReg); 960fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel 9616af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt } else if (!isLargeFrame) { 9626af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg) 9636af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(SPReg) 9646af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addImm(NegFrameSize) 9656af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(SPReg); 9669bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt 9676af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt } else { 9686af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg) 9696af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addImm(NegFrameSize >> 16); 9706af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg) 9716af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(ScratchReg, RegState::Kill) 9726af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addImm(NegFrameSize & 0xFFFF); 9736af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg) 9746af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(SPReg, RegState::Kill) 9756af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(SPReg) 9766af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(ScratchReg); 97733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 97833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 979ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // Add Call Frame Information for the instructions we generated above. 980ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines if (needsCFI) { 981ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines unsigned CFIIndex; 982ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 983ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines if (HasBP) { 984ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // Define CFA in terms of BP. Do this in preference to using FP/SP, 985ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // because if the stack needed aligning then CFA won't be at a fixed 986ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // offset from FP/SP. 987ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines unsigned Reg = MRI->getDwarfRegNum(BPReg, true); 988ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines CFIIndex = MMI.addFrameInst( 989ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines MCCFIInstruction::createDefCfaRegister(nullptr, Reg)); 990ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines } else { 991ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // Adjust the definition of CFA to account for the change in SP. 992ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines assert(NegFrameSize); 993ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines CFIIndex = MMI.addFrameInst( 994ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize)); 995ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines } 996dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 997dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines .addCFIIndex(CFIIndex); 99833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 99933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov if (HasFP) { 1000ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // Describe where FP was saved, at a fixed offset from CFA. 10016af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt unsigned Reg = MRI->getDwarfRegNum(FPReg, true); 100236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines CFIIndex = MMI.addFrameInst( 100336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MCCFIInstruction::createOffset(nullptr, Reg, FPOffset)); 1004dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 100536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines .addCFIIndex(CFIIndex); 100633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 100733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 1008ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines if (FI->usesPICBase()) { 1009ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // Describe where FP was saved, at a fixed offset from CFA. 1010ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true); 1011ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines CFIIndex = MMI.addFrameInst( 1012ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines MCCFIInstruction::createOffset(nullptr, Reg, PBPOffset)); 1013ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 1014ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines .addCFIIndex(CFIIndex); 1015ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines } 1016ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 1017fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel if (HasBP) { 1018ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // Describe where BP was saved, at a fixed offset from CFA. 10196af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt unsigned Reg = MRI->getDwarfRegNum(BPReg, true); 102036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines CFIIndex = MMI.addFrameInst( 102136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MCCFIInstruction::createOffset(nullptr, Reg, BPOffset)); 1022dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 102336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines .addCFIIndex(CFIIndex); 1024fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel } 1025fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel 102633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov if (MustSaveLR) { 1027ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // Describe where LR was saved, at a fixed offset from CFA. 10286af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt unsigned Reg = MRI->getDwarfRegNum(LRReg, true); 102936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines CFIIndex = MMI.addFrameInst( 103036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MCCFIInstruction::createOffset(nullptr, Reg, LROffset)); 1031dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 103236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines .addCFIIndex(CFIIndex); 103333464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 103433464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 103533464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 103633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // If there is a frame pointer, copy R1 into R31 103733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov if (HasFP) { 10386af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, OrInst, FPReg) 10396af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(SPReg) 10406af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(SPReg); 104133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 1042ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines if (!HasBP && needsCFI) { 1043ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // Change the definition of CFA from SP+offset to FP+offset, because SP 1044ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // will change at every alloca. 10456af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt unsigned Reg = MRI->getDwarfRegNum(FPReg, true); 104636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines unsigned CFIIndex = MMI.addFrameInst( 104736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MCCFIInstruction::createDefCfaRegister(nullptr, Reg)); 104836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 1049dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 105036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines .addCFIIndex(CFIIndex); 105133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 105233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 105333464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 1054ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines if (needsCFI) { 1055ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // Describe where callee saved registers were saved, at fixed offsets from 1056ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // CFA. 105733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 105833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 105933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov unsigned Reg = CSI[I].getReg(); 106033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 10616e032942cf58d1c41f88609a1cec74eb74940ecdRafael Espindola 10626e032942cf58d1c41f88609a1cec74eb74940ecdRafael Espindola // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just 10636e032942cf58d1c41f88609a1cec74eb74940ecdRafael Espindola // subregisters of CR2. We just need to emit a move of CR2. 1064c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper if (PPC::CRBITRCRegClass.contains(Reg)) 10656e032942cf58d1c41f88609a1cec74eb74940ecdRafael Espindola continue; 10666e032942cf58d1c41f88609a1cec74eb74940ecdRafael Espindola 10679d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // For SVR4, don't emit a move for the CR spill slot if we haven't 10689d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // spilled CRs. 10699bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4) 1070de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar && !MustSaveCR) 10719bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt continue; 10729d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky 10739d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // For 64-bit SVR4 when we have spilled CRs, the spill location 10749d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // is SP+8, not a frame-relative slot. 10759bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 107637ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for 107737ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // the whole CR word. In the ELFv2 ABI, every CR that was 107837ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines // actually saved gets its own CFI record. 107937ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2; 108036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( 108137ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines nullptr, MRI->getDwarfRegNum(CRReg, true), 8)); 1082dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 108336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines .addCFIIndex(CFIIndex); 10849bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt continue; 10859d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky } 10869d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky 10879d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 108836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( 108936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines nullptr, MRI->getDwarfRegNum(Reg, true), Offset)); 1090dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) 109136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines .addCFIIndex(CFIIndex); 109233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 109333464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 109433464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov} 109533464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 109616c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikovvoid PPCFrameLowering::emitEpilogue(MachineFunction &MF, 1097f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar MachineBasicBlock &MBB) const { 1098f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator(); 1099f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar DebugLoc dl; 1100f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 1101f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (MBBI != MBB.end()) 1102f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar dl = MBBI->getDebugLoc(); 1103f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 110433464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov const PPCInstrInfo &TII = 1105ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 1106fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel const PPCRegisterInfo *RegInfo = 1107ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 110833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 11099bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt // Get alignment info so we know how to restore the SP. 111033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov const MachineFrameInfo *MFI = MF.getFrameInfo(); 111133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 111233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // Get the number of bytes allocated from the FrameInfo. 111333464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov int FrameSize = MFI->getStackSize(); 111433464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 111533464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // Get processor type. 111633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov bool isPPC64 = Subtarget.isPPC64(); 11179bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt // Get the ABI. 11189bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt bool isSVR4ABI = Subtarget.isSVR4ABI(); 11199bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt 112033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // Check if the link register (LR) has been saved. 112133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 112233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov bool MustSaveLR = FI->mustSaveLR(); 1123a0ec3f9b7b826b9b40b80199923b664bad808cceCraig Topper const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs(); 1124de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool MustSaveCR = !MustSaveCRs.empty(); 11256af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt // Do we have a frame pointer and/or base pointer for this function? 1126c8bd78c16ba0489835f2eb6101d9bdb96301cfe7Anton Korobeynikov bool HasFP = hasFP(MF); 1127fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel bool HasBP = RegInfo->hasBasePointer(MF); 112833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 11296af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1; 113037ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines unsigned BPReg = RegInfo->getBaseRegister(MF); 11316af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 1132f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar unsigned ScratchReg = 0; 11336af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg 11346af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8 11356af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt : PPC::MTLR ); 11366af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD 11376af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt : PPC::LWZ ); 11386af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8 11396af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt : PPC::LIS ); 11406af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8 11416af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt : PPC::ORI ); 11426af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8 11436af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt : PPC::ADDI ); 11446af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8 11456af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt : PPC::ADD4 ); 1146de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 1147ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines int LROffset = getReturnSaveOffset(); 114833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 114933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov int FPOffset = 0; 1150f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 1151de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Using the same bool variable as below to supress compiler warnings. 1152de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool SingleScratchReg = findScratchRegister(&MBB, true, false, &ScratchReg, 1153de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar &TempReg); 1154de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar assert(SingleScratchReg && 1155de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar "Could not find an available scratch register"); 1156de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 1157de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar SingleScratchReg = ScratchReg == TempReg; 1158de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 115933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov if (HasFP) { 11609bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt if (isSVR4ABI) { 116133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov MachineFrameInfo *FFI = MF.getFrameInfo(); 116233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov int FPIndex = FI->getFramePointerSaveIndex(); 116333464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov assert(FPIndex && "No Frame Pointer Save Slot!"); 116433464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov FPOffset = FFI->getObjectOffset(FPIndex); 116533464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } else { 1166ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines FPOffset = getFramePointerSaveOffset(); 116733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 116833464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 116933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 1170fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel int BPOffset = 0; 1171fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel if (HasBP) { 11729bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt if (isSVR4ABI) { 1173fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel MachineFrameInfo *FFI = MF.getFrameInfo(); 1174fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel int BPIndex = FI->getBasePointerSaveIndex(); 1175fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel assert(BPIndex && "No Base Pointer Save Slot!"); 1176fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel BPOffset = FFI->getObjectOffset(BPIndex); 1177fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel } else { 1178ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines BPOffset = getBasePointerSaveOffset(); 1179fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel } 1180fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel } 1181fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel 1182ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines int PBPOffset = 0; 1183ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines if (FI->usesPICBase()) { 1184ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines MachineFrameInfo *FFI = MF.getFrameInfo(); 1185ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines int PBPIndex = FI->getPICBasePointerSaveIndex(); 1186ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines assert(PBPIndex && "No PIC Base Pointer Save Slot!"); 1187ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines PBPOffset = FFI->getObjectOffset(PBPIndex); 1188ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines } 1189ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 1190f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar bool IsReturnBlock = (MBBI != MBB.end() && MBBI->isReturn()); 1191f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 1192f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (IsReturnBlock) { 1193f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar unsigned RetOpcode = MBBI->getOpcode(); 1194f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar bool UsesTCRet = RetOpcode == PPC::TCRETURNri || 1195f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar RetOpcode == PPC::TCRETURNdi || 1196f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar RetOpcode == PPC::TCRETURNai || 1197f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar RetOpcode == PPC::TCRETURNri8 || 1198f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar RetOpcode == PPC::TCRETURNdi8 || 1199f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar RetOpcode == PPC::TCRETURNai8; 1200f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 1201f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (UsesTCRet) { 1202f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar int MaxTCRetDelta = FI->getTailCallSPDelta(); 1203f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar MachineOperand &StackAdjust = MBBI->getOperand(1); 1204f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar assert(StackAdjust.isImm() && "Expecting immediate value."); 1205f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar // Adjust stack pointer. 1206f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar int StackAdj = StackAdjust.getImm(); 1207f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar int Delta = StackAdj - MaxTCRetDelta; 1208f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar assert((Delta >= 0) && "Delta must be positive"); 1209f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (MaxTCRetDelta>0) 1210f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar FrameSize += (StackAdj +Delta); 1211f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar else 1212f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar FrameSize += StackAdj; 1213f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar } 121433464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 121533464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 12169bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt // Frames of 32KB & larger require special handling because they cannot be 12179bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt // indexed into with a simple LD/LWZ immediate offset operand. 12189bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt bool isLargeFrame = !isInt<16>(FrameSize); 12199bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt 122033464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov if (FrameSize) { 12219bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt // In the prologue, the loaded (or persistent) stack pointer value is offset 12229bb6c81683393363ed1ff8c66397f2d944c0966bBill Schmidt // by the STDU/STDUX/STWU/STWUX instruction. Add this offset back now. 12236af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt 12246af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt // If this function contained a fastcc call and GuaranteedTailCallOpt is 12256af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt // enabled (=> hasFastCall()==true) the fastcc call might contain a tail 12266af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt // call which invalidates the stack pointer value in SP(0). So we use the 12276af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt // value of R31 in this case. 12286af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt if (FI->hasFastCall()) { 12296af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt assert(HasFP && "Expecting a valid frame pointer."); 12306af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt if (!isLargeFrame) { 12316af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) 12326af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(FPReg).addImm(FrameSize); 123333464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } else { 12346af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg) 12356af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addImm(FrameSize >> 16); 12366af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg) 12376af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(ScratchReg, RegState::Kill) 12386af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addImm(FrameSize & 0xFFFF); 12396af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, AddInst) 12406af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(SPReg) 12416af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(FPReg) 12426af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(ScratchReg); 124333464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 12446af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt } else if (!isLargeFrame && !HasBP && !MFI->hasVarSizedObjects()) { 12456af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) 12466af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(SPReg) 12476af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addImm(FrameSize); 12486af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt } else { 12496af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, LoadInst, SPReg) 12506af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addImm(0) 12516af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(SPReg); 125233464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 12536af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt } 125433464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 1255de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar assert((isPPC64 || !MustSaveCR) && 1256de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar "Epilogue CR restoring supported only in 64-bit mode"); 1257de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 1258de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // If we need to save both the LR and the CR and we only have one available 1259de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // scratch register, we must do them one at a time. 1260de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (MustSaveCR && SingleScratchReg && MustSaveLR) { 1261de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg) 1262de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar .addImm(8) 1263de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar .addReg(SPReg); 1264de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 1265de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i]) 1266de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar .addReg(TempReg, getKillRegState(i == e-1)); 1267de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 1268de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 12696af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt if (MustSaveLR) 12706af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg) 12716af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addImm(LROffset) 12726af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(SPReg); 1273fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel 1274de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (MustSaveCR && 1275de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64 12766af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg) 12776af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addImm(8) 12786af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(SPReg); 127933464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 12806af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt if (HasFP) 12816af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, LoadInst, FPReg) 12826af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addImm(FPOffset) 12836af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(SPReg); 1284fb6fe0aea2d1adde6d5e86f43797b5795ff2dc36Hal Finkel 1285ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines if (FI->usesPICBase()) 1286ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. 1287ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines BuildMI(MBB, MBBI, dl, LoadInst) 1288ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines .addReg(PPC::R30) 1289ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines .addImm(PBPOffset) 1290ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines .addReg(SPReg); 1291ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 12926af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt if (HasBP) 12936af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, LoadInst, BPReg) 12946af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addImm(BPOffset) 12956af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(SPReg); 129633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 1297de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (MustSaveCR && 1298de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64 12996af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 13006af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i]) 13016af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(TempReg, getKillRegState(i == e-1)); 1302fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel 13036af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt if (MustSaveLR) 13046af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg); 130533464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov 130633464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // Callee pop calling convention. Pop parameter/linkage area. Used for tail 130733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov // call optimization 1308f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (IsReturnBlock) { 1309f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar unsigned RetOpcode = MBBI->getOpcode(); 1310f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (MF.getTarget().Options.GuaranteedTailCallOpt && 1311f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) && 1312f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar MF.getFunction()->getCallingConv() == CallingConv::Fast) { 1313f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 1314f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar unsigned CallerAllocatedAmt = FI->getMinReservedArea(); 1315f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 1316f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) { 1317f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) 1318f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar .addReg(SPReg).addImm(CallerAllocatedAmt); 1319f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar } else { 1320f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg) 132133464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov .addImm(CallerAllocatedAmt >> 16); 1322f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg) 13236af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(ScratchReg, RegState::Kill) 132433464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov .addImm(CallerAllocatedAmt & 0xFFFF); 1325f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar BuildMI(MBB, MBBI, dl, AddInst) 13266af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(SPReg) 132733464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov .addReg(FPReg) 13286af35e95765e2d577919714dfbdac3ebf84cac78Bill Schmidt .addReg(ScratchReg); 1329f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar } 1330de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } else { 1331de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar createTailCallBranchInstr(MBB); 1332f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar } 133333464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov } 133433464912237efaa0ed7060829e66b59055bdd48bAnton Korobeynikov} 1335d9e3385ced2dc887e2fe8e1c071bd2611e4d3edeAnton Korobeynikov 1336de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarvoid PPCFrameLowering::createTailCallBranchInstr(MachineBasicBlock &MBB) const { 1337de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator(); 1338de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar DebugLoc dl; 1339de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 1340de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (MBBI != MBB.end()) 1341de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar dl = MBBI->getDebugLoc(); 1342de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 1343de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar const PPCInstrInfo &TII = 1344de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 1345de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 1346de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Create branch instruction for pseudo tail call return instruction 1347de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned RetOpcode = MBBI->getOpcode(); 1348de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (RetOpcode == PPC::TCRETURNdi) { 1349de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MBBI = MBB.getLastNonDebugInstr(); 1350de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineOperand &JumpTarget = MBBI->getOperand(0); 1351de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). 1352de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 1353de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } else if (RetOpcode == PPC::TCRETURNri) { 1354de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MBBI = MBB.getLastNonDebugInstr(); 1355de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 1356de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); 1357de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } else if (RetOpcode == PPC::TCRETURNai) { 1358de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MBBI = MBB.getLastNonDebugInstr(); 1359de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineOperand &JumpTarget = MBBI->getOperand(0); 1360de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); 1361de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } else if (RetOpcode == PPC::TCRETURNdi8) { 1362de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MBBI = MBB.getLastNonDebugInstr(); 1363de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineOperand &JumpTarget = MBBI->getOperand(0); 1364de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). 1365de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 1366de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } else if (RetOpcode == PPC::TCRETURNri8) { 1367de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MBBI = MBB.getLastNonDebugInstr(); 1368de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 1369de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); 1370de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } else if (RetOpcode == PPC::TCRETURNai8) { 1371de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MBBI = MBB.getLastNonDebugInstr(); 1372de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineOperand &JumpTarget = MBBI->getOperand(0); 1373de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); 1374de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 1375de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar} 1376de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 1377f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainarvoid PPCFrameLowering::determineCalleeSaves(MachineFunction &MF, 1378f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar BitVector &SavedRegs, 1379f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar RegScavenger *RS) const { 1380f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS); 1381f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 1382fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel const PPCRegisterInfo *RegInfo = 1383ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 138494c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 138594c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov // Save and clear the LR state. 138694c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 138794c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov unsigned LR = RegInfo->getRARegister(); 138894c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov FI->setMustSaveLR(MustSaveLR(MF, LR)); 1389f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar SavedRegs.reset(LR); 139094c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 139194c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov // Save R31 if necessary 139294c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov int FPSI = FI->getFramePointerSaveIndex(); 139394c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov bool isPPC64 = Subtarget.isPPC64(); 139494c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov bool isDarwinABI = Subtarget.isDarwinABI(); 139594c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov MachineFrameInfo *MFI = MF.getFrameInfo(); 139694c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 139794c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov // If the frame pointer save index hasn't been defined yet. 1398c8bd78c16ba0489835f2eb6101d9bdb96301cfe7Anton Korobeynikov if (!FPSI && needsFP(MF)) { 139994c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov // Find out what the fix offset of the frame pointer save area. 1400ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines int FPOffset = getFramePointerSaveOffset(); 140194c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov // Allocate the frame index for frame pointer save area. 140216c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 140394c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov // Save the result. 140494c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov FI->setFramePointerSaveIndex(FPSI); 140594c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov } 140694c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 1407fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel int BPSI = FI->getBasePointerSaveIndex(); 1408fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel if (!BPSI && RegInfo->hasBasePointer(MF)) { 1409ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines int BPOffset = getBasePointerSaveOffset(); 1410fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel // Allocate the frame index for the base pointer save area. 1411fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true); 1412fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel // Save the result. 1413fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel FI->setBasePointerSaveIndex(BPSI); 1414fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel } 1415fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel 1416ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // Reserve stack space for the PIC Base register (R30). 1417ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines // Only used in SVR4 32-bit. 1418ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines if (FI->usesPICBase()) { 1419f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar int PBPSI = MFI->CreateFixedObject(4, -8, true); 1420ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines FI->setPICBasePointerSaveIndex(PBPSI); 1421ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines } 1422ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 142394c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov // Reserve stack space to move the linkage area to in case of a tail call. 142494c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov int TCSPDelta = 0; 14258a8d479214745c82ef00f08d4e4f1c173b5f9ce2Nick Lewycky if (MF.getTarget().Options.GuaranteedTailCallOpt && 14268a8d479214745c82ef00f08d4e4f1c173b5f9ce2Nick Lewycky (TCSPDelta = FI->getTailCallSPDelta()) < 0) { 142716c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true); 142894c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov } 142994c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 1430dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the 14314edd84da1b3f7fd73e96a13b6b7e183ad04ac7c4Bill Schmidt // function uses CR 2, 3, or 4. 1432dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines if (!isPPC64 && !isDarwinABI && 1433f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar (SavedRegs.test(PPC::CR2) || 1434f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar SavedRegs.test(PPC::CR3) || 1435f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar SavedRegs.test(PPC::CR4))) { 14364edd84da1b3f7fd73e96a13b6b7e183ad04ac7c4Bill Schmidt int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true); 14374edd84da1b3f7fd73e96a13b6b7e183ad04ac7c4Bill Schmidt FI->setCRSpillFrameIndex(FrameIdx); 14384edd84da1b3f7fd73e96a13b6b7e183ad04ac7c4Bill Schmidt } 143994c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov} 144094c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 14413080d23fde4981835d8a7faf46c152441fadb11fHal Finkelvoid PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF, 14420cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel RegScavenger *RS) const { 144394c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov // Early exit if not using the SVR4 ABI. 14440cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel if (!Subtarget.isSVR4ABI()) { 14450cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel addScavengingSpillSlot(MF, RS); 144694c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov return; 14470cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel } 144894c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 144994c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov // Get callee saved register information. 145094c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov MachineFrameInfo *FFI = MF.getFrameInfo(); 145194c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); 145294c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 1453de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // If the function is shrink-wrapped, and if the function has a tail call, the 1454de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // tail call might not be in the new RestoreBlock, so real branch instruction 1455de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // won't be generated by emitEpilogue(), because shrink-wrap has chosen new 1456de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // RestoreBlock. So we handle this case here. 1457de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (FFI->getSavePoint() && FFI->hasTailCall()) { 1458de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineBasicBlock *RestoreBlock = FFI->getRestorePoint(); 1459de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (MachineBasicBlock &MBB : MF) { 1460de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (MBB.isReturnBlock() && (&MBB) != RestoreBlock) 1461de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar createTailCallBranchInstr(MBB); 1462de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 1463de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 1464de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 146594c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov // Early exit if no callee saved registers are modified! 1466c8bd78c16ba0489835f2eb6101d9bdb96301cfe7Anton Korobeynikov if (CSI.empty() && !needsFP(MF)) { 14670cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel addScavengingSpillSlot(MF, RS); 146894c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov return; 146994c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov } 147094c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 147194c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov unsigned MinGPR = PPC::R31; 147294c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov unsigned MinG8R = PPC::X31; 147394c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov unsigned MinFPR = PPC::F31; 147494c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov unsigned MinVR = PPC::V31; 147594c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 147694c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov bool HasGPSaveArea = false; 147794c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov bool HasG8SaveArea = false; 147894c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov bool HasFPSaveArea = false; 147994c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov bool HasVRSAVESaveArea = false; 148094c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov bool HasVRSaveArea = false; 148194c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 148294c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov SmallVector<CalleeSavedInfo, 18> GPRegs; 148394c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov SmallVector<CalleeSavedInfo, 18> G8Regs; 148494c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov SmallVector<CalleeSavedInfo, 18> FPRegs; 148594c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov SmallVector<CalleeSavedInfo, 18> VRegs; 148694c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 148794c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 148894c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov unsigned Reg = CSI[i].getReg(); 1489c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper if (PPC::GPRCRegClass.contains(Reg)) { 149094c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov HasGPSaveArea = true; 149194c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 149294c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov GPRegs.push_back(CSI[i]); 149394c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 149494c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov if (Reg < MinGPR) { 149594c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov MinGPR = Reg; 149694c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov } 1497c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::G8RCRegClass.contains(Reg)) { 149894c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov HasG8SaveArea = true; 149994c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 150094c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov G8Regs.push_back(CSI[i]); 150194c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 150294c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov if (Reg < MinG8R) { 150394c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov MinG8R = Reg; 150494c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov } 1505c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::F8RCRegClass.contains(Reg)) { 150694c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov HasFPSaveArea = true; 150794c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 150894c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov FPRegs.push_back(CSI[i]); 150994c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 151094c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov if (Reg < MinFPR) { 151194c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov MinFPR = Reg; 151294c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov } 1513c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::CRBITRCRegClass.contains(Reg) || 1514c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper PPC::CRRCRegClass.contains(Reg)) { 15159d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky ; // do nothing, as we already know whether CRs are spilled 1516c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::VRSAVERCRegClass.contains(Reg)) { 151794c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov HasVRSAVESaveArea = true; 1518c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper } else if (PPC::VRRCRegClass.contains(Reg)) { 151994c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov HasVRSaveArea = true; 152094c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 152194c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov VRegs.push_back(CSI[i]); 152294c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 152394c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov if (Reg < MinVR) { 152494c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov MinVR = Reg; 152594c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov } 152694c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov } else { 152794c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov llvm_unreachable("Unknown RegisterClass!"); 152894c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov } 152994c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov } 153094c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 153194c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); 1532ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); 153394c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 153494c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov int64_t LowerBound = 0; 153594c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 153694c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov // Take into account stack space reserved for tail calls. 153794c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov int TCSPDelta = 0; 15388a8d479214745c82ef00f08d4e4f1c173b5f9ce2Nick Lewycky if (MF.getTarget().Options.GuaranteedTailCallOpt && 15398a8d479214745c82ef00f08d4e4f1c173b5f9ce2Nick Lewycky (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { 154094c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov LowerBound = TCSPDelta; 154194c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov } 154294c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 154394c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov // The Floating-point register save area is right below the back chain word 154494c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov // of the previous stack frame. 154594c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov if (HasFPSaveArea) { 154694c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { 154794c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov int FI = FPRegs[i].getFrameIdx(); 154894c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 154994c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 155094c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov } 155194c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 1552aa6047d23d8ed55abd8545f5cbe82cd13cbd756aHal Finkel LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8; 155394c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov } 155494c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 155594c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov // Check whether the frame pointer register is allocated. If so, make sure it 155694c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov // is spilled to the correct offset. 1557c8bd78c16ba0489835f2eb6101d9bdb96301cfe7Anton Korobeynikov if (needsFP(MF)) { 155894c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov HasGPSaveArea = true; 155994c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 156094c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov int FI = PFI->getFramePointerSaveIndex(); 156194c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov assert(FI && "No Frame Pointer Save Slot!"); 156294c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 156394c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 156494c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov } 156594c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 1566ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines if (PFI->usesPICBase()) { 1567ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines HasGPSaveArea = true; 1568ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 1569ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines int FI = PFI->getPICBasePointerSaveIndex(); 1570ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines assert(FI && "No PIC Base Pointer Save Slot!"); 1571ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 1572ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1573ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines } 1574ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines 1575fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel const PPCRegisterInfo *RegInfo = 1576ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo()); 1577fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel if (RegInfo->hasBasePointer(MF)) { 1578fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel HasGPSaveArea = true; 1579fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel 1580fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel int FI = PFI->getBasePointerSaveIndex(); 1581fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel assert(FI && "No Base Pointer Save Slot!"); 1582fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel 1583fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1584fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel } 1585fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753dHal Finkel 158694c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov // General register save area starts right below the Floating-point 158794c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov // register save area. 158894c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov if (HasGPSaveArea || HasG8SaveArea) { 158994c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov // Move general register save area spill slots down, taking into account 159094c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov // the size of the Floating-point register save area. 159194c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { 159294c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov int FI = GPRegs[i].getFrameIdx(); 159394c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 159494c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 159594c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov } 159694c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 159794c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov // Move general register save area spill slots down, taking into account 159894c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov // the size of the Floating-point register save area. 159994c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) { 160094c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov int FI = G8Regs[i].getFrameIdx(); 160194c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 160294c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 160394c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov } 160494c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 160594c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov unsigned MinReg = 1606aa6047d23d8ed55abd8545f5cbe82cd13cbd756aHal Finkel std::min<unsigned>(TRI->getEncodingValue(MinGPR), 1607aa6047d23d8ed55abd8545f5cbe82cd13cbd756aHal Finkel TRI->getEncodingValue(MinG8R)); 160894c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 160994c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov if (Subtarget.isPPC64()) { 161094c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov LowerBound -= (31 - MinReg + 1) * 8; 161194c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov } else { 161294c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov LowerBound -= (31 - MinReg + 1) * 4; 161394c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov } 161494c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov } 161594c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 16169d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // For 32-bit only, the CR save area is below the general register 16179d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // save area. For 64-bit SVR4, the CR save area is addressed relative 16189d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // to the stack pointer and hence does not need an adjustment here. 16199d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // Only CR2 (the first nonvolatile spilled) has an associated frame 16209d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // index so that we have a single uniform save area. 16219d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) { 162294c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov // Adjust the frame index of the CR spill slot. 162394c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 162494c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov unsigned Reg = CSI[i].getReg(); 162594c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 16269d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2) 1627dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Leave Darwin logic as-is. 1628dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines || (!Subtarget.isSVR4ABI() && 1629dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines (PPC::CRBITRCRegClass.contains(Reg) || 1630dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines PPC::CRRCRegClass.contains(Reg)))) { 163194c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov int FI = CSI[i].getFrameIdx(); 163294c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 163394c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 163494c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov } 163594c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov } 163694c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 163794c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov LowerBound -= 4; // The CR save area is always 4 bytes long. 163894c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov } 163994c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 164094c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov if (HasVRSAVESaveArea) { 164194c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov // FIXME SVR4: Is it actually possible to have multiple elements in CSI 164294c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov // which have the VRSAVE register class? 164394c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov // Adjust the frame index of the VRSAVE spill slot. 164494c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 164594c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov unsigned Reg = CSI[i].getReg(); 164694c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 1647c909950c384e8234a7b3c5a76b7f79e3f7012cebCraig Topper if (PPC::VRSAVERCRegClass.contains(Reg)) { 164894c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov int FI = CSI[i].getFrameIdx(); 164994c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 165094c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 165194c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov } 165294c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov } 165394c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 165494c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. 165594c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov } 165694c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 165794c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov if (HasVRSaveArea) { 165894c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov // Insert alignment padding, we need 16-byte alignment. 165994c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov LowerBound = (LowerBound - 15) & ~(15); 166094c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 166194c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 166294c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov int FI = VRegs[i].getFrameIdx(); 166394c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov 166494c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 166594c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov } 166694c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov } 16670cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel 16680cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel addScavengingSpillSlot(MF, RS); 16690cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel} 16700cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel 16710cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkelvoid 16720cfb42adb5072fb19a01dba3ea58a33fd5927947Hal FinkelPPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF, 16730cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel RegScavenger *RS) const { 16740cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 16750cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel // a large stack, which will require scavenging a register to materialize a 16760cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel // large offset. 16770cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel 16780cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel // We need to have a scavenger spill slot for spills if the frame size is 16790cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel // large. In case there is no free register for large-offset addressing, 16800cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel // this slot is used for the necessary emergency spill. Also, we need the 16810cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel // slot for dynamic stack allocations. 16820cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel 16830cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel // The scavenger might be invoked if the frame offset does not fit into 16840cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel // the 16-bit immediate. We don't know the complete frame size here 16850cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel // because we've not yet computed callee-saved register spills or the 16860cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel // needed alignment padding. 16870cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel unsigned StackSize = determineFrameLayout(MF, false, true); 16880cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel MachineFrameInfo *MFI = MF.getFrameInfo(); 16893f2c047f32c9b488d9c49bb2dc87b979530dab3fHal Finkel if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) || 16903f2c047f32c9b488d9c49bb2dc87b979530dab3fHal Finkel hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) { 16910cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 16920cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 16930cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 1694dc3beb90178fc316f63790812b22201884eaa017Hal Finkel RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 16950cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel RC->getAlignment(), 16960cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel false)); 169701f99d29c3010f2891e5edb78182216214017063Hal Finkel 1698aad2a72c285a48e34d89ba69d24eb624f2b09b0eHal Finkel // Might we have over-aligned allocas? 1699aad2a72c285a48e34d89ba69d24eb624f2b09b0eHal Finkel bool HasAlVars = MFI->hasVarSizedObjects() && 1700aad2a72c285a48e34d89ba69d24eb624f2b09b0eHal Finkel MFI->getMaxAlignment() > getStackAlignment(); 1701aad2a72c285a48e34d89ba69d24eb624f2b09b0eHal Finkel 170201f99d29c3010f2891e5edb78182216214017063Hal Finkel // These kinds of spills might need two registers. 1703aad2a72c285a48e34d89ba69d24eb624f2b09b0eHal Finkel if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars) 170401f99d29c3010f2891e5edb78182216214017063Hal Finkel RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 170501f99d29c3010f2891e5edb78182216214017063Hal Finkel RC->getAlignment(), 170601f99d29c3010f2891e5edb78182216214017063Hal Finkel false)); 170701f99d29c3010f2891e5edb78182216214017063Hal Finkel 17080cfb42adb5072fb19a01dba3ea58a33fd5927947Hal Finkel } 170994c5ae08750f314bc3cf1bf882b686244a3927d9Anton Korobeynikov} 17109d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky 1711dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesbool 17129d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman DivackyPPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 1713dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MachineBasicBlock::iterator MI, 1714dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const std::vector<CalleeSavedInfo> &CSI, 1715dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const TargetRegisterInfo *TRI) const { 17169d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky 17179d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // Currently, this function only handles SVR4 32- and 64-bit ABIs. 17189d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // Return false otherwise to maintain pre-existing behavior. 17199d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky if (!Subtarget.isSVR4ABI()) 17209d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky return false; 17219d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky 17229d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky MachineFunction *MF = MBB.getParent(); 17239d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky const PPCInstrInfo &TII = 1724ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 17259d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky DebugLoc DL; 17269d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky bool CRSpilled = false; 172763496f66c5b528a48f8da7714ee3f635f8aadd18Hal Finkel MachineInstrBuilder CRMIB; 1728dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 17299d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 17309d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky unsigned Reg = CSI[i].getReg(); 17316a636a813f33b46b3271ec8517ee1936a0c92c9fHal Finkel // Only Darwin actually uses the VRSAVE register, but it can still appear 17326a636a813f33b46b3271ec8517ee1936a0c92c9fHal Finkel // here if, for example, @llvm.eh.unwind.init() is used. If we're not on 17336a636a813f33b46b3271ec8517ee1936a0c92c9fHal Finkel // Darwin, ignore it. 17346a636a813f33b46b3271ec8517ee1936a0c92c9fHal Finkel if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI()) 17356a636a813f33b46b3271ec8517ee1936a0c92c9fHal Finkel continue; 17366a636a813f33b46b3271ec8517ee1936a0c92c9fHal Finkel 17379d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // CR2 through CR4 are the nonvolatile CR fields. 17389d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4; 17399d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky 17409d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // Add the callee-saved register as live-in; it's killed at the spill. 17419d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky MBB.addLiveIn(Reg); 17429d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky 174363496f66c5b528a48f8da7714ee3f635f8aadd18Hal Finkel if (CRSpilled && IsCRField) { 174463496f66c5b528a48f8da7714ee3f635f8aadd18Hal Finkel CRMIB.addReg(Reg, RegState::ImplicitKill); 174563496f66c5b528a48f8da7714ee3f635f8aadd18Hal Finkel continue; 174663496f66c5b528a48f8da7714ee3f635f8aadd18Hal Finkel } 174763496f66c5b528a48f8da7714ee3f635f8aadd18Hal Finkel 17489d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // Insert the spill to the stack frame. 17499d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky if (IsCRField) { 1750fb6fe0aea2d1adde6d5e86f43797b5795ff2dc36Hal Finkel PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>(); 17519d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky if (Subtarget.isPPC64()) { 1752fb6fe0aea2d1adde6d5e86f43797b5795ff2dc36Hal Finkel // The actual spill will happen at the start of the prologue. 1753fb6fe0aea2d1adde6d5e86f43797b5795ff2dc36Hal Finkel FuncInfo->addMustSaveCR(Reg); 17549d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky } else { 1755fb6fe0aea2d1adde6d5e86f43797b5795ff2dc36Hal Finkel CRSpilled = true; 1756ded53bf4dd499f213334400fa870d0c7896d1d0dBill Schmidt FuncInfo->setSpillsCR(); 1757fb6fe0aea2d1adde6d5e86f43797b5795ff2dc36Hal Finkel 1758dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have 1759dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // the same frame index in PPCRegisterInfo::hasReservedSpillSlot. 1760dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12) 176163496f66c5b528a48f8da7714ee3f635f8aadd18Hal Finkel .addReg(Reg, RegState::ImplicitKill); 176263496f66c5b528a48f8da7714ee3f635f8aadd18Hal Finkel 1763dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MBB.insert(MI, CRMIB); 1764dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW)) 1765dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines .addReg(PPC::R12, 1766dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines getKillRegState(true)), 1767dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines CSI[i].getFrameIdx())); 17689d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky } 17699d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky } else { 17709d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 17719d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky TII.storeRegToStackSlot(MBB, MI, Reg, true, 1772dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines CSI[i].getFrameIdx(), RC, TRI); 17739d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky } 17749d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky } 17759d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky return true; 17769d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky} 17779d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky 17789d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divackystatic void 1779b99c995825a49f0da5af40ee1b61269deb8994b5Hal FinkelrestoreCRs(bool isPPC64, bool is31, 1780b99c995825a49f0da5af40ee1b61269deb8994b5Hal Finkel bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, 1781dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 1782dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) { 17839d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky 17849d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky MachineFunction *MF = MBB.getParent(); 1785ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines const PPCInstrInfo &TII = *MF->getSubtarget<PPCSubtarget>().getInstrInfo(); 17869d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky DebugLoc DL; 17879d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky unsigned RestoreOp, MoveReg; 17889d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky 1789fb6fe0aea2d1adde6d5e86f43797b5795ff2dc36Hal Finkel if (isPPC64) 1790fb6fe0aea2d1adde6d5e86f43797b5795ff2dc36Hal Finkel // This is handled during epilogue generation. 1791fb6fe0aea2d1adde6d5e86f43797b5795ff2dc36Hal Finkel return; 1792fb6fe0aea2d1adde6d5e86f43797b5795ff2dc36Hal Finkel else { 17939d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // 32-bit: FP-relative 17949d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ), 1795dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines PPC::R12), 1796dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines CSI[CSIIndex].getFrameIdx())); 179733efedc0481c4b0d9866ff526eb1161372b5919fUlrich Weigand RestoreOp = PPC::MTOCRF; 17989d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky MoveReg = PPC::R12; 17999d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky } 1800dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 18019d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky if (CR2Spilled) 18029d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2) 1803d957f957eee12cf26a7160e6015f0a7c2629904fHal Finkel .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled))); 18049d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky 18059d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky if (CR3Spilled) 18069d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3) 1807d957f957eee12cf26a7160e6015f0a7c2629904fHal Finkel .addReg(MoveReg, getKillRegState(!CR4Spilled))); 18089d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky 18099d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky if (CR4Spilled) 18109d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4) 1811d957f957eee12cf26a7160e6015f0a7c2629904fHal Finkel .addReg(MoveReg, getKillRegState(true))); 18129d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky} 18139d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky 1814de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga NainarMachineBasicBlock::iterator PPCFrameLowering:: 1815700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli BenderskyeliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 1816700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky MachineBasicBlock::iterator I) const { 1817ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1818700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky if (MF.getTarget().Options.GuaranteedTailCallOpt && 1819700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky I->getOpcode() == PPC::ADJCALLSTACKUP) { 1820700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky // Add (actually subtract) back the amount the callee popped on return. 1821700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky if (int CalleeAmt = I->getOperand(1).getImm()) { 1822700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky bool is64Bit = Subtarget.isPPC64(); 1823700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky CalleeAmt *= -1; 1824700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 1825700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 1826700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 1827700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 1828700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 1829700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 1830700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky MachineInstr *MI = I; 1831de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar const DebugLoc &dl = MI->getDebugLoc(); 1832700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky 1833700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky if (isInt<16>(CalleeAmt)) { 1834700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg) 1835700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky .addReg(StackReg, RegState::Kill) 1836700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky .addImm(CalleeAmt); 1837700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky } else { 1838700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky MachineBasicBlock::iterator MBBI = I; 1839700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 1840700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky .addImm(CalleeAmt >> 16); 1841700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 1842700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky .addReg(TmpReg, RegState::Kill) 1843700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky .addImm(CalleeAmt & 0xFFFF); 1844700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg) 1845700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky .addReg(StackReg, RegState::Kill) 1846700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky .addReg(TmpReg); 1847700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky } 1848700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky } 1849700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky } 1850700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 1851de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return MBB.erase(I); 1852700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky} 1853700ed80d3da5e98e05ceb90e9bfb66058581a6dbEli Bendersky 1854dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesbool 18559d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman DivackyPPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 1856dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MachineBasicBlock::iterator MI, 1857dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const std::vector<CalleeSavedInfo> &CSI, 1858dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const TargetRegisterInfo *TRI) const { 18599d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky 18609d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // Currently, this function only handles SVR4 32- and 64-bit ABIs. 18619d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // Return false otherwise to maintain pre-existing behavior. 18629d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky if (!Subtarget.isSVR4ABI()) 18639d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky return false; 18649d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky 18659d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky MachineFunction *MF = MBB.getParent(); 18669d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky const PPCInstrInfo &TII = 1867ebe69fe11e48d322045d5949c83283927a0d790bStephen Hines *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo()); 18689d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky bool CR2Spilled = false; 18699d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky bool CR3Spilled = false; 18709d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky bool CR4Spilled = false; 18719d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky unsigned CSIIndex = 0; 18729d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky 18739d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // Initialize insertion-point logic; we will be restoring in reverse 18749d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // order of spill. 18759d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky MachineBasicBlock::iterator I = MI, BeforeI = I; 18769d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky bool AtStart = I == MBB.begin(); 18779d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky 18789d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky if (!AtStart) 18799d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky --BeforeI; 18809d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky 18819d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 18829d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky unsigned Reg = CSI[i].getReg(); 18839d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky 18846a636a813f33b46b3271ec8517ee1936a0c92c9fHal Finkel // Only Darwin actually uses the VRSAVE register, but it can still appear 18856a636a813f33b46b3271ec8517ee1936a0c92c9fHal Finkel // here if, for example, @llvm.eh.unwind.init() is used. If we're not on 18866a636a813f33b46b3271ec8517ee1936a0c92c9fHal Finkel // Darwin, ignore it. 18876a636a813f33b46b3271ec8517ee1936a0c92c9fHal Finkel if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI()) 18886a636a813f33b46b3271ec8517ee1936a0c92c9fHal Finkel continue; 18896a636a813f33b46b3271ec8517ee1936a0c92c9fHal Finkel 18909d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky if (Reg == PPC::CR2) { 18919d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky CR2Spilled = true; 18929d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // The spill slot is associated only with CR2, which is the 18939d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // first nonvolatile spilled. Save it here. 18949d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky CSIIndex = i; 18959d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky continue; 18969d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky } else if (Reg == PPC::CR3) { 18979d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky CR3Spilled = true; 18989d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky continue; 18999d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky } else if (Reg == PPC::CR4) { 19009d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky CR4Spilled = true; 19019d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky continue; 19029d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky } else { 19039d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // When we first encounter a non-CR register after seeing at 19049d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // least one CR register, restore all spilled CRs together. 19059d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky if ((CR2Spilled || CR3Spilled || CR4Spilled) 1906dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 1907b99c995825a49f0da5af40ee1b61269deb8994b5Hal Finkel bool is31 = needsFP(*MF); 1908b99c995825a49f0da5af40ee1b61269deb8994b5Hal Finkel restoreCRs(Subtarget.isPPC64(), is31, 1909b99c995825a49f0da5af40ee1b61269deb8994b5Hal Finkel CR2Spilled, CR3Spilled, CR4Spilled, 1910dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MBB, I, CSI, CSIIndex); 1911dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines CR2Spilled = CR3Spilled = CR4Spilled = false; 19129d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky } 19139d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky 19149d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // Default behavior for non-CR saves. 19159d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 19169d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(), 1917dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines RC, TRI); 19189d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky assert(I != MBB.begin() && 1919dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines "loadRegFromStackSlot didn't insert any code!"); 19209d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky } 19219d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky 19229d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // Insert in reverse order. 19239d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky if (AtStart) 19249d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky I = MBB.begin(); 19259d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky else { 19269d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky I = BeforeI; 19279d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky ++I; 1928dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } 19299d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky } 19309d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky 19319d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky // If we haven't yet spilled the CRs, do so now. 1932b99c995825a49f0da5af40ee1b61269deb8994b5Hal Finkel if (CR2Spilled || CR3Spilled || CR4Spilled) { 1933dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool is31 = needsFP(*MF); 1934b99c995825a49f0da5af40ee1b61269deb8994b5Hal Finkel restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled, 1935dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MBB, I, CSI, CSIIndex); 1936b99c995825a49f0da5af40ee1b61269deb8994b5Hal Finkel } 19379d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky 19389d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky return true; 19399d760ae5c6bc1d1482e2824efcf9cb11db1cc16fRoman Divacky} 1940f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 1941f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainarbool PPCFrameLowering::enableShrinkWrapping(const MachineFunction &MF) const { 1942f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar return (MF.getSubtarget<PPCSubtarget>().isSVR4ABI() && 1943f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar MF.getSubtarget<PPCSubtarget>().isPPC64()); 1944f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar} 1945