131d157ae1ac2cd9c787dc3c1d28e64c682803844Jia Liu//===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===// 2a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng// 3a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng// The LLVM Compiler Infrastructure 4a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng// 5a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng// This file is distributed under the University of Illinois Open Source 6a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng// License. See LICENSE.TXT for details. 7a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng// 8a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng//===----------------------------------------------------------------------===// 9a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng// 10a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng// This file provides X86 specific target descriptions. 11a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng// 12a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng//===----------------------------------------------------------------------===// 13a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng 14ed5e3552147830159a1d48d067dfbb49ac9cccfdEvan Cheng#include "X86MCTargetDesc.h" 154b64e8a9e13ba782da2034e1dee52f077bdb759cEvan Cheng#include "InstPrinter/X86ATTInstPrinter.h" 164b64e8a9e13ba782da2034e1dee52f077bdb759cEvan Cheng#include "InstPrinter/X86IntelInstPrinter.h" 17d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "X86MCAsmInfo.h" 18d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/ADT/Triple.h" 197801136b95d1fbe515b9655b73ada39b05a33559Evan Cheng#include "llvm/MC/MCInstrAnalysis.h" 2022fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng#include "llvm/MC/MCInstrInfo.h" 21a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576dEvan Cheng#include "llvm/MC/MCRegisterInfo.h" 22a87e40f16f1c3117412e01107807e490d6fb29bcEvan Cheng#include "llvm/MC/MCStreamer.h" 23ce795dc92f693a855dbf1450570e6aeb69774bccEvan Cheng#include "llvm/MC/MCSubtargetInfo.h" 24d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/MC/MachineLocation.h" 25655b8de7b2ab773a977e0c524307e71354d8af29Craig Topper#include "llvm/Support/ErrorHandling.h" 26d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/Support/Host.h" 273e74d6fdd248e20a280f1dff3da9a6c689c2c4c3Evan Cheng#include "llvm/Support/TargetRegistry.h" 2873f50d9bc3bd46cc0abeba9bb0d46977ba1aea42Evan Cheng 29dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines#if _MSC_VER 30dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines#include <intrin.h> 31dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines#endif 32dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 33dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesusing namespace llvm; 34dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 3573f50d9bc3bd46cc0abeba9bb0d46977ba1aea42Evan Cheng#define GET_REGINFO_MC_DESC 3673f50d9bc3bd46cc0abeba9bb0d46977ba1aea42Evan Cheng#include "X86GenRegisterInfo.inc" 3722fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng 3822fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng#define GET_INSTRINFO_MC_DESC 3922fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng#include "X86GenInstrInfo.inc" 4022fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng 41ce795dc92f693a855dbf1450570e6aeb69774bccEvan Cheng#define GET_SUBTARGETINFO_MC_DESC 42385e930d55f3ecd3c9538823dfa5896a12461845Evan Cheng#include "X86GenSubtargetInfo.inc" 43ce795dc92f693a855dbf1450570e6aeb69774bccEvan Cheng 446948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainarstd::string X86_MC::ParseX86Triple(const Triple &TT) { 451fac6b50ea720d75fc2bf01a288e99f239869e90Nick Lewycky std::string FS; 466948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar if (TT.getArch() == Triple::x86_64) 4736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines FS = "+64bit-mode,-32bit-mode,-16bit-mode"; 486948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar else if (TT.getEnvironment() != Triple::CODE16) 4936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines FS = "-64bit-mode,+32bit-mode,-16bit-mode"; 501fac6b50ea720d75fc2bf01a288e99f239869e90Nick Lewycky else 5136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines FS = "-64bit-mode,-32bit-mode,+16bit-mode"; 5236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 531fac6b50ea720d75fc2bf01a288e99f239869e90Nick Lewycky return FS; 5418fb1d35db9e2160be3a5bd2950f7e0d206bdbb8Evan Cheng} 5518fb1d35db9e2160be3a5bd2950f7e0d206bdbb8Evan Cheng 56f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainarunsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) { 57c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines if (TT.getArch() == Triple::x86_64) 580e6a052331f674dd70e28af41f654a7874405eabEvan Cheng return DWARFFlavour::X86_64; 590e6a052331f674dd70e28af41f654a7874405eabEvan Cheng 60c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines if (TT.isOSDarwin()) 610e6a052331f674dd70e28af41f654a7874405eabEvan Cheng return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic; 62c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hines if (TT.isOSCygMing()) 630e6a052331f674dd70e28af41f654a7874405eabEvan Cheng // Unsupported by now, just quick fallback 640e6a052331f674dd70e28af41f654a7874405eabEvan Cheng return DWARFFlavour::X86_32_Generic; 650e6a052331f674dd70e28af41f654a7874405eabEvan Cheng return DWARFFlavour::X86_32_Generic; 660e6a052331f674dd70e28af41f654a7874405eabEvan Cheng} 670e6a052331f674dd70e28af41f654a7874405eabEvan Cheng 68de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarvoid X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) { 690e6a052331f674dd70e28af41f654a7874405eabEvan Cheng // FIXME: TableGen these. 70de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) { 717abf67a092c0a75d6d1631766d6a8ef14e38d526Michael Liao unsigned SEH = MRI->getEncodingValue(Reg); 720e6a052331f674dd70e28af41f654a7874405eabEvan Cheng MRI->mapLLVMRegToSEHReg(Reg, SEH); 730e6a052331f674dd70e28af41f654a7874405eabEvan Cheng } 74de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 75de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // These CodeView registers are numbered sequentially starting at value 1. 76de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar static const MCPhysReg LowCVRegs[] = { 77de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar X86::AL, X86::CL, X86::DL, X86::BL, X86::AH, X86::CH, 78de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar X86::DH, X86::BH, X86::AX, X86::CX, X86::DX, X86::BX, 79de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar X86::SP, X86::BP, X86::SI, X86::DI, X86::EAX, X86::ECX, 80de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar X86::EDX, X86::EBX, X86::ESP, X86::EBP, X86::ESI, X86::EDI, 81de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar }; 82de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned CVLowRegStart = 1; 83de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (unsigned I = 0; I < array_lengthof(LowCVRegs); ++I) 84de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MRI->mapLLVMRegToCVReg(LowCVRegs[I], I + CVLowRegStart); 85de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 86de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MRI->mapLLVMRegToCVReg(X86::EFLAGS, 34); 87de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 88de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // The x87 registers start at 128 and are numbered sequentially. 89de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned FP0Start = 128; 90de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (unsigned I = 0; I < 8; ++I) 91de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MRI->mapLLVMRegToCVReg(X86::FP0 + I, FP0Start + I); 92de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 93de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // The low 8 XMM registers start at 154 and are numbered sequentially. 94de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned CVXMM0Start = 154; 95de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (unsigned I = 0; I < 8; ++I) 96de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MRI->mapLLVMRegToCVReg(X86::XMM0 + I, CVXMM0Start + I); 97de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 98de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // The high 8 XMM registers start at 252 and are numbered sequentially. 99de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned CVXMM8Start = 252; 100de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (unsigned I = 0; I < 8; ++I) 101de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MRI->mapLLVMRegToCVReg(X86::XMM8 + I, CVXMM8Start + I); 102de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 103de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // FIXME: XMM16 and above from AVX512 not yet documented. 104de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 105de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // AMD64 registers start at 324 and count up. 106de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned CVX64RegStart = 324; 107de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar static const MCPhysReg CVX64Regs[] = { 108de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::RAX, X86::RBX, 109de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBP, X86::RSP, 110de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, 111de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar X86::R14, X86::R15, X86::R8B, X86::R9B, X86::R10B, X86::R11B, 112de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar X86::R12B, X86::R13B, X86::R14B, X86::R15B, X86::R8W, X86::R9W, 113de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar X86::R10W, X86::R11W, X86::R12W, X86::R13W, X86::R14W, X86::R15W, 114de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R13D, 115de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar X86::R14D, X86::R15D, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, 116de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, 117de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 118de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar }; 119de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (unsigned I = 0; I < array_lengthof(CVX64Regs); ++I) 120de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MRI->mapLLVMRegToCVReg(CVX64Regs[I], CVX64RegStart + I); 1210e6a052331f674dd70e28af41f654a7874405eabEvan Cheng} 1220e6a052331f674dd70e28af41f654a7874405eabEvan Cheng 1236948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga NainarMCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT, 1246948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar StringRef CPU, StringRef FS) { 12518fb1d35db9e2160be3a5bd2950f7e0d206bdbb8Evan Cheng std::string ArchFS = X86_MC::ParseX86Triple(TT); 12618fb1d35db9e2160be3a5bd2950f7e0d206bdbb8Evan Cheng if (!FS.empty()) { 12718fb1d35db9e2160be3a5bd2950f7e0d206bdbb8Evan Cheng if (!ArchFS.empty()) 1280c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar ArchFS = (Twine(ArchFS) + "," + FS).str(); 12918fb1d35db9e2160be3a5bd2950f7e0d206bdbb8Evan Cheng else 13018fb1d35db9e2160be3a5bd2950f7e0d206bdbb8Evan Cheng ArchFS = FS; 13118fb1d35db9e2160be3a5bd2950f7e0d206bdbb8Evan Cheng } 13218fb1d35db9e2160be3a5bd2950f7e0d206bdbb8Evan Cheng 13318fb1d35db9e2160be3a5bd2950f7e0d206bdbb8Evan Cheng std::string CPUName = CPU; 134dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines if (CPUName.empty()) 135cc0ddc707d5a7b1dd11141881df0bf4210f8aeeeEvan Cheng CPUName = "generic"; 13618fb1d35db9e2160be3a5bd2950f7e0d206bdbb8Evan Cheng 137f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar return createX86MCSubtargetInfoImpl(TT, CPUName, ArchFS); 138ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng} 139ebdeeab812beec0385b445f3d4c41a114e0d972fEvan Cheng 1401abf2cb59b8d63415780a03329307c0997b2670cEvan Chengstatic MCInstrInfo *createX86MCInstrInfo() { 1411abf2cb59b8d63415780a03329307c0997b2670cEvan Cheng MCInstrInfo *X = new MCInstrInfo(); 1421abf2cb59b8d63415780a03329307c0997b2670cEvan Cheng InitX86MCInstrInfo(X); 143ce795dc92f693a855dbf1450570e6aeb69774bccEvan Cheng return X; 144ce795dc92f693a855dbf1450570e6aeb69774bccEvan Cheng} 145ce795dc92f693a855dbf1450570e6aeb69774bccEvan Cheng 146f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainarstatic MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) { 147f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar unsigned RA = (TT.getArch() == Triple::x86_64) 148f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar ? X86::RIP // Should have dwarf #16. 149f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar : X86::EIP; // Should have dwarf #8. 1500e6a052331f674dd70e28af41f654a7874405eabEvan Cheng 1511abf2cb59b8d63415780a03329307c0997b2670cEvan Cheng MCRegisterInfo *X = new MCRegisterInfo(); 152f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false), 153f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar X86_MC::getDwarfRegFlavour(TT, true), RA); 154de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar X86_MC::initLLVMToSEHAndCVRegMapping(X); 1551abf2cb59b8d63415780a03329307c0997b2670cEvan Cheng return X; 1561abf2cb59b8d63415780a03329307c0997b2670cEvan Cheng} 1571abf2cb59b8d63415780a03329307c0997b2670cEvan Cheng 1586948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainarstatic MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, 1596948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar const Triple &TheTriple) { 1602d28617de2b0b731c08d1af9e830f31e14ac75b4Evan Cheng bool is64Bit = TheTriple.getArch() == Triple::x86_64; 1611abf2cb59b8d63415780a03329307c0997b2670cEvan Cheng 1622d28617de2b0b731c08d1af9e830f31e14ac75b4Evan Cheng MCAsmInfo *MAI; 16336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (TheTriple.isOSBinFormatMachO()) { 1642d28617de2b0b731c08d1af9e830f31e14ac75b4Evan Cheng if (is64Bit) 1652d28617de2b0b731c08d1af9e830f31e14ac75b4Evan Cheng MAI = new X86_64MCAsmInfoDarwin(TheTriple); 1661abf2cb59b8d63415780a03329307c0997b2670cEvan Cheng else 1672d28617de2b0b731c08d1af9e830f31e14ac75b4Evan Cheng MAI = new X86MCAsmInfoDarwin(TheTriple); 16836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines } else if (TheTriple.isOSBinFormatELF()) { 1697bbd6e366b39157445cc921024a987e61ea68c00Andrew Kaylor // Force the use of an ELF container. 1707bbd6e366b39157445cc921024a987e61ea68c00Andrew Kaylor MAI = new X86ELFMCAsmInfo(TheTriple); 171f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar } else if (TheTriple.isWindowsMSVCEnvironment() || 172f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar TheTriple.isWindowsCoreCLREnvironment()) { 173116bc795da4b10773235a89cc251d31651b3851dMichael J. Spencer MAI = new X86MCAsmInfoMicrosoft(TheTriple); 17437ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines } else if (TheTriple.isOSCygMing() || 17537ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines TheTriple.isWindowsItaniumEnvironment()) { 176116bc795da4b10773235a89cc251d31651b3851dMichael J. Spencer MAI = new X86MCAsmInfoGNUCOFF(TheTriple); 1772d28617de2b0b731c08d1af9e830f31e14ac75b4Evan Cheng } else { 1787bbd6e366b39157445cc921024a987e61ea68c00Andrew Kaylor // The default is ELF. 1792d28617de2b0b731c08d1af9e830f31e14ac75b4Evan Cheng MAI = new X86ELFMCAsmInfo(TheTriple); 1801abf2cb59b8d63415780a03329307c0997b2670cEvan Cheng } 1811abf2cb59b8d63415780a03329307c0997b2670cEvan Cheng 1822d28617de2b0b731c08d1af9e830f31e14ac75b4Evan Cheng // Initialize initial frame state. 1832d28617de2b0b731c08d1af9e830f31e14ac75b4Evan Cheng // Calculate amount of bytes used for return address storing 1842d28617de2b0b731c08d1af9e830f31e14ac75b4Evan Cheng int stackGrowth = is64Bit ? -8 : -4; 1851abf2cb59b8d63415780a03329307c0997b2670cEvan Cheng 1862d28617de2b0b731c08d1af9e830f31e14ac75b4Evan Cheng // Initial state of the frame pointer is esp+stackGrowth. 1874a971705bc6030dc2e4338b3cd5cffa2e0f88b7bRafael Espindola unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP; 1884a971705bc6030dc2e4338b3cd5cffa2e0f88b7bRafael Espindola MCCFIInstruction Inst = MCCFIInstruction::createDefCfa( 189dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth); 1904a971705bc6030dc2e4338b3cd5cffa2e0f88b7bRafael Espindola MAI->addInitialFrameState(Inst); 1912d28617de2b0b731c08d1af9e830f31e14ac75b4Evan Cheng 1922d28617de2b0b731c08d1af9e830f31e14ac75b4Evan Cheng // Add return address to move list 1934a971705bc6030dc2e4338b3cd5cffa2e0f88b7bRafael Espindola unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP; 1944a971705bc6030dc2e4338b3cd5cffa2e0f88b7bRafael Espindola MCCFIInstruction Inst2 = MCCFIInstruction::createOffset( 195dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth); 1964a971705bc6030dc2e4338b3cd5cffa2e0f88b7bRafael Espindola MAI->addInitialFrameState(Inst2); 1972d28617de2b0b731c08d1af9e830f31e14ac75b4Evan Cheng 1982d28617de2b0b731c08d1af9e830f31e14ac75b4Evan Cheng return MAI; 1991abf2cb59b8d63415780a03329307c0997b2670cEvan Cheng} 2001abf2cb59b8d63415780a03329307c0997b2670cEvan Cheng 201de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarstatic void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM, 202de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar CodeModel::Model &CM) { 203f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar bool is64Bit = TT.getArch() == Triple::x86_64; 204439661395fd2a2a832dba01c65bc88718528313cEvan Cheng 20534ad6db8b958fdc0d38e122edf753b5326e69b03Evan Cheng // For static codegen, if we're not already set, use Small codegen. 20634ad6db8b958fdc0d38e122edf753b5326e69b03Evan Cheng if (CM == CodeModel::Default) 20734ad6db8b958fdc0d38e122edf753b5326e69b03Evan Cheng CM = CodeModel::Small; 20834ad6db8b958fdc0d38e122edf753b5326e69b03Evan Cheng else if (CM == CodeModel::JITDefault) 20934ad6db8b958fdc0d38e122edf753b5326e69b03Evan Cheng // 64-bit JIT places everything in the same buffer except external funcs. 21034ad6db8b958fdc0d38e122edf753b5326e69b03Evan Cheng CM = is64Bit ? CodeModel::Large : CodeModel::Small; 211439661395fd2a2a832dba01c65bc88718528313cEvan Cheng} 212439661395fd2a2a832dba01c65bc88718528313cEvan Cheng 2130c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarstatic MCInstPrinter *createX86MCInstPrinter(const Triple &T, 2144b64e8a9e13ba782da2034e1dee52f077bdb759cEvan Cheng unsigned SyntaxVariant, 215b950585cc5a0d665e9accfe5ce490cd269756f2eJames Molloy const MCAsmInfo &MAI, 21617463b3ef1a3d39b10619254f12e806c8c43f9e7Craig Topper const MCInstrInfo &MII, 2170c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar const MCRegisterInfo &MRI) { 2184b64e8a9e13ba782da2034e1dee52f077bdb759cEvan Cheng if (SyntaxVariant == 0) 2190c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return new X86ATTInstPrinter(MAI, MII, MRI); 2204b64e8a9e13ba782da2034e1dee52f077bdb759cEvan Cheng if (SyntaxVariant == 1) 22117463b3ef1a3d39b10619254f12e806c8c43f9e7Craig Topper return new X86IntelInstPrinter(MAI, MII, MRI); 222dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 2234b64e8a9e13ba782da2034e1dee52f077bdb759cEvan Cheng} 2244b64e8a9e13ba782da2034e1dee52f077bdb759cEvan Cheng 2256948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainarstatic MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple, 226de7cbbfcce5c068f0699bdcb6dac093c0c91ba6fQuentin Colombet MCContext &Ctx) { 2272c94d0faa0e1c268893d5e04dc77e8a35889db00Ahmed Bougacha // Default to the stock relocation info. 2286948897e478cbd66626159776a8017b3c18579b9Pirama Arumuga Nainar return llvm::createMCRelocationInfo(TheTriple, Ctx); 2292c94d0faa0e1c268893d5e04dc77e8a35889db00Ahmed Bougacha} 2302c94d0faa0e1c268893d5e04dc77e8a35889db00Ahmed Bougacha 2317801136b95d1fbe515b9655b73ada39b05a33559Evan Chengstatic MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) { 2327801136b95d1fbe515b9655b73ada39b05a33559Evan Cheng return new MCInstrAnalysis(Info); 2337801136b95d1fbe515b9655b73ada39b05a33559Evan Cheng} 2347801136b95d1fbe515b9655b73ada39b05a33559Evan Cheng 235e78085a3c03de648a481e9751c3094c517bd7123Evan Cheng// Force static initialization. 236e78085a3c03de648a481e9751c3094c517bd7123Evan Chengextern "C" void LLVMInitializeX86TargetMC() { 2374c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar for (Target *T : {&TheX86_32Target, &TheX86_64Target}) { 2384c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar // Register the MC asm info. 2394c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo); 2404c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar 2414c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar // Register the MC codegen info. 242de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar RegisterMCAdjustCodeGenOptsFn Y(*T, adjustCodeGenOpts); 2434c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar 2444c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar // Register the MC instruction info. 2454c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo); 2464c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar 2474c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar // Register the MC register info. 2484c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar TargetRegistry::RegisterMCRegInfo(*T, createX86MCRegisterInfo); 2494c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar 2504c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar // Register the MC subtarget info. 2514c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar TargetRegistry::RegisterMCSubtargetInfo(*T, 2524c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar X86_MC::createX86MCSubtargetInfo); 2534c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar 2544c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar // Register the MC instruction analyzer. 2554c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar TargetRegistry::RegisterMCInstrAnalysis(*T, createX86MCInstrAnalysis); 2564c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar 2574c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar // Register the code emitter. 2584c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar TargetRegistry::RegisterMCCodeEmitter(*T, createX86MCCodeEmitter); 2594c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar 2604c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar // Register the object streamer. 2614c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar TargetRegistry::RegisterCOFFStreamer(*T, createX86WinCOFFStreamer); 2624c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar 2634c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar // Register the MCInstPrinter. 2644c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar TargetRegistry::RegisterMCInstPrinter(*T, createX86MCInstPrinter); 2654c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar 2664c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar // Register the MC relocation info. 2674c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo); 2684c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar } 269a87e40f16f1c3117412e01107807e490d6fb29bcEvan Cheng 270a87e40f16f1c3117412e01107807e490d6fb29bcEvan Cheng // Register the asm backend. 27178c10eeaa57d1c6c4b7781d3c0bcb0cfbbc43b5cEvan Cheng TargetRegistry::RegisterMCAsmBackend(TheX86_32Target, 27278c10eeaa57d1c6c4b7781d3c0bcb0cfbbc43b5cEvan Cheng createX86_32AsmBackend); 27378c10eeaa57d1c6c4b7781d3c0bcb0cfbbc43b5cEvan Cheng TargetRegistry::RegisterMCAsmBackend(TheX86_64Target, 27478c10eeaa57d1c6c4b7781d3c0bcb0cfbbc43b5cEvan Cheng createX86_64AsmBackend); 275439661395fd2a2a832dba01c65bc88718528313cEvan Cheng} 276de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 277de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarunsigned llvm::getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size, 278de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool High) { 279de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar switch (Size) { 280de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar default: return 0; 281de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case 8: 282de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (High) { 283de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar switch (Reg) { 284de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar default: return getX86SubSuperRegisterOrZero(Reg, 64); 285de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 286de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::SI; 287de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 288de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::DI; 289de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 290de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::BP; 291de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 292de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::SP; 293de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 294de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::AH; 295de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 296de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::DH; 297de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 298de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::CH; 299de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 300de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::BH; 301de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 302de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } else { 303de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar switch (Reg) { 304de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar default: return 0; 305de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 306de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::AL; 307de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 308de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::DL; 309de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 310de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::CL; 311de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 312de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::BL; 313de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 314de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::SIL; 315de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 316de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::DIL; 317de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 318de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::BPL; 319de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 320de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::SPL; 321de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 322de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R8B; 323de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 324de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R9B; 325de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 326de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R10B; 327de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 328de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R11B; 329de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 330de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R12B; 331de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 332de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R13B; 333de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 334de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R14B; 335de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 336de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R15B; 337de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 338de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 339de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case 16: 340de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar switch (Reg) { 341de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar default: return 0; 342de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 343de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::AX; 344de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 345de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::DX; 346de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 347de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::CX; 348de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 349de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::BX; 350de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 351de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::SI; 352de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 353de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::DI; 354de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 355de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::BP; 356de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 357de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::SP; 358de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 359de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R8W; 360de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 361de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R9W; 362de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 363de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R10W; 364de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 365de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R11W; 366de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 367de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R12W; 368de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 369de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R13W; 370de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 371de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R14W; 372de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 373de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R15W; 374de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 375de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case 32: 376de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar switch (Reg) { 377de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar default: return 0; 378de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 379de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::EAX; 380de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 381de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::EDX; 382de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 383de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::ECX; 384de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 385de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::EBX; 386de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 387de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::ESI; 388de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 389de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::EDI; 390de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 391de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::EBP; 392de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 393de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::ESP; 394de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 395de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R8D; 396de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 397de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R9D; 398de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 399de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R10D; 400de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 401de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R11D; 402de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 403de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R12D; 404de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 405de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R13D; 406de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 407de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R14D; 408de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 409de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R15D; 410de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 411de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case 64: 412de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar switch (Reg) { 413de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar default: return 0; 414de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 415de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::RAX; 416de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 417de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::RDX; 418de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 419de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::RCX; 420de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 421de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::RBX; 422de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 423de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::RSI; 424de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 425de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::RDI; 426de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 427de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::RBP; 428de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 429de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::RSP; 430de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 431de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R8; 432de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 433de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R9; 434de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 435de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R10; 436de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 437de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R11; 438de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 439de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R12; 440de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 441de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R13; 442de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 443de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R14; 444de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 445de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return X86::R15; 446de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 447de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 448de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar} 449de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 450de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarunsigned llvm::getX86SubSuperRegister(unsigned Reg, unsigned Size, bool High) { 451de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned Res = getX86SubSuperRegisterOrZero(Reg, Size, High); 452de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar assert(Res != 0 && "Unexpected register or VT"); 453de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return Res; 454de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar} 455de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 456de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 457