1de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar//===-- X86FixupBWInsts.cpp - Fixup Byte or Word instructions -----------===// 2de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// 3de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// The LLVM Compiler Infrastructure 4de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// 5de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// This file is distributed under the University of Illinois Open Source 6de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// License. See LICENSE.TXT for details. 7de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// 8de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar//===----------------------------------------------------------------------===// 9de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// \file 10de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// This file defines the pass that looks through the machine instructions 11de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// late in the compilation, and finds byte or word instructions that 12de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// can be profitably replaced with 32 bit instructions that give equivalent 13de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// results for the bits of the results that are used. There are two possible 14de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// reasons to do this. 15de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// 16de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// One reason is to avoid false-dependences on the upper portions 17de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// of the registers. Only instructions that have a destination register 18de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// which is not in any of the source registers can be affected by this. 19de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// Any instruction where one of the source registers is also the destination 20de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// register is unaffected, because it has a true dependence on the source 21de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// register already. So, this consideration primarily affects load 22de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// instructions and register-to-register moves. It would 23de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// seem like cmov(s) would also be affected, but because of the way cmov is 24de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// really implemented by most machines as reading both the destination and 25de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// and source regsters, and then "merging" the two based on a condition, 26de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// it really already should be considered as having a true dependence on the 27de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// destination register as well. 28de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// 29de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// The other reason to do this is for potential code size savings. Word 30de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// operations need an extra override byte compared to their 32 bit 31de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// versions. So this can convert many word operations to their larger 32de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// size, saving a byte in encoding. This could introduce partial register 33de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// dependences where none existed however. As an example take: 34de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// orw ax, $0x1000 35de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// addw ax, $3 36de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// now if this were to get transformed into 37de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// orw ax, $1000 38de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// addl eax, $3 39de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// because the addl encodes shorter than the addw, this would introduce 40de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// a use of a register that was only partially written earlier. On older 41de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// Intel processors this can be quite a performance penalty, so this should 42de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// probably only be done when it can be proven that a new partial dependence 43de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// wouldn't be created, or when your know a newer processor is being 44de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// targeted, or when optimizing for minimum code size. 45de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// 46de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar//===----------------------------------------------------------------------===// 47de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 48de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#include "X86.h" 49de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#include "X86InstrInfo.h" 50de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#include "X86Subtarget.h" 51de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#include "llvm/ADT/Statistic.h" 52de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#include "llvm/CodeGen/LivePhysRegs.h" 53de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#include "llvm/CodeGen/MachineFunctionPass.h" 54de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#include "llvm/CodeGen/MachineInstrBuilder.h" 55de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#include "llvm/CodeGen/MachineLoopInfo.h" 56de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#include "llvm/CodeGen/MachineRegisterInfo.h" 57de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#include "llvm/CodeGen/Passes.h" 58de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#include "llvm/Support/Debug.h" 59de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#include "llvm/Support/raw_ostream.h" 60de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#include "llvm/Target/TargetInstrInfo.h" 61de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarusing namespace llvm; 62de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 63de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#define FIXUPBW_DESC "X86 Byte/Word Instruction Fixup" 64de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#define FIXUPBW_NAME "x86-fixup-bw-insts" 65de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 66de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#define DEBUG_TYPE FIXUPBW_NAME 67de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 68de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// Option to allow this optimization pass to have fine-grained control. 69de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// This is turned off by default so as not to affect a large number of 70de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// existing lit tests. 71de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarstatic cl::opt<bool> 72de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar FixupBWInsts("fixup-byte-word-insts", 73de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar cl::desc("Change byte and word instructions to larger sizes"), 74de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar cl::init(true), cl::Hidden); 75de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 76de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarnamespace { 77de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarclass FixupBWInstPass : public MachineFunctionPass { 78de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar /// Loop over all of the instructions in the basic block replacing applicable 79de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar /// byte or word instructions with better alternatives. 80de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar void processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB); 81de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 82de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar /// This sets the \p SuperDestReg to the 32 bit super reg of the original 83de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar /// destination register of the MachineInstr passed in. It returns true if 84de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar /// that super register is dead just prior to \p OrigMI, and false if not. 85de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool getSuperRegDestIfDead(MachineInstr *OrigMI, 86de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned &SuperDestReg) const; 87de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 88de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar /// Change the MachineInstr \p MI into the equivalent extending load to 32 bit 89de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar /// register if it is safe to do so. Return the replacement instruction if 90de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar /// OK, otherwise return nullptr. 91de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineInstr *tryReplaceLoad(unsigned New32BitOpcode, MachineInstr *MI) const; 92de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 93de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar /// Change the MachineInstr \p MI into the equivalent 32-bit copy if it is 94de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar /// safe to do so. Return the replacement instruction if OK, otherwise return 95de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar /// nullptr. 96de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineInstr *tryReplaceCopy(MachineInstr *MI) const; 97de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 98de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Change the MachineInstr \p MI into an eqivalent 32 bit instruction if 99de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // possible. Return the replacement instruction if OK, return nullptr 100de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // otherwise. Set WasCandidate to true or false depending on whether the 101de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // MI was a candidate for this sort of transformation. 102de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineInstr *tryReplaceInstr(MachineInstr *MI, MachineBasicBlock &MBB, 103de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool &WasCandidate) const; 104de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarpublic: 105de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar static char ID; 106de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 107de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar const char *getPassName() const override { 108de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return FIXUPBW_DESC; 109de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 110de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 111de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar FixupBWInstPass() : MachineFunctionPass(ID) { 112de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar initializeFixupBWInstPassPass(*PassRegistry::getPassRegistry()); 113de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 114de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 115de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar void getAnalysisUsage(AnalysisUsage &AU) const override { 116de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar AU.addRequired<MachineLoopInfo>(); // Machine loop info is used to 117de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // guide some heuristics. 118de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineFunctionPass::getAnalysisUsage(AU); 119de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 120de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 121de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar /// Loop over all of the basic blocks, replacing byte and word instructions by 122de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar /// equivalent 32 bit instructions where performance or code size can be 123de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar /// improved. 124de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool runOnMachineFunction(MachineFunction &MF) override; 125de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 126de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineFunctionProperties getRequiredProperties() const override { 127de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return MachineFunctionProperties().set( 128de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineFunctionProperties::Property::AllVRegsAllocated); 129de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 130de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 131de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarprivate: 132de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineFunction *MF; 133de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 134de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar /// Machine instruction info used throughout the class. 135de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar const X86InstrInfo *TII; 136de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 137de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar /// Local member for function's OptForSize attribute. 138de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool OptForSize; 139de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 140de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar /// Machine loop info used for guiding some heruistics. 141de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineLoopInfo *MLI; 142de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 143de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar /// Register Liveness information after the current instruction. 144de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar LivePhysRegs LiveRegs; 145de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar}; 146de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarchar FixupBWInstPass::ID = 0; 147de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar} 148de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 149de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga NainarINITIALIZE_PASS(FixupBWInstPass, FIXUPBW_NAME, FIXUPBW_DESC, false, false) 150de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 151de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga NainarFunctionPass *llvm::createX86FixupBWInsts() { return new FixupBWInstPass(); } 152de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 153de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarbool FixupBWInstPass::runOnMachineFunction(MachineFunction &MF) { 154de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (!FixupBWInsts || skipFunction(*MF.getFunction())) 155de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return false; 156de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 157de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar this->MF = &MF; 158de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar TII = MF.getSubtarget<X86Subtarget>().getInstrInfo(); 159de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar OptForSize = MF.getFunction()->optForSize(); 160de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MLI = &getAnalysis<MachineLoopInfo>(); 161de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar LiveRegs.init(&TII->getRegisterInfo()); 162de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 163de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar DEBUG(dbgs() << "Start X86FixupBWInsts\n";); 164de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 165de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Process all basic blocks. 166de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (auto &MBB : MF) 167de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar processBasicBlock(MF, MBB); 168de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 169de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar DEBUG(dbgs() << "End X86FixupBWInsts\n";); 170de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 171de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return true; 172de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar} 173de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 174de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// TODO: This method of analysis can miss some legal cases, because the 175de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// super-register could be live into the address expression for a memory 176de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// reference for the instruction, and still be killed/last used by the 177de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// instruction. However, the existing query interfaces don't seem to 178de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// easily allow that to be checked. 179de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// 180de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// What we'd really like to know is whether after OrigMI, the 181de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// only portion of SuperDestReg that is alive is the portion that 182de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// was the destination register of OrigMI. 183de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarbool FixupBWInstPass::getSuperRegDestIfDead(MachineInstr *OrigMI, 184de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned &SuperDestReg) const { 185de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar auto *TRI = &TII->getRegisterInfo(); 186de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 187de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned OrigDestReg = OrigMI->getOperand(0).getReg(); 188de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar SuperDestReg = getX86SubSuperRegister(OrigDestReg, 32); 189de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 190de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg); 191de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 192de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Make sure that the sub-register that this instruction has as its 193de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // destination is the lowest order sub-register of the super-register. 194de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // If it isn't, then the register isn't really dead even if the 195de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // super-register is considered dead. 196de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (SubRegIdx == X86::sub_8bit_hi) 197de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return false; 198de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 199de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (LiveRegs.contains(SuperDestReg)) 200de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return false; 201de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 202de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (SubRegIdx == X86::sub_8bit) { 203de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // In the case of byte registers, we also have to check that the upper 204de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // byte register is also dead. That is considered to be independent of 205de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // whether the super-register is dead. 206de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned UpperByteReg = 207de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar getX86SubSuperRegister(SuperDestReg, 8, /*High=*/true); 208de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 209de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (LiveRegs.contains(UpperByteReg)) 210de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return false; 211de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 212de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 213de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return true; 214de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar} 215de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 216de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga NainarMachineInstr *FixupBWInstPass::tryReplaceLoad(unsigned New32BitOpcode, 217de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineInstr *MI) const { 218de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned NewDestReg; 219de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 220de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // We are going to try to rewrite this load to a larger zero-extending 221de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // load. This is safe if all portions of the 32 bit super-register 222de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // of the original destination register, except for the original destination 223de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // register are dead. getSuperRegDestIfDead checks that. 224de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (!getSuperRegDestIfDead(MI, NewDestReg)) 225de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return nullptr; 226de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 227de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Safe to change the instruction. 228de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineInstrBuilder MIB = 229de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar BuildMI(*MF, MI->getDebugLoc(), TII->get(New32BitOpcode), NewDestReg); 230de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 231de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned NumArgs = MI->getNumOperands(); 232de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (unsigned i = 1; i < NumArgs; ++i) 233de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MIB.addOperand(MI->getOperand(i)); 234de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 235de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 236de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 237de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return MIB; 238de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar} 239de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 240de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga NainarMachineInstr *FixupBWInstPass::tryReplaceCopy(MachineInstr *MI) const { 241de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar assert(MI->getNumExplicitOperands() == 2); 242de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar auto &OldDest = MI->getOperand(0); 243de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar auto &OldSrc = MI->getOperand(1); 244de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 245de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned NewDestReg; 246de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (!getSuperRegDestIfDead(MI, NewDestReg)) 247de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return nullptr; 248de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 249de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned NewSrcReg = getX86SubSuperRegister(OldSrc.getReg(), 32); 250de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 251de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // This is only correct if we access the same subregister index: otherwise, 252de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // we could try to replace "movb %ah, %al" with "movl %eax, %eax". 253de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar auto *TRI = &TII->getRegisterInfo(); 254de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (TRI->getSubRegIndex(NewSrcReg, OldSrc.getReg()) != 255de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar TRI->getSubRegIndex(NewDestReg, OldDest.getReg())) 256de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return nullptr; 257de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 258de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Safe to change the instruction. 259de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Don't set src flags, as we don't know if we're also killing the superreg. 260de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // However, the superregister might not be defined; make it explicit that 261de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // we don't care about the higher bits by reading it as Undef, and adding 262de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // an imp-use on the original subregister. 263de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineInstrBuilder MIB = 264de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar BuildMI(*MF, MI->getDebugLoc(), TII->get(X86::MOV32rr), NewDestReg) 265de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar .addReg(NewSrcReg, RegState::Undef) 266de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar .addReg(OldSrc.getReg(), RegState::Implicit); 267de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 268de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Drop imp-defs/uses that would be redundant with the new def/use. 269de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (auto &Op : MI->implicit_operands()) 270de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (Op.getReg() != (Op.isDef() ? NewDestReg : NewSrcReg)) 271de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MIB.addOperand(Op); 272de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 273de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return MIB; 274de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar} 275de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 276de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga NainarMachineInstr *FixupBWInstPass::tryReplaceInstr( 277de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineInstr *MI, MachineBasicBlock &MBB, 278de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool &WasCandidate) const { 279de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineInstr *NewMI = nullptr; 280de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar WasCandidate = false; 281de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 282de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // See if this is an instruction of the type we are currently looking for. 283de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar switch (MI->getOpcode()) { 284de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 285de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::MOV8rm: 286de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Only replace 8 bit loads with the zero extending versions if 287de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // in an inner most loop and not optimizing for size. This takes 288de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // an extra byte to encode, and provides limited performance upside. 289de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (MachineLoop *ML = MLI->getLoopFor(&MBB)) { 290de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (ML->begin() == ML->end() && !OptForSize) { 291de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar NewMI = tryReplaceLoad(X86::MOVZX32rm8, MI); 292de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar WasCandidate = true; 293de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 294de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 295de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar break; 296de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 297de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::MOV16rm: 298de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Always try to replace 16 bit load with 32 bit zero extending. 299de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Code size is the same, and there is sometimes a perf advantage 300de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // from eliminating a false dependence on the upper portion of 301de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // the register. 302de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar NewMI = tryReplaceLoad(X86::MOVZX32rm16, MI); 303de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar WasCandidate = true; 304de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar break; 305de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 306de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::MOV8rr: 307de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar case X86::MOV16rr: 308de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Always try to replace 8/16 bit copies with a 32 bit copy. 309de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Code size is either less (16) or equal (8), and there is sometimes a 310de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // perf advantage from eliminating a false dependence on the upper portion 311de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // of the register. 312de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar NewMI = tryReplaceCopy(MI); 313de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar WasCandidate = true; 314de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar break; 315de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 316de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar default: 317de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // nothing to do here. 318de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar break; 319de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 320de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 321de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return NewMI; 322de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar} 323de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 324de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarvoid FixupBWInstPass::processBasicBlock(MachineFunction &MF, 325de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineBasicBlock &MBB) { 326de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 327de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // This algorithm doesn't delete the instructions it is replacing 328de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // right away. By leaving the existing instructions in place, the 329de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // register liveness information doesn't change, and this makes the 330de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // analysis that goes on be better than if the replaced instructions 331de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // were immediately removed. 332de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // 333de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // This algorithm always creates a replacement instruction 334de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // and notes that and the original in a data structure, until the 335de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // whole BB has been analyzed. This keeps the replacement instructions 336de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // from making it seem as if the larger register might be live. 337de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar SmallVector<std::pair<MachineInstr *, MachineInstr *>, 8> MIReplacements; 338de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 339de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Start computing liveness for this block. We iterate from the end to be able 340de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // to update this for each instruction. 341de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar LiveRegs.clear(); 342de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // We run after PEI, so we need to AddPristinesAndCSRs. 343de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar LiveRegs.addLiveOuts(MBB); 344de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 345de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool WasCandidate = false; 346de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 347de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (auto I = MBB.rbegin(); I != MBB.rend(); ++I) { 348de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineInstr *MI = &*I; 349de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 350de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineInstr *NewMI = tryReplaceInstr(MI, MBB, WasCandidate); 351de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 352de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Add this to replacements if it was a candidate, even if NewMI is 353de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // nullptr. We will revisit that in a bit. 354de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (WasCandidate) { 355de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MIReplacements.push_back(std::make_pair(MI, NewMI)); 356de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 357de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 358de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // We're done with this instruction, update liveness for the next one. 359de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar LiveRegs.stepBackward(*MI); 360de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 361de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 362de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar while (!MIReplacements.empty()) { 363de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineInstr *MI = MIReplacements.back().first; 364de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineInstr *NewMI = MIReplacements.back().second; 365de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MIReplacements.pop_back(); 366de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (NewMI) { 367de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MBB.insert(MI, NewMI); 368de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MBB.erase(MI); 369de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 370de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 371de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar} 372